NB7V585MMNR4G

NB7V585M 1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator Description Multi−Level Inputs w/ Internal Termination The NB7V585M is a differential 1 −to −6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 9). The NB7V585M produces six identical output copies of clock or data operating up to 6 GHz or 10 Gb/s, respectively. As such, NB7V585M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The 16 mA differential CML output structure provides matching internal 50 W source terminations, 400 mV output swings when externally terminated with a 50 W resistor to VCC (see Figure 14) and is optimized for low skew and minimal jitter. The NB7V585M is powered with either 1.8 V or 2.5 V supply and is offered in a low profile 5x5 mm 32−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7V585M is a member of the GigaComm™ family of high performance clock products. Features http://onsemi.com MARKING DIAGRAM* 1 1 32 QFN32 MN SUFFIX CASE 488AM NB7V 585M AWLYYWW G A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. SIMPLIFIED LOGIC DIAGRAM VCC Q0 Q0 • • • • • • • • • • • • • • • Maximum Input Data Rate > 10 Gb/s Data Dependent Jitter < 10 ps Maximum Input Clock Frequency > 6 GHz Random Clock Jitter < 0.8 ps RMS, Max Low Skew 1:6 CML Outputs, 20 ps Max 2:1 Multi−Level Mux Inputs 175 ps Typical Propagation Delay 50 ps Typical Rise and Fall Times Differential CML Outputs, 330 mV Peak−to−Peak, Typical Operating Range: VCC = 1.71 V to 1.89 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN32 Package, 5 mm x 5 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices SEL VREFAC0 IN0 VT0 IN0 0 Q1 Q1 Q2 Q2 IN1 VT1 IN1 VREFAC1 VCC GND 1 Q3 Q3 Q4 Q4 Q5 Q5 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2009 February, 2009 − Rev. 1 1 Publication Order Number: NB7V585M/D NB7V585M Exposed Pad (EP) Table 1. INPUT SELECT FUNCTION TABLE SEL* 0 CLK Input Selected IN0 IN1 GND VCC SEL Q0 32 IN0 VT0 VREFAC0 1 2 3 4 5 6 7 8 9 GND 31 30 29 28 Q0 27 26 25 24 23 22 21 GND VCC Q2 Q2 Q3 Q3 VCC VCC Q1 Q1 1 *Defaults HIGH when left open. IN0 IN1 VT1 VREFAC1 IN1 NB7V585M 20 19 18 17 GND 10 NC 11 VCC 12 Q5 13 Q5 14 Q4 15 Q4 16 VCC Figure 1. 32−Lead QFN Pinout (Top View) Table 2. PIN DESCRIPTION Pin 1,4 5,8 2,6 31 10 11, 16, 18 23, 25, 30 29, 28 27, 26 22, 21 20, 19 15, 14 13, 12 9, 17, 24, 32 3 7 − Name IN0, IN0 IN1, IN1 VT0, VT1 SEL NC VCC Q0, Q0 Q1, Q1 Q2, Q2 Q3, Q3 Q4, Q4 Q5, Q5 GND VREFAC0 VREFAC1 EP − − LVTTL/LVCMOS Input − − CML Output CML Output CML Output I/O LVPECL, CML, LVDS Input Description Non−inverted, Inverted, Differential Inputs Internal 100 W Center−tapped Termination Pin for IN0/IN0 and IN1/IN1 Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open No Connect Positive Supply Voltage. Non−inverted, Inverted Differential Outputs (Note 1). Non−inverted, Inverted Differential Outputs (Note 1). Non−inverted, Inverted Differential Outputs (Note 1). Negative Supply Voltage, connected to Ground Output Voltage Reference for Capacitor−Coupled Inputs, only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INn/INn input, then, the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source termination resistors. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7V585M Table 3. ATTRIBUTES Characteristics ESD Protection Input Pullup Resistor (RPU) Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 4 kV > 200 V 75 kW Level 1 UL 94 V−0 @ 0.125 in 308 Table 4. MAXIMUM RATINGS Symbol VCC VIO VINPP IIN IOUT IVFREFAC TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input/Output Voltage Differential Input Voltage |INx − INx| Input Current Through RT (50 W Resistor) Output Current VREFAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) (Note 4) Wave Solder Pb−Free 0 lfpm 500 lfpm Standard Board QFN−32 QFN−32 QFN−32 Continuous Surge Condition 1 GND = 0 V GND = 0 V −0.5 v VIO v VCC + 0.5 Condition 2 Rating 3.0 −0.5 to VCC + 0.5 1.89 $40 34 40 $1.5 −40 to +85 −65 to +150 31 27 12 265 Unit V V V mA mA mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7V585M Table 5. DC CHARACTERISTICS − CML OUTPUT VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 5) Symbol POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.65 V VCC = 1.89 V 235 210 260 mA Characteristic Min Typ Max Unit CML OUTPUTS (Note 6) VOH Output HIGH Voltage VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC = 1.8 V VCC – 40 2460 1760 VCC – 500 2000 1300 VCC – 20 2480 1780 VCC – 400 2100 1400 VCC 2500 1800 VCC – 275 2200 1500 mV VOL Output LOW Voltage mV DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figure 6) Vth VIH VIL VISE VREFAC VREFAC Output Reference Voltage @ 100 mA for Capacitor − Coupled Inputs, Only VCC − 625 VCC − 500 VCC − 400 mV Input Threshold Reference Voltage Range (Note 8) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage (VIH − VIL) 1050 Vth + 100 GND 200 VCC − 100 VCC Vth − 100 1200 mV mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 4 and 7) VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Differential Input HIGH Voltage (IN, IN) Differential Input LOW Voltage (IN, IN) Differential Input Voltage (IN, IN) (VIHD − VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) Input HIGH Current IN/IN (VTO / VT1 Open) Input LOW Current IN/IN (VTO / VT1 Open) 1100 GND 100 1050 −150 −150 VCC VCC − 100 1200 VCC − 50 150 150 mV mV mV mV mA mA CONTROL INPUT (SEL Pin) Input HIGH Voltage for Control Pin Input LOW Voltage for Control Pin Input HIGH Current Input LOW Current VCC x 0.65 GND −150 −150 20 5 VCC VCC x 0.35 +150 +150 mV mV mA mA TERMINATION RESISTORS Internal Input Termination Resistor (Measured from INx to VTx) Internal Output Termination Resistor 45 45 50 50 55 55 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs (Qn/Qn) have internal 50 W source termination resistors and must be externally terminated with 50 W to VCCO for proper operation. 7. Vth, VIH, VIL and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7V585M Table 6. AC CHARACTERISTICS VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 11) Symbol fMAX fDATAMAX VOUTPP tPLH, tPHL tPLH TC tSKEW tDC tJITTER VINPP tr, tf Characteristic Maximum Input Clock Frequency, VOUTPP w 200 mV Maximum Operating Input Data Rate (PRBS23) Output Voltage Amplitude (See Figures 4, Note 15) Propagation Delay to Output Differential @ 1 GHz, Measured at Differential Crosspoint Propagation Delay Temperature Coefficient Output − Output Skew (Within Device) (Note 12) Device − Device Skew (tpd Max − tpdmin) Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 4.0 GHz Output Random Jitter (RJ) (Note 13) Deterministic Jitter (DJ) (Note 14) Input Voltage Swing (Differential Configuration) (Note 15) Output Rise/Fall Times @ 1 GHz (20% − 80%) Qn, Qn fin v 6.0 GHz fin v 10 Gbps 100 50 45 50 0.2 fin v 4.0 GHz fin v 6.0 GHz INx/INx to Qn/Qn SEL to Qn Min 6.0 10 250 200 125 400 325 175 200 100 30 50 55 0.8 10 1200 65 250 300 Typ 7.0 Max Unit GHz Gbps mV ps fs/°C ps % ps rms ps pk−pk mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the crosspoint of the outputs. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. 450 OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 INx 250 200 150 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VTx 50 W INx fout, CLOCK OUTPUT FREQUENCY (GHz) 50 W VCC Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical) Figure 3. Input Structure http://onsemi.com 5 NB7V585M INx INx Qn Qn tPLH VOUTPP = VOH(Qn) − VOL(Qn) tPHL VINPP = VIH(INx) − VIL(INx) INx INx VID = |VIHD(IN) − VILD(IN)| VIHD VILD Figure 4. Differential Inputs Driven Differentially Figure 5. AC Reference Measurement INx Vth Vth INx INx INx Figure 6. Differential Input Driven Single−Ended Figure 7. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VCC VCMmax INx VCMR INx VCMmin GND VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHDmin VILDmin Vth IN Vthmin GND Figure 8. Vth Diagram Figure 9. VCMR Diagram NB7V585M VCCO VCC (Receiver) 50 W 50 W Q Q 50 W 50 W 16 mA GND Figure 10. Typical CML Output Structure and Termination http://onsemi.com 6 NB7V585M VCC VCC VCC VCC ZO = 50 W LVPECL Driver VT = VCC − 2 V ZO = 50 W NB7V585M INx 50 W 50 W INx LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB7V585M INx 50 W 50 W INx GND GND GND GND Figure 11. LVPECL Interface Figure 12. LVDS Interface VCC VCC VCC VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB7V585M INx 50 W 50 W INx Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W NB7V585M INx 50 W 50 W INx GND GND GND Figure 13. Standard 50 W Load CML Interface Figure 14. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) GND *VREFAC bypassed to ground with a 0.01 mF capacitor ORDERING INFORMATION Device NB7V585MMNG NB7V585MMNR4G Package QFN32 (Pb−Free) QFN32 (Pb−Free) Shipping† 74 Units / Rail 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB7V585M PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O D A B 2X 2X 0.15 C 0.15 C 0.10 C 32 X 0.08 C L 32 X b 0.10 C A B 32 X 0.05 C BOTTOM VIEW GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÉÉ TOP VIEW SIDE VIEW 9 8 PIN ONE LOCATION E NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 (A3) A A1 C EXPOSED PAD 16 SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L SOLDERING FOOTPRINT* 5.30 3.20 0.63 32 X D2 K 17 32 X E2 1 32 25 24 3.20 5.30 e 32 X 0.28 0.50 PITCH 28 X *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 NB7V585M/D