NB6L572MMNR4G

NB6L572M 2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator Multi−Level Inputs w/ Internal Termination http://onsemi.com Description The NB6L572M is a high performance differential 4:1 Clock / Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that operates up to 6 GHz / 8 Gbps respectively with a 2.5 V or 3.3 V power supply. The differential Clock / Data inputs have internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The NB6L572M incorporates a pair of Select pins that will choose one of four differential inputs and will produce two identical CML output copies of Clock or Data. As such, the NB6L572M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The two differential CML outputs will swing 400 mV when externally loaded and terminated with a 50 W resistor to VCC and are optimized for low skew and minimal jitter. The NB6L572M is offered in a low profile 5x5mm 32−pin QFN Pb−Free package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6L572M is a member of the ECLinPS MAX™ family of high performance clock products. Features • • • • • • • • November, 2009 − Rev. 1 1 1 32 QFN32 MN SUFFIX CASE 488AM NB6L 572M AWLYYWWG G A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. • Differential CML Outputs, 400 mV Peak−to−Peak, Input Data Rate > 8 Gb/s Typical Data Dependent Jitter < 10 ps Maximum Input Clock Frequency > 6 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:2 CML Outputs, < 15 ps max 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML LVDS 200 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times © Semiconductor Components Industries, LLC, 2009 MARKING DIAGRAM • • • • • • 1 Typical Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN−32 Package, 5mm x 5mm 40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices Publication Order Number: NB6L572M/D NB6L572M Multilevel Inputs LVPECL, LVDS, CML IN0 VT0 IN0 50 W 0 50 W VREFAC0 IN1 VT1 IN1 CML Outputs 50 W IN2 IN2 Q0 4:1 MUX VREFAC1 VT2 Q0 1 50 W 50 W Q1 2 50 W Q1 VREFAC2 IN3 VT3 IN3 50 W 3 50 W VREFAC3 SEL0 SEL1 IN3 VREFAC3 VT3 IN3 IN2 VREFAC2 VT2 IN2 Figure 1. Simplified Block Diagram 32 31 30 29 28 27 26 25 Table 1. INPUT SELECT FUNCTION TABLE Exposed Pad (EP) SEL1* SEL0* Clock / Data Input Selected 0 0 IN0 Input Selected IN0 1 24 GND 0 1 IN1 Input Selected VT0 2 23 VCC 1 0 IN2 Input Selected VREFAC0 3 22 Q1 1 1 IN3 Input Selected IN0 4 21 Q1 IN1 5 20 VCC VT1 6 19 NC VREFAC1 7 18 SEL1 IN1 8 17 VCC 9 10 11 12 13 14 15 16 GND VCC Q0 Q0 VCC NC SEL0 VCC NB6L572M *Defaults HIGH when left open. Figure 2. Pinout: QFN−32 (Top View) http://onsemi.com 2 NB6L572M Table 2. PIN DESCRIPTION Pin Number Pin Name I/O 1, 4 5, 8 25, 28 29, 32 IN0, IN0 IN1, IN1 IN2, IN2 IN3, IN3 LVPECL, CML, LVDS Input Pin Description 2, 6 26, 30 VT0, VT1 VT2, VT3 15 18 SEL0 SEL1 LVTTL/LVCMOS Input 14, 19 NC − No Connect 10, 13, 16 17, 20, 23 VCC − Positive Supply Voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation. 11, 12 21, 22 Q0, Q0 Q1, Q1 CML Output 9, 24 GND 3 7 27 31 VREF−AC0 VREF−AC1 VREF−AC2 VREF−AC3 − Output Voltage Reference for Capacitor−Coupled Inputs − EP − The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND. Non−inverted, Inverted, Differential Clock or Data Inputs Internal 100 W Center−tapped Termination Pin for INx/INx Input Select pins, default HIGH when left open through a 131 kW pullup resistor. Input logic threshold is VCC/2. See Select Function, Table 1. Non−inverted, Inverted Differential Outputs. Negative Supply Voltage, connected to Ground 1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation. 2. All VCC, and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 3 NB6L572M Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 2 kV > 200 V RPU − SELx Input Pull−up Resistor 131 kW Moisture Sensitivity (Note 3) Flammability Rating QFN−32 Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 275 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V −0.5 V to +4.0 V VIN Positive Input Voltage GND = 0 V −0.5 to VCC +0.5 V VINPP Differential Input Voltage |IN – INx| 1.89 V Iout Output Current Through RT (50 W Resistor) $40 mA IIN Input current Through RT (50 W resistor) $40 mA IVREFAC VREFAC Sink or Source Current $1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) QFN32 QFN32 31 27 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 4) QFN32 12 °C/W Tsol Wave Solder 265 °C 0 lfpm 500 lfpm v 20 sec Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB6L572M Table 5. DC CHARACTERISTICS CML OUTPUT VCC = 2.375 V to 3.6 V , GND = 0 V, TA = −40°C to +85°C (Note 5) Symbol Characteristic Min Typ Max Unit 3.0 2.375 3.3 2.5 3.6 2.625 V 130 115 165 150 mA VCC – 30 3270 2470 VCC – 10 3290 2490 VCC 3300 2500 mV VCC – 650 2650 VCC – 650 1850 VCC – 450 2850 VCC – 450 2050 VCC – 300 3000 VCC – 300 2200 mV POWER SUPPLY VCC Power Supply Voltage VCC = 3.3 V VCC = 2.5 V ICC Power Supply Current for VCC (Inputs and Outputs Open) VCC = 3.3 V VCC = 2.5 V CML OUTPUTS (Note 6) VOH Output HIGH Voltage VOL Output LOW Voltage VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 5 & 6) (Note 8) VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth – 100 mV Vth Input Threshold Reference Voltage Range (Note 8) 1100 VCC – 100 mV VISE Single−ended Input Voltage (VIH – VIL) 200 1200 mV Output Reference Voltage (100 mA Load) 1050 VCC – 1050 mV VREFAC VREF−AC VCC – 1250 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9) VIHD Differential Input HIGH Voltage (IN, IN) 1200 VCC mV VILD Differential Input LOW Voltage (IN, IN) 0 VIHD – 100 mV VID Differential Input Voltage (IN, IN) (VIHD – VILD) 100 1200 mV VCMR Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) 1050 VCC – 50 mV IIH Input HIGH Current IN / INx (VTIN / VTINx Open) −150 150 mA IIL Input LOW Current IN / INx (VTIN / VTINx Open) −150 150 mA CONTROL INPUT (SELx Pin) VIH Input HIGH Voltage for Control Pin VCC x 0.65 VCC V VIL Input LOW Voltage for Control Pin GND VCC x 0.35 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA TERMINATION RESISTORS RTIN Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and Output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB6L572M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 11) Symbol Characteristic Min Typ 5 6 GHz Maximum Operating Data Rate NRZ, (PRBS23) 6.5 8 Gbps fSEL Maximum Toggle Frequency, SELx 20 40 MHz VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 5 GHz (Note 12) (Figure 10) 250 400 mV tPLH, tPHL Propagation Delay to Differential Outputs Measured at Differential Crosspoint 125 200 4 tPD Tempco Differential Propagation Delay Temperature Coefficient tskew Output – Output skew (within device) (Note 13) Device – Device skew (tpdmax – tpdmin) tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin = 1 GHz FN Phase Noise, fin = 1 GHz tŐFN tJITTER fMAX Maximum Input Clock Frequency VOUT w 250 mV fDATAMAX @ 1 GHz INx/INx to Qx/Qx @ 50 MHz SELx to Qx Max 250 10 100 45 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz Unit ps ns Dfs/°C 0 5 15 25 ps 50 55 % −134 −136 −149 −150 −150 −150 dBc Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS) 35 fs Random Clock Jitter, RJ(RMS) (Note 14) Deterministic Jitter, DJ (Note 15) (FR4 ≤ 12’) 0.2 1 0.8 5 ps RMS ps pk−pk 0.35 0.7 ps RMS 1200 mV 50 ps fin ≤ 5 GHz fin ≤ 6.5 Gbps Crosstalk Induced Jitter (Adjacent Channel) (Note 16) VINPP Input Voltage Swing (Differential Configuration) (Note 17) 100 tr,, tf Output Rise/Fall Times @ 1 GHz; (20% − 80%), VIN = 400 mV Qx, Qx 20 35 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Output voltage swing is a single−ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 16. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. 17. Input voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 600 Q AMP (mV) 500 400 300 200 100 0 0 1 2 3 4 5 6 7 fin, CLOCK INPUT FREQUENCY (GHz) 8 Figure 3. Clock Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 6 NB6L572M VCC IN VIH Vth INx VIL 50 W IN VTx Vth 50 W INx Figure 5. Differential Input Driven Single−Ended Figure 4. Input Structure VCC VIHmax Vthmax Vth VILmax IN VIH Vth VIL IN IN VIHmin Vthmin VILmin GND Figure 6. Vth Diagram Figure 7. Differential Inputs Driven Differentially VCC VIHDmax VILDmax VCMmax IN IN IN VID = |VIHD(IN) − VILD(IN)| VCMR VIHD VIHDtyp VILDtyp IN VILD VID = VIHD − VILD VIHDmin VCMmin VILDmin GND Figure 9. VCMR Diagram Figure 8. Differential Inputs Driven Differentially IN VCC / 2 VINPP = VIH(IN) − VIL(IN) IN VCC / 2 SELx tpd Q VOUTPP = VOH(Q) − VOL(Q) Q tpd Q Q tPHL tPLH Figure 11. SELx to Qx Timing Diagram Figure 10. AC Reference Measurement http://onsemi.com 7 NB6L572M VCC VCC NB6L572M IN Zo = 50 W 50 W LVDS Driver 50 W Zo = 50 W VT = OPEN 50 W Zo = 50 W IN CLKx GND IN CLKx Figure 12. LVPECL Interface GND GND VCC VCC VCC VCC NB6L572M IN Zo = 50 W 50 W CML Driver 50 W Differential Driver VT = VCC 50 W Zo = 50 W Zo = 50 W NB6L572M VCC (Receiver) 50 W Q GND *VREFAC bypassed to ground with a 0.01 mF capacitor. Receiver VCCO IN Figure 15. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) Figure 14. Standard 50 W Load CML Interface NB6L572M 50 W GND GND 50 W VT = VREFAC* IN GND GND Figure 13. LVDS Interface NB6L572M IN Zo = 50 W NB6L572M IN Zo = 50 W 50 W VT = VCC − 2.0 V LVPECL Driver VCC VCC 50 W VCC = 2.5 V 50 W 50 W 50 W Q Q Q 50 W 16 mA 16 mA GND GND Figure 16. Typical CML Output Structure and Termination (VCC = 2.5 V or 3.3 V) 50 W 50 W GND Figure 17. Alternative Output Termination (VCC = 2.5 V, Only) DEVICE ORDERING INFORMATION Package Shipping† NB6L572MMNG QFN−32 (Pb−Free) 74 Units / Rail NB6L572MMNR4G QFN−32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ECLinPS MAX is a trademark of Semiconductor Component Industries, LLC (SCILLC). http://onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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