NTTFS3A08PZTWG

NTTFS3A08PZ Power MOSFET −20 V, −15 A, Single P−Channel, m8FL Features • Ultra Low RDS(on) to Minimize Conduction Losses • m8FL 3.3 x 3.3 x 0.8 mm for Space Saving and Excellent Thermal Conduction • ESD Protection Level of 5 kV per JESD22−A114 • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com V(BR)DSS RDS(on) MAX 6.7 mW @ −4.5 V −20 V Applications ID MAX −15 A 9.0 mW @ −2.5 V • Battery Switch • High Side Load Switch • Optimized for Power Management Applications for Portable P−Channel MOSFET S Products such as Media Tablets, Ultrabook PCs and Cellphones MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C Continuous Drain Current RqJA ≤ 10 s (Note 1) TA = 25°C Power Dissipation RqJA ≤ 10 s (Note 1) Symbol Value Unit VDSS −20 V VGS ±8 V ID −15 A TA = 85°C Steady State PD ID TA = 85°C MARKING DIAGRAM 2.3 W A −22 −16 PD 4.9 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID −9 A Power Dissipation RqJA (Note 2) TA = 25°C PD 0.84 TA = 25°C, tp = 10 ms IDM −46 A TJ, Tstg −55 to +150 °C VESD 5000 V TA = 85°C Operating Junction and Storage Temperature ESD (HBM, JESD22−A114) −7 W IS −3 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. October, 2012 − Rev. 2 1 1 S S S G 1 WDFN8 (m8FL) CASE 511AB 3A08 A Y WW G 3A08 AYWWG G D D D D = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NTTFS3A08PZTAG WDFN8 (Pb−Free) 1500 / Tape & Reel NTTFS3A08PZTWG WDFN8 (Pb−Free) 5000 / Tape & Reel Device Source Current (Body Diode) © Semiconductor Components Industries, LLC, 2012 D −11 TA = 25°C Pulsed Drain Current G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTTFS3A08P/D NTTFS3A08PZ THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Ambient – Steady State (Note 3) Parameter RqJA 55 °C/W Junction−to−Ambient – Steady State (Note 4) RqJA 148 Junction−to−Ambient – (t ≤ 10 s) (Note 3) RqJA 26 3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size (40 mm2, 1 oz. Cu). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA −20 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS V 6 Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = −16 V Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±5 V VGS(TH) VGS = VDS, ID = −250 mA TJ = 25°C mV/°C −1 mA ±5 mA −1.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS −0.4 3.3 mV/°C VGS = −4.5 V ID = −12 A 4.9 6.7 VGS = −2.5 V ID = −10 A 6.9 9.0 VDS = −1.5 V, ID = −8 A mW 62 S 5000 pF CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance VGS = 0 V, f = 1.0 MHz, VDS = −10 V 600 Crss 540 Total Gate Charge QG(TOT) 56 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 15.4 td(on) 13 VGS = −4.5 V, VDS = −10 V, ID = −8 A nC 2.0 6.5 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = −4.5 V, VDS = −10 V, ID = −8 A, RG = 6.0 W tf ns 60 250 170 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = −3 A TJ = 25°C −0.65 207 VGS = 0 V, dIS/dt = 100 A/ms, IS = −6 A QRR http://onsemi.com 2 V ns 45 162 234 5. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. −1.0 nC NTTFS3A08PZ TYPICAL CHARACTERISTICS VDS ≤ −10 V −ID, DRAIN CURRENT (A) 50 −4.5 V to −2.5 V 40 VGS = −1.8 V 30 20 10 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 60 −2 V 0 0.5 1.0 1.5 20 TJ = −55°C 10 0 0.5 1.0 1.5 2.0 Figure 2. Transfer Characteristics TJ = 25°C ID = −12 A 0.07 0.06 0.05 0.04 0.03 0.02 1.5 2.0 2.5 3.0 3.5 4.0 4.5 −VGS, GATE VOLTAGE (V) 0.015 TJ = 25°C 2.5 VGS = −1.8 V 0.010 VGS = −2.5 V VGS = −4.5 V 0.005 0 0 10 20 30 40 −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100,000 1.6 VGS = −4.5 V ID = −12.0 A TJ = 125°C 1.4 −IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE (W) TJ = 25°C Figure 1. On−Region Characteristics 0.08 1.5 TJ = 125°C 30 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.09 1.0 40 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.10 0.01 0 50 0 2.0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) 60 1.3 10,000 1.2 1.1 1.0 0.9 TJ = 85°C 1000 0.8 0.7 −50 −25 0 25 50 75 100 125 150 100 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTTFS3A08PZ VGS = 0 V TJ = 25°C f = 1 MHz C, CAPACITANCE (pF) 6400 Ciss 5600 4800 4000 3200 2400 Coss 1600 800 0 Crss 0 2 4 6 8 10 12 14 16 18 20 5 18 QT 16 4 14 VGS 12 3 10 VDS 2 QGS 8 QGD 1 0 0 10 6 VDS = −10 V ID = −8 A TJ = 25°C 20 30 40 4 2 50 60 0 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 1000 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 8000 7200 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 10 −IS, SOURCE CURRENT (A) TJ = 25°C t, TIME (ns) td(off) 100 tf tr td(on) 10 VGS = −4.5 V VDD = −10 V ID = −8 A 1 1 10 0.1 100 TJ = −55°C 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 0.95 400 0.85 350 ID = −250 mA 0.75 300 0.65 POWER (W) −VGS(th) (V) TJ = 125°C 1 0.55 0.45 250 200 150 0.35 100 0.25 50 0.15 −50 −25 0 25 50 75 100 125 0 150 1.E−04 1.E−02 1.E+00 1.E+02 TJ, TEMPERATURE (°C) SINGLE PULSE TIME (s) Figure 11. Threshold Voltage Figure 12. Single Pulse Maximum Power Dissipation http://onsemi.com 4 NTTFS3A08PZ TYPICAL CHARACTERISTICS −ID, DRAIN CURRENT (A) 100 100 ms 10 1 ms 10 ms VGS = −8 V Single Pulse TC = 25°C 1 0.1 0.01 dc RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 100 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 60 RqJA = 55°C/W 50 40 30 Duty Cycle = 0.5 20 10 0 0.20 0.05 0.02 0.01 0.10 1E−06 Single Pulse 1E−05 1E−04 1E−03 1E−02 1E−01 t, TIME (s) Figure 14. FET Thermal Response http://onsemi.com 5 1E+00 1E+01 1E+02 1E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN8 3.3x3.3, 0.65P CASE 511AB ISSUE D 1 SCALE 2:1 DATE 23 APR 2012 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A D1 B 2X 0.20 C 8 7 6 5 4X E1 E q c 1 2 3 4 A1 TOP VIEW 0.10 C A e SIDE VIEW 0.10 8X b C A B 0.05 C 4X DETAIL A 8X e/2 1 0.42 4 INCHES NOM 0.030 −−− 0.012 0.008 0.130 BSC 0.116 0.120 0.078 0.083 0.130 BSC 0.116 0.120 0.058 0.063 0.009 0.012 0.026 BSC 0.012 0.016 0.026 0.032 0.012 0.017 0.002 0.005 0.055 0.059 0_ −−− MIN 0.028 0.000 0.009 0.006 MAX 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.016 0.020 0.037 0.022 0.008 0.063 12 _ 0.65 PITCH PACKAGE OUTLINE 4X 0.66 M E3 8 5 D2 BOTTOM VIEW 1 3.60 L1 GENERIC MARKING DIAGRAM* XXXXX A Y WW G MILLIMETERS MIN NOM MAX 0.70 0.75 0.80 0.00 −−− 0.05 0.23 0.30 0.40 0.15 0.20 0.25 3.30 BSC 2.95 3.05 3.15 1.98 2.11 2.24 3.30 BSC 2.95 3.05 3.15 1.47 1.60 1.73 0.23 0.30 0.40 0.65 BSC 0.30 0.41 0.51 0.65 0.80 0.95 0.30 0.43 0.56 0.06 0.13 0.20 1.40 1.50 1.60 0_ −−− 12 _ SOLDERING FOOTPRINT* L G SEATING PLANE DETAIL A K E2 C 6X 0.10 C DIM A A1 b c D D1 D2 E E1 E2 E3 e G K L L1 M q XXXXX AYWWG G 0.75 2.30 0.57 0.47 2.37 3.46 DIMENSION: MILLIMETERS = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON30561E WDFN8 3.3X3.3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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