SI53154-A01AGMR

Si53154 PCI-E XPRESS G EN 1, G EN 2, G EN 3, AND G EN 4 Q UAD F ANOUT B UFFER Features       PCI-Express Gen 1, Gen 2, Gen 3,  and Gen 4 common clock compliant  Supports Serial ATA (SATA) at  100 MHz  100–210 MHz operation Low power, push pull, differential  output buffers Internal termination for maximum  integration  Dedicated output enable pin for each output Four PCI-Express buffered clock outputs Clock input spread tolerable Supports LVDS outputs I2C support with readback capabilities Extended temperature: –40 to 85 °C 3.3 V power supply 24-pin QFN package Ordering Information: See page 17. Applications 24 22 21 20 SCLK 19 VDD 1 18 OE3* OE1* 2 17 VDD VDD 3 VSS 4 OE2* 5 VDD 6 16 DIFF3 25 GND 15 DIFF3 14 DIFF2 8 9 10 11 12 DIFF0 DIFF0 DIFF1 DIFF1 VDD 13 DIFF2 7 OE0* The Si53154 is a spread spectrum tolerant PCIe clock buffer that can source four PCIe clocks simultaneously. The device has four hardware output enable control inputs for enabling the respective differential outputs on the fly. The device also features output enable control through I2C communication. I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, compliment, or both differential signals on the clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. 23 VDD Description SDATA Wireless access point  Routers DIFFIN Pin Assignments  VSS Network attached storage  Multi-function printers DIFFIN  *Note: Internal 100 kohm pull-up. Patents pending Functional Block Diagram DIFF0 DIFF1 DIFFIN DIFFIN DIFF2 DIFF3 SCLK SDATA Control & Memory Control RAM OE [3:0] Rev. 1.3 4/16 Copyright © 2016 by Silicon Laboratories Si53154 Si53154 2 Rev. 1.3 Si53154 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Rev. 1.3 3 Si53154 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ± 5% 3.135 — 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — – V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (Single-Ended Outputs) VOH IOH = –1 mA 2.4 — — V 3.3 V Output Low Voltage (Single-Ended Outputs) VOL IOL = 1 mA — — 0.4 V High-impedance Output Current IOZ –10 — 10 A Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH — — 35 mA Output Pin Capacitance Pin Inductance Dynamic Supply Current in Fanout Mode 4 IDD_3.3V Differential clocks with 5” traces and 2 pF load, frequency at 100 MHz Rev. 1.3 Si53154 Table 2. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit 100 — 210 MHz 0.6 — 4 V/ns DIFFIN at 0.7 V Input Frequency Range Rising and Falling Slew Rates for Each Clock Output Signal in a Given Differential Pair fin TR / TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) Differential Input High Voltage VIH 150 — — mV Differential Input Low Voltage VIL — — –150 mV Crossing Point Voltage at 0.7 V Swing VOX Single-ended measurement 250 — 550 mV Vcross Variation over all Edges VOX Single-ended measurement — — 140 mV VRB –100 — 100 mV TSTABLE 500 — — ps Absolute Maximum Input Voltage VMAX — — 1.15 V Absolute Minimum Input Voltage VMIN –0.3 — — V Duty Cycle for Each Clock Output Signal in a Given Differential Pair TDC Measured at crossing point VOX 45 — 55 % Rise/Fall Matching TRFM Determined as a fraction of 2 x (TR – TF)/(TR + TF) — — 20 % Duty Cycle TDC Measured at 0 V differential 45 — 55 % Clock Skew TSKEW Measured at 0 V differential — — 50 ps Additive Peak Jitter Pk-Pk 0 — 10 ps 10 kHz < F < 1.5 MHz 0 — 0.5 ps 1.5 MHz< F < Nyquist Rate 0 — 0.5 ps Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 — 0.10 ps Differential Ringback Voltage Time before Ringback Allowed DIFF at 0.7 V Additive PCIe Gen 2 Phase Jitter RMSGEN2 Additive PCIe Gen 3 Phase Jitter RMSGEN3 Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Rev. 1.3 5 Si53154 Table 2. AC Electrical Specifications (Continued) Parameter Symbol Condition Min Typ Max Unit Additive PCIe Gen 4 Phase Jitter RMSGEN4 PCIe Gen 4 — — 0.10 ps Additive Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 20 50 ps Long-term Accuracy LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew rate TR/TF Measured differentially from ±150 mV 2.5 — 8 V/ns 300 — 550 mV — — 5 ms 10.0 — — ns Crossing Point Voltage at 0.7 V Swing VOX Enable/Disable and Setup Clock Stabilization from Power-Up TSTABLE Stopclock Set-up Time TSS Measured from the point when both VDD and clock input are valid Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Industrial Temperature, Operating Ambient TA Functional –40 — 85 °C Commercial Temperature, Operating Ambient TA Functional 0 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 25 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESDHBM JEDEC (JESD 22 - A114) 2000 — – V UL-94 UL (Class) Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating V–0 Note: Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 Rev. 1.3 Si53154 2. Functional Description 2.1. OE Pin Definition The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins are required to be driven at all times even though they have an internal 100 k resistor. 2.2. OE Assertion The OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles. 2.3. OE Deassertion When the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final output state is driven low. Rev. 1.3 7 Si53154 3. Test and Measurement Setup Figures 1–3 show the test load configuration for differential clock signals. Figure 1. 0.7 V Differential Load Configuration Figure 2. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) 8 Rev. 1.3 Si53154 VMIN = –0.30V VMIN = –0.30V Figure 3. Single-Ended Measurement for Differential Output Signals (for AC Parameters Measurement) Rev. 1.3 9 Si53154 4. Control Registers 4.1. I2C Interface To enhance the flexibility and function of the clock buffer, an I2C interface is provided. Through the I2C Interface, various device functions are available, such as individual clock output enable. The registers associated with the I2C Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. Power management functions can only be programed in program mode and not in normal operation modes. 4.2. Data Protocol The I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The block write and block read protocol is outlined in Table 4 while Table 5 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 4. Block Read and Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... 10 Block Write Protocol Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Byte Count–8 bits Acknowledge from slave Data byte 1–8 bits Acknowledge from slave Data byte 2–8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N–8 bits Acknowledge from slave Stop Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Rev. 1.3 Block Read Protocol Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Read = 1 Acknowledge from slave Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits Acknowledge Data bytes from slave/Acknowledge Data Byte N from slave–8 bits NOT Acknowledge Stop Si53154 Table 5. Byte Read and Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Byte Write Protocol Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Data byte–8 bits Acknowledge from slave Stop Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Rev. 1.3 Byte Read Protocol Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits Read Acknowledge from slave Data from slave–8 bits NOT Acknowledge Stop 11 Si53154 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W D2 D1 D0 Name Type Reset settings = 00000000 Bit Name Function 7:0 Reserved Control Register 1. Byte 1 Bit D7 D6 D5 D4 D3 Name Type DIFF0_OE R/W R/W R/W R/W R/W Reset settings = 00000101 Bit Name 7:3 Reserved 2 DIFF0_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 1 Reserved 0 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. 12 Rev. 1.3 R/W DIFF1_OE R/W R/W Si53154 Control Register 2. Byte 2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W DIFF2_OE DIFF3_OE R/W R/W Reset settings = 11000000 Bit Name Function 7 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 6 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. 5:0 Reserved Control Register 3. Byte 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 00001000 Bit Name Function 7:4 Rev Code Bit 3:0 Program Revision Code. 3:0 Vendor ID bit 3:0 Vendor Identification Code. Control Register 4. Byte 4 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name BC7 BC7 BC5 BC4 BC3 BC2 BC1 BC0 Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 00000110 Bit Name 7:0 BC7:0 Function Byte Count Register. Rev. 1.3 13 Si53154 Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W Reset settings = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 14 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV Rev. 1.3 011: 600 mV 111: 1000 mV Si53154 24 23 22 21 20 SCLK SDATA VDD DIFFIN DIFFIN VSS 5. Pin Descriptions: 24-Pin QFN 19 VDD 1 18 OE3* OE1* 2 17 VDD VDD 3 VSS 4 OE2* 5 VDD 6 16 DIFF3 25 GND 15 DIFF3 14 DIFF2 7 8 9 10 11 12 OE0* DIFF0 DIFF0 DIFF1 DIFF1 VDD 13 DIFF2 *Note: Internal 100 kohm pull-up. Figure 4. 24-Pin QFN Table 6. Si53154 24-Pin QFN Descriptions Pin # Name Type Description 1 VDD PWR 3.3 V power supply. 2 OE1 I,PU 3 VDD PWR 3.3 V power supply. 4 VSS GND Ground. 5 OE2 I,PU Active high input pin enables DIFF2 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 6 VDD PWR 3.3 V power supply. 7 OE0 I,PU 8 DIFF0 O, DIF 0.7 V, differential clock output. 9 DIFF0 O, DIF 0.7 V, differential clock output. 10 DIFF1 O, DIF 0.7 V, differential clock output. 11 DIFF1 O, DIF 0.7 V, differential clock output. 12 VDD 13 DIFF2 Active high input pin enables DIFF1 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. Active high input pin enables DIFF0 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. PWR 3.3 V power supply. O, DIF 0.7 V, differential clock output. Rev. 1.3 15 Si53154 Table 6. Si53154 24-Pin QFN Descriptions Pin # Name 14 DIFF2 O, DIF 0.7 V, differential clock output. 15 DIFF3 O, DIF 0.7 V, differential clock output. 16 DIFF3 O, DIF 0.7 V, differential clock output. 17 VDD PWR 3.3 V power supply. 18 OE3 I,PU 19 SCLK I 20 SDATA I/O 21 VDD 22 DIFFIN I 0.7 V Differential True Input, typically 100 MHz. Input frequency range 100 to 210 MHz. 23 DIFFIN O 0.7 V Differential Complement Input, typically 100 MHz. Input frequency range 100 to 210 MHz. 24 VSS GND Ground. 25 GND GND Ground for bottom pad of the IC. 16 Type Description Active high input pin enables DIFF3 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. SMBus compatible SCLOCK. SMBus compatible SDATA. PWR 3.3 V power supply. Rev. 1.3 Si53154 6. Ordering Guide Part Number Package Type Temperature Si53154-A01AGM 24-pin QFN Extended, –40 to 85 C Si53154-A01AGMR 24-pin QFN—Tape and Reel Extended, –40 to 85 C Lead-free Rev. 1.3 17 Si53154 7. Package Outline Figure 5 illustrates the package details for the Si53154. Table 7 lists the values for the dimensions shown in the illustration. Figure 5. 24-Pin Quad Flat No Lead (QFN) Package Table 7. Package Diagram Dimensions Symbol Millimeters Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.20 0.25 0.30 D D2 4.00 BSC 2.60 2.70 e 0.50 BSC E 4.00 BSC 2.80 E2 2.60 2.70 2.80 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components 18 Rev. 1.3 Si53154 8. Land Pattern Figure 6 illustrates the recommended land pattern details for the Si53154 in a 24-pin QFN package. Table 8 lists the values for the dimensions shown in the illustration. Figure 6. Land Pattern Rev. 1.3 19 Si53154 Table 8. PCB Land Pattern Dimensions Dimension Unit mm C1 4.0 C2 4.0 E 0.50 BSC X1 0.30 X2 2.70 Y1 0.80 Y2 2.70 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x2 array of 1.10mm x 1.10mm openings on 1.30mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 20 Rev. 1.3 Si53154 DOCUMENT CHANGE LIST Revision 0.1 to Revision 1.0  Updated Features and Description. Updated Table 2.  Updated Table 3.  Updated Section 4.1.  Revision 1.0 to Revision 1.1  Updated Features on page 1  Updated Description on page 1.  Updated specs in Table 2, “AC Electrical Specifications,” on page 5.  Added Land Pattern Revision 1.1 to Revision 1.2  Added condition for Clock Stabilization from Powerup, TSTABLE, in Table 2. Revision 1.2 to Revision 1.3  Updated Theta JC to 25°C/W. Rev. 1.3 21 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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