BlueNRG-LP
Datasheet
Programmable Bluetooth® Low Energy wireless SoC
Features
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Product status link
BlueNRG-LP
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Product summary
Order code
BlueNRG-3x5yz
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Bluetooth Low Energy system-on-chip supporting Bluetooth 5.2
specifications
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2 Mbps data rate
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Long range (Coded PHY)
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Advertising extensions
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Channel selection algorithm #2
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GATT caching
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LE Ping procedure
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Periodic advertising and periodic advertising sync transfer
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LE L2CAP connection-oriented channel
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LE power control and path loss monitoring
Radio
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RX sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps
(long range)
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Programmable output power up to +8 dBm (at antenna connector)
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Data rate supported: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps
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128 physical connections
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Integrated balun
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Support for external PA
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BlueNRG core coprocessor (DMA based) for Bluetooth Low
Energy timing critical operation
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2.4 GHz proprietary radio driver
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Suitable for systems requiring compliance with the following radio
frequency regulations: ETSI EN 300 328, EN 300 440, FCC
CFR47 part 15, ARIB STD-T66
Ultra-low power radio performance
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10 nA in SHUTDOWN mode (1.8 V)
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0.6 uA in DEEPSTOP mode (with external LSE and BLE wake-up
sources, 1.8 V)
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0.9 uA in DEEPSTOP mode (with internal LSI and BLE wake-up
sources, 1.8 V)
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4.3 mA peak current in TX (@ 0 dBm, 3.3 V)
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3.4 mA peak current in RX (@ sensitivity level, 3.3V)
High performance and ultra-low power Cortex-M0+ 32-bit, running up to 64
MHz
Dynamic current consumption: 18 µA/MHz
Operating supply voltage: from 1.7 to 3.6 V
-40 ºC to 105 ºC temperature range
Supply and reset management
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High efficiency embedded SMPS step-down converter with
intelligent bypass mode
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Ultra-low power power-on-reset (POR) and power-down-reset
(PDR)
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Programmable voltage detector (PVD)
Clock sources
DS13282 - Rev 5 - April 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
BlueNRG-LP
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Fail safe 32 MHz crystal oscillator with integrated trimming capacitors
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32 kHz crystal oscillator
Internal low-power 32 kHz RO
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On-chip non-volatile Flash memory of 256 kB
On-chip RAM of 64 kB or 32 kB
One-time-programmable (OTP) memory area of 1 kB
Embedded UART bootloader
Ultra-low power modes with or without timer and RAM retention
Quadrature decoder
Enhanced security mechanisms such as:
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Flash read/write protection
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SWD disabling
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Secure bootloader
Security features
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True random number generator (RNG)
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Hardware encryption AES maximum 128-bit security co-processor
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HW public key accelerator (PKA)
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CRC calculation unit
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64-bit unique ID
System peripherals
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1x DMA controller with 8 channels supporting ADC, SPI, I2C, USART and LPUART
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1x SPI
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2x SPI/I2S
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2x I2C (SMBus/PMBus)
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1x PDM (digital microphone interface)
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1x LPUART
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1x USART (ISO 7816 smartcard mode, IrDA, SPI Master and Modbus)
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1x independent WDG
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1x real time clock (RTC)
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1x independent SysTick
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1x 16-bit, 6 channel advanced timer
Up to 32 fast I/Os
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28 of them with wake-up capability
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31 of them 5 V tolerant
Analog peripherals
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12-bit ADC with 8 input channels, up to 16 bits with a decimation filter
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Battery monitoring
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Analog watchdog
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Analog Mic I/F with PGA
Development support
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Serial wire debug (SWD)
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4 breakpoints and 2 watchpoints
All packages are ECOPACK2 compliant
Applications
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DS13282 - Rev 5
Industrial
Home and industrial automation
Smart lighting
page 2/73
BlueNRG-LP
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Fitness,wellness and sports
Healthcare, consumer medical
Security/proximity
Remote control
Assisted living
Mobile phone peripherals
PC peripherals
Description
The BlueNRG-LP is an ultra-low power programmable Bluetooth® Low Energy wireless SoC solution. It embeds
STMicroelectronics’s state-of-art 2.4 GHz RF radio IPs combining unparalleled performance with extremely longbattery lifetime. It is compliant with Bluetooth® Low Energy SIG core specification version 5.2 addressing point-topoint connectivity and Bluetooth Mesh networking and allows large-scale device networks to be established in a
reliable way. The BlueNRG-LP is also suitable for 2.4 GHz proprietary radio wireless communication to address
ultra-low latency applications.
The BlueNRG-LP embeds a Cortex®-M0+ microcontroller that can operate up to 64 MHz and also the BlueNRG
core coprocessor (DMA based) for Bluetooth Low Energy timing critical operations.
The main Bluetooth® Low Energy 5.2 specification supported features are:
2 Mbps data rate, long range (Coded PHY), advertising extensions, channel selection algorithm #2, GATT
caching, hardware support for simultaneous connection, master/slave and multiple roles simultaneously, extended
packet length support.
In addition, the BlueNRG-LP provides enhanced security hardware support by dedicated hardware functions:
True random number generator (RNG), encryption AES maximum 128-bit security co-processor, public key
accelerator (PKA), CRC calculation unit, 64-bit unique ID, Flash memory read and write protection.
The BlueNRG-LP can be configured to support standalone or network processor applications. In the first
configuration, the BlueNRG-LP operates as single device in the application for managing both the application
code and the Bluetooth Low Energy stack.
The BlueNRG-LP embeds high-speed and flexible memory types:
Flash memory of 256 kB, RAM memory of 64 kB, one-time-programmable (OTP) memory area of 1 kB, ROM
memory of 7 kB.
Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA
channels with a full flexible channel mapping by the DMAMUX peripheral.
The BlueNRG-LP embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to three
internal sources, including battery monitoring and a temperature sensor.
The BlueNRG-LP has a low-power RTC and one advanced 16-bit timer.
The BlueNRG-LP features standard and advanced communication interfaces:
1x SPI, 2x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode), IrDA and Modbus mode, 2x
I2C supporting SMBus/PMBus, 1x channel PDM.
The BlueNRG-LP operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A
comprehensive set of power-saving modes enables the design of low-power applications.
The BlueNRG-LP integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with a
fixed threshold that generates a device reset when the VDD drops under 1.65 V.
The BlueNRG-LP comes in different package versions supporting up to:
32 I/Os for the QFN48 package, 20 I/Os for the QFN32 package, 30 I/Os for the WCSP49 package.
DS13282 - Rev 5
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BlueNRG-LP
Figure 1. The BlueNRG-LP block diagram
256 kB Flash
JTAG/SWD
NVIC
SRAM0
Cortex-M0+
SRAM1
SRAM2
DMA (8 ch)
MR_BLE
AHB Lite
DMAMUX
SRAM3
PKA + RAM
RNG
PWRC
RCC
LSE
32 kHz
GPIO0
LSI
32 kHz
GPIO1
CRC
SYSCFG
ADC
APB
HSE
32 MHz
RC64MPLL
RTC
IWDG
TIM1
Power supply/POR/
PDR/PVD
DS13282 - Rev 5
SPI1
SPI2/I2S2
SPI3/I2S3
I2C1
I2C2
USART
LPUART
page 4/73
BlueNRG-LP
Functional overview
1
Functional overview
1.1
System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
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Three masters:
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– CPU (Cortex®-M0+) core S-bus
– DMA1
– Radio system
Nine slaves:
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Internal Flash memory on CPU (Cortex®-M0+) S bus
Internal SRAM0 (16 kB)
Internal SRAM1 (16 kB)
Internal SRAM2 (16 kB)
Internal SRAM3 (16 kB)
APB0 peripherals (through an AHB to APB bridge)
APB1 peripherals (through an AHB to APB bridge)
AHB0 peripherals
AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even
when several high-speed peripherals work simultaneously.
Figure 2. Bus matrix
DS13282 - Rev 5
page 5/73
BlueNRG-LP
ARM Cortex–M0+ core with MPU
1.2
ARM Cortex–M0+ core with MPU
The BlueNRG-LP contains an ARM Cortex-M0+ microcontroller core. The Cortex-M0+ was developed to provide
a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-power
consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The Cortex-M0+ can run from 1 MHz up to 64 MHz.
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage
pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but
powerful instruction set and extensively optimized design, providing high-end processing hardware including a
single-cycle multiplier.
The interrupts are handled by the Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls
specific Cortex-M0+ interrupts as well as the BlueNRG-LP peripheral interrupts. With its embedded ARM core, the
BlueNRG-LP family is compatible with all ARM tools and software.
1.3
Memories
1.3.1
Embedded Flash memory
The Flash controller implements the erase and program Flash memory operation. The flash controller also
implements the read and write protection.
The Flash memory features are:
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Memory organization:
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– 1 bank of 256 kB
– Page size: 2 kB
– Page number 128
32-bit wide data read/write
Page erase and mass erase
The Flash controller features are:
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1.3.2
Flash memory read operations
Flash memory write operations: single data write or 4x32-bits burst write
Flash memory erase operations
Page write protect mechanism
Embedded SRAM
The BlueNRG-LP has a total of 64 kB of embedded SRAM, split into four banks as shown in the following table:
Table 1. SRAM overview
1.3.3
SRAM bank
Size
Address
Retained in DEEPSTOP
SRAM0
16 kB
0x2000 0000
Always
SRAM1
16 kB
0x2000 4000
Programmable by the user
SRAM2
16 kB
0x2000 8000
Programmable by the user
SRAM3
16 kB
0x2000 C000
Programmable by the user
Embedded ROM
The BlueNRG-LP has a total of 7 kB of embedded ROM. This area is ST reserved and contains:
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1.3.4
The UART bootloader from which the CPU boots after each reset (first 6 kB of ROM memory)
Some ST reserved values including the ADC trimming values (the last 1 kB of ROM memory)
Embedded OTP
The one-time-programmable (OTP) is a memory of 1 kB dedicated for user data. The OTP data cannot be
erased.
DS13282 - Rev 5
page 6/73
BlueNRG-LP
Security and safety
The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a
system reset. This operation freezes the OTP memory from further unwanted write operations.
1.3.5
Memory protection unit (MPU)
The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory
or resources used by any other active task. This memory area is organized into up to 8 protected areas. The
protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against
the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program
accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area settings, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
1.4
Security and safety
The BlueNRG-LP contains many security blocks for the BLE and the host application.
It includes:
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Flash read/write protections
As protection against potential hacker attacks, the SWD access can be disabled
Secure bootloader (refer to the dedicated BlueNRG-LP UART bootloader protocol application note AN5471)
Customer storage of the BLE keys
True random number generator (RNG)
Private key accelerator (PKA) including:
– Elliptic curve Diffie-Hellman (ECDH) public-private key pair calculation accelerator
– Based on the Montgomery method for fast modular multiplications
– Built-in Montgomery domain inward and outward transformations
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1.5
◦ AMBA AHB lite slave interface with a reduced command set
Cyclic redundancy check calculation unit (CRC)
RF subsystem
The BlueNRG-LP embeds an ultra-low power radio, compliant with Bluetooth® Low Energy (BLE) specification.
The BLE features 1 Mbps and 2 Mbps transfer rates as well as long range options (125 kbps, 500 kbps), supports
multiple roles simultaneously acting at the same time as Bluetooth® Low Energy sensor and hub device.
The BLE protocol stack is implemented by an efficient system partitioned as follows:
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1.5.1
Hardware part: BlueCore handling time critical and time consuming BLE protocol parts
Firmware part: Arm® Cortex®-M0+ core handling non time critical BLE protocol parts
RF front-end block diagram
The RF front-end is based on a direct modulation of the carrier in TX, and uses a low IF architecture in RX mode.
Thanks to an internal transformer with RF pins, the circuit directly interfaces the antenna (single ended
connection, impedance close to 50 Ω). The natural band pass behavior of the internal transformer simplifies
outside circuitry aimed at harmonic filtering and out of band interferer rejection.
In transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the
power amplifier. A linearized, smoothed analog control offers a clean power ramp-up.
In receive mode, the automatic gain control (AGC) can reduce the chain gain at both RF and IF locations, for
optimized interferer rejections. Thanks to the use of complex filtering and highly accurate I/Q architecture, high
sensitivity and excellent linearity can be achieved.
DS13282 - Rev 5
page 7/73
BlueNRG-LP
RF subsystem
Figure 3. BlueNRG-LP RF block diagram
Timer and Power
control
AGC
control
AGC
TX_SEQUENCE
RF control
ADC
RX_SEQUENCE
Interrupt
Wakeup
AHB
BLE
controller
APB
BLE
modulator
G
BP
filter
ADC
LNA
G
RF1
BLE
demodulator
PLL
See
notes
PA
Adjust
PA ramp
generator
Adjust
HSE
SMPS
VDDSD VSSSD VLXSD
LDO
LDO
LDO
VFBSD
Max PA
level
Trimmed
bias
VDDRF
Notes: QFN42 and QFN48: VSS through exposed pad, and VSSRF pins must be connected to ground plane.
CSP49: VSSRF pins must be connected to ground plane.
DS13282 - Rev 5
page 8/73
BlueNRG-LP
Power supply management
1.6
1.6.1
Power supply management
SMPS step-down regulator
The device integrates a step-down converter to improve low power performance when the VDD voltage is high
enough. The SMPS output voltage can be programmed from 1.2 V to 1.90 V. It is internally clocked at 4 MHz or 8
MHz.
The device can be operated without the SMPS by just wiring its output to VDD. This is the case for applications
where the voltage is low, or where the power consumption is not critical.
Except for the configuration SMPS OFF, an L/C BOM must be present on the board and connected to the VFBSD
pad.
Figure 4. Power supply configuration
DS13282 - Rev 5
page 9/73
BlueNRG-LP
Power supply management
1.6.2
Power supply schemes
The BlueNRG-LP embeds three power domains:
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VDD33 (VDDIO or VDD):
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– the voltage range is between 1.7 V and 3.6 V
– it supplies a part of the I/O ring, the embedded regulators and the system analog IPs as power
management block and embedded oscillators
VDD12o:
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– always-on digital power domain
– this domain is generally supplied at 1.2 V during active phase of the device
– this domain is supplied at 1.0 V during low power mode (DEEPSTOP)
VDD12i:
– interruptible digital power domain
– this domain is generally supplied at 1.2 V during active phase of the device
– this domain is shut down during low power mode (DEEPSTOP)
Figure 5. Power supply domain overview
VDDIO
VFBSD
SMPS
VREG PAD
VGATEN
CMDNO
CMDNI
VGATEP
MLDO
LP-Reg
V33 Domain
(VDDIO)
HSE, LSI, LSE
PDR, POR, PVD
PWRC33,
RCC33
1.6.3
VDD12O
AlwaysOn
Domain
(VDD12O)
HSI
BLE_wakeup,
RTC, WDOG,
PWRCo,
RCCo
VDD12I
RFLDOs
VRF
Interruptible domain
(VDD12I)
CPU
RF_FSM
BLE
Peripherals
RCCi
Analog
RF
Linear voltage regulators
The digital power supplies are provided by different regulators:
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The main LDO (MLDO):
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– it provides 1.2 V from a 1.4-3.3 V input voltage
– it supplies both VDD12i and VDD12o when the device is active
– it is disabled during the low power mode (DEEPSTOP)
Low power LDO (LPREG):
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– it stays enabled during both active and low power phases
– it provides 1.0 V voltage
– it is not connected to the digital domain when the device is active
– it is connected to the VDD12o domain during low power mode (DEEPSTOP)
A dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block
An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).
DS13282 - Rev 5
page 10/73
BlueNRG-LP
Operating modes
1.6.4
Power supply supervisor
The BlueNRG-LP device embeds several power voltage monitoring:
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1.7
Power-on-reset (POR): during the power-on, the device remains in reset mode if VDDIO is below a VPOR
threshold (typically 1.65 V)
Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply voltage
(VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always enabled
Power voltage detector (PVD): can be used to monitor the VDDIO (against a programmed threshold) or
an external analog input signal. When the feature is enabled and the PVD measures a voltage below the
comparator, an interrupt is generated (if unmasked)
Operating modes
Several operating modes are defined for the BlueNRG-LP:
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RUN mode
DEEPSTOP mode
SHUTDOWN mode
Table 2. Relationship between the low power modes and functional blocks
1.7.1
Mode
SHUTDOWN
DEEPSTOP
IDLE
RUN
CPU
OFF
OFF
OFF
ON
Flash
OFF
OFF
ON
ON
RAM
OFF
ON/OFF granularity 16 kB
ON/OFF
ON/OFF
Radio
OFF
OFF
ON/OFF
ON/OFF
Supply system
OFF
OFF
ON ( DC-DC ON/OFF)
ON ( DC-DC ON/OFF)
Register retention
OFF
ON
ON
ON
HS clock
OFF
OFF
ON
ON
LS clock
OFF
ON/OFF
ON
ON
Peripherals
OFF
OFF
ON/OFF
ON/OFF
Wake-on RTC
OFF
ON/OFF
ON/OFF
NA
Wake-on GPIOs
OFF
ON/OFF
ON/OFF
NA
Wake-on reset pin
ON
ON
ON
NA
RUN mode
In RUN mode the BlueNRG-LP is fully operational:
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All interfaces are active
The internal power supplies are active
The system clock and the bus clock are running
The CPU core and the radio can be used
The power consumption may be reduced by gating the clock of the unused peripherals.
1.7.2
DEEPSTOP mode
The DEEPSTOP is the only low power mode of the BlueNRG-LP allowing the restart from a saved context
environment and the application at wake-up to go on running.
The conditions to enter the DEEPSTOP mode are:
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The radio is sleeping (no radio activity)
The CPU is sleeping (WFI with SLEEPDEEP bit activated)
No unmasked wake-up sources are active
The low power mode selection (LPMS) bit of the power controller unit is 0 (default)
In DEEPSTOP mode:
DS13282 - Rev 5
page 11/73
BlueNRG-LP
Operating modes
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The system and the bus clocks are stopped
Only the essential digital power domain is ON and supplied at 1.0 V
The bank RAM0 is kept in retention
The other banks of RAM can be in retention or not, depending on the software configuration
The low speed clock can be running or stopped, depending on the software configuration:
– ON or OFF
– Sourced by LSE or by LSI
The RTC and the IWDG stay active, if enabled and the low speed clock is ON
The I/Os pull-up and pull-down can be controlled during DEEPSTOP mode, depending on the software
configuration
The radio wake-up block, including its timer, stay active (if enabled and the low speed clock is ON)
Eight I/Os (PA4/ PA5/ PA6/ PA7/ PA8/ PA9/ PA10/ PA11) can be in output driving:
– A static low or high level
– The low speed clock
– The RTC output
Possible wake-up sources are:
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The radio block is able to generate two events to wake up the system through its embedded wake-up timer
running on low speed clock:
– Radio wake-up time is reached
– CPU host wake-up time is reached
The RTC can generate a wake-up event
The IWDG can generate a reset event
Up to 28 GPIOs are able to wake up the system (PA0 to PA15 and PB0 to PB11)
At the wake-up, all the hardware resources located in the digital power domain that are OFF during the
DEEPSTOP mode, are reset. The CPU reboots. The wake-up reason is visible in the register of the power
controller.
1.7.3
SHUTDOWN mode
The SHUTDOWN mode is the least power consuming mode.
The conditions to enter SHUTDOWN mode are the same conditions needed to enter DEEPSTOP mode except
that the LPMS bit of the power controller unit is 1.
In SHUTDOWN mode, the BlueNRG-LP is in ultra-low power consumption: all voltage regulators, clocks and the
RF interface are not powered. The BlueNRG-LP can enter shutdown mode by internal software sequence. The
only way to exit shutdown mode is by asserting and deasserting the RSTN pin.
In SHUTDOWN mode:
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The system is powered down as both the regulators are OFF
The VDDIO power domain is ON
All the clocks are OFF, LSI and LSE are OFF
The I/Os pull-up and pull-down can be controlled during SHUTDOWN mode, depending on the software
configuration
The only wake-up source is a low pulse on the RSTN pin
The exit from SHUTDOWN is similar to a POR startup. The PDR feature can be enabled or disabled during
SHUTDOWN.
DS13282 - Rev 5
page 12/73
BlueNRG-LP
Reset management
1.8
Reset management
The BlueNRG-LP offers two different resets:
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The PORESETn: this reset is provided by the low power management unit (LPMU) analog block and
corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset
impacts all resources of the BlueNRG-LP. The exit from SHUTDOWN mode is equivalent to a POR and thus
generates a PORESETn. The PORESETn signal is active when the power supply of the device is below a
threshold value or when the regulator does not provide the target voltage.
The PADRESETn (system reset): this reset is built through several sources:
– PORESETn
– Reset due to the watchdog
The BlueNRG-LP device embeds a watchdog timer, which may be used to recover from software crashes
– Reset due to CPU Lockup
The Cortex-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an
unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex-M0+
– Software system reset
The system reset request is generated by the debug circuitry of the Cortex®-M0+. The debugger sets
the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system reset
request through the AIRCR can also be done by the embedded software (into the hardfault handler for
instance)
– Reset from the RSTN external pin
The RSTN pin toggles to inform that a reset has occurred
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•
•
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•
This PADRESETn resets all resources of the BlueNRG-LP, except:
Debug features
Flash controller key management
RTC timer
Power controller unit
Part of the RCC registers
The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case
of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.
1.9
Clock management
Three different clock sources may be used to drive the system clock of the BlueNRG-LP:
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HSI: high speed internal 64 MHz RC oscillator
PLL64M: 64 MHz PLL clock
HSE: high speed 32 MHz external crystal
The BlueNRG-LP has also a low speed clock tree used by some timers in the radio, RTC and IWDG.
Four different clock sources can be used for this low speed clock tree:
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Low speed internal (LSI): low speed and low drift internal RC with a fixed frequency between 24 kHz and 49
kHz depending on the sample
Low speed external (LSE) from:
– An external crystal 32.768 kHz
– A single-ended 32.738 kHz input signal
A 32 kHz clock (CLK_16 MHz/512 in Figure 6. Clock tree) obtained by dividing HSI or HSE. In this case, the
slow clock is not available in DEEPSTOP low power mode
LSI_LPMU: 32 kHz clock used by the low power management unit (LPMU) analog block.
By default, after a system reset, all low speed sources are OFF.
Both the activation and the selection of the slow clock are relevant during the DEEPSTOP mode and at wakeup
as slow clock generates a clock for the timers involved in wake-up event generation.
The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock
output by this block can be:
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•
DS13282 - Rev 5
A non-accurate clock when no external XO provides an input clock to this block (HSI)
An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)
page 13/73
BlueNRG-LP
Clock management
This fast clock source is used to generate all the fast clock of the device through dividers. After reset, the
CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories and peripherals).
This fast clock source is also used to generate several internal fast clocks in the system:
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Always 32 MHz requested by a few peripherals like the radio
Always 16 MHz requested by a few peripherals like serial interfaces (to maintain fixed the baud rate while
system clock is switching from one frequency to another) or like the Flash controller and radio (to have a fixed
reference clock to manage delays)
Figure 6. Clock tree
LSI RCO
32kHz
LSI_LPMU
RCO 32kHz
CLKSLOWSEL
LCOSEL
LCO
CK_RTC,
CK_WDG,
CK_BLEWKUP
CLK_16MHz/512
OSC32k_OUT
CLK_TIM1
LSE OSC
32kHz
SYSCLKDIV
OSC32k_IN
SYSCLK PRE
OSC_OUT
OSC_IN
CLK_SYS
/1, /2, .. , /32
HSE OSC
32MHz
1
1
0
0
SYSCLK PRE
/1, /2, .. , /64
to CPU,
AHB0,
APB0,
APB1,
SRAM,
PKA,
CLK_SPI1
HSESEL
HSI
RCO+PLL
64MHz
HSESEL
SYSCLKDIV
/4
1
/2
0
CLKANA_ADC
CLK_SMPS
CLK_SMPS
SMPSDIV
CLK_SYS
MCO
/1, /2, .. , /16
/2
1
/4
0
HSE
HSI
CLK_16MHz
1
HSESEL
CLK_16MHz/512
CLKANA_ADC,
CLK_USART,
CLK_I2C,
CLK_BLE16,
CLK_FLASH,
CLK_PWR,
CLK_RNG
CLK_LPUART
CLKSYS_BLE
0
MCOSEL
1
/2
BLECLKDIV
CLK_32MHz
CLK_BLE32,
CLKDIG_ADC
0
HSESEL
1
CLK_SPI2/I2S2
CLK_16MHz
0
SP2CKSEL
1
CLK_SPI3/I2S3
0
SP3CKSEL
It is possible to output some internal clocks on external pads:
•
•
the low speed clocks can be output on the LCO I/O
the high speed clocks can be output on the MCO I/O
This is possible by programming the associated I/O in the correct alternate function.
Most of the peripherals only use the system clock except:
DS13282 - Rev 5
page 14/73
BlueNRG-LP
Boot mode
•
•
•
•
•
•
•
1.10
I2C, USART, LPUART: they always use a16 MHz clock to have a fixed reference clock for baud rate
management. The goal is to allow the CPU to boost or slow down the system clock (depending on on-going
activities) without impacting a potential on-going serial interface transfer on external I/Os
SPI: when the I2S mode is used, the baud rate is always managed through the 16 MHz or 32 MHz clock.
When modes other than the I2S run, the baud rate is managed by the system clock. This implies its baud rate
is impacted by dynamic system clock frequency changes
RNG: in parallel to the system clock, the RNG always uses 16 MHz clock to generate at a constant frequency
the random number whatever the system clock frequency
Flash controller: in parallel to the system clock, the Flash controller always uses 16 MHz clock to generate
specific delays required by the Flash memory during programming and erase operations for example
PKA: in parallel to the system clock, the PKA uses a clock at half of the system clock frequency
Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a
potential divider (1 or 2 or 4). In parallel, the radio always uses 16 MHz and always 32 MHz for modulator,
demodulator and to have a fixed reference clock to manage specific delays
ADC: in parallel to the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz
Boot mode
Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This
modification is performed by programming the REMAP bit in the Flash controller.
The following memory can be remapped:
•
•
1.11
Main Flash memory
SRAM0 memory
Embedded UART bootloader
The BlueNRG-LP has a pre-programmed bootloader supporting UART protocol with automatic baud rate
detection. The main features of the embedded bootloader are:
•
•
•
•
Auto baud rate detection up to 1 Mbps
Flash mass erase, section erase
Flash programming
Flash readout protection enable/disable
The pre-programmed bootloader is an application, which is stored in the BlueNRG-LP internal ROM at
manufacturing time by STMicroelectronics. This application allows upgrading the device Flash with a user
application using a serial communication channel (UART).
Bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application residing in
Flash is launched.
Note:
Bootloader protocol is described in a separate application note (the BlueNRG-LP UART bootloader protocol,
AN5471)
1.12
General purpose inputs/outputs (GPIO)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without
pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
1.13
Direct memory access (DMA)
The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as
memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources
are free for other operations.
The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests.
DMA main features are:
•
DS13282 - Rev 5
Eight independently configurable channels (requests)
page 15/73
BlueNRG-LP
Nested vectored interrupt controller (NVIC)
•
•
•
•
•
•
•
•
•
1.14
Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also
supported on each channel. This configuration is done by software
Priorities among requests from channels of DMA are software programmable (four levels consisting of very
high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)
Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking.
Source/destination addresses must be aligned on the data size
Support for circular buffer management
Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together
in a single interrupt request for each channel
Memory-to-memory transfer (RAM only)
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
Access to SRAMs and APB1 peripherals as source and destination
Programmable number of data to be transferred: up to 65536
Nested vectored interrupt controller (NVIC)
The interrupts are handled by the Cortex®-M0+ nested vector interrupt controller (NVIC). NVIC controls specific
Cortex®-M0+ interrupts as well as the BlueNRG-LPS peripheral interrupts.
The NVIC benefits are the following:
•
•
•
•
•
•
•
•
Nested vectored interrupt controller that is an integral part of the ARM® Cortex®-M0+
Tightly coupled interrupt controller provides low interrupt latency
Control system exceptions and peripheral interrupts
NVIC supports 32 vectored interrupts
Four programmable interrupt priority levels with hardware priority level masking
Software interrupt generation using the ARM® exceptions SVCall and PendSV
Support for NMI
ARM® Cortex® M0+ vector table offset register VTOR implemented
NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.
1.15
Analog digital converter (ADC)
The BlueNRG-LPS embeds a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-todigital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources
and up to two internal sources.
The ADC main features are:
•
•
•
•
•
•
•
•
•
•
1.15.1
Conversion frequency is up to 1 Msps
Three input voltage ranges are supported (0 - 1.2 V, 0 - 2.4 V, 0 - 3.6 V)
Up to eight analog single-ended channels or four analog differential inputs or a mix of both
Temperature sensor conversion
Battery level conversion up to 3.6 V
ADC continuous or single mode conversion is possible
ADC down-sampler for multi-purpose applications to improve analog performance while off-loading the CPU
(ratio adjustable from 1 to 128)
A watchdog feature to inform when data is outside thresholds
DMA capability
Interrupt sources with flags.
Digital microphone MEMS interface
The digital microphone MEMS interface aims to interconnect with an external digital MEMS microphone. The
BlueNRG-LP can configure two GPIOs as PDM interface. The PDM_CLK provides the clock output signal,
programmable in frequency, to the microphone, while the PDM_DATA receives the PDM output data from the
microphone. The decimation filter and the digital control resources are used to handle the PDM data stream.
DS13282 - Rev 5
page 16/73
BlueNRG-LP
True random number generator (RNG)
1.15.2
Analog microphone interface
The analog microphone interface is dedicated to the analog microphone signal. The input audio signal is amplified
with a programmable gain amplifier (PGA) from 0 dB to 30 dB, then the data stream is sampled by ADC and
processed through the decimation filter.
1.15.3
Temperature sensor
The temperature sensor (TS) generates a voltage that varies linearly with temperature. The temperature sensor
is internally connected to the ADC input channel, which is used to convert the sensor output voltage into a digital
value.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by
ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in
read-only mode.
1.16
True random number generator (RNG)
RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the host
when read. The minimum period is 1.25 us, corresponding to 20 RNG clock cycles between two consecutive
random number.
1.17
Timers and watchdog
The BlueNRG-LP includes one advanced 16-bit timer, one watchdog timer and a SysTick timer.
1.17.1
Advanced control timer (TIM1)
The advanced-control timer can be considered as a three-phase PWM multiplexed on six channels. The six
channels have complementary PWM outputs with programmable inserted dead-times.
They can also be used as general-purpose timers for:
•
•
•
•
1.17.2
Input capture (except channels 5 and 6)
Output compare
PWM generation (edge and center-aligned mode)
One-pulse mode output
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from the LS clock
and it can operate in DEEPSTOP mode. It can also be used as a watchdog to reset the device when a problem
occurs.
1.17.3
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It
features:
•
•
•
1.18
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Real-time clock (RTC)
The RTC is an independent BCD timer/counter. The RTC provides a time of day/clock/calendar with
programmable alarm interrupt. RTC includes also a periodic programmable wake-up flag with interrupt capability.
The RTC provides an automatic wake-up to manage all low power modes.
Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day
of month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also
available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the
programmable alarm sub seconds, seconds, minutes, hours, day, and date.
DS13282 - Rev 5
page 17/73
BlueNRG-LP
Inter-integrated circuit interface (I2C)
A digital calibration circuit with 0.95 ppm resolution is available to compensate for quartz crystal inaccuracy. After
power-on reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply
voltage remains in the operating range, the RTC never stops, regardless of the device status (RUN mode, low
power mode or under system reset). The RTC counter does not freeze when CPU is halted by a debugger.
1.19
Inter-integrated circuit interface (I2C)
The BlueNRG-LP embeds two I2Cs. The I2C bus interface handles communications between the microcontroller
and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C bus specification and user manual rev. 5 compatibilities:
•
– Slave and master modes
– Multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (fm+), with a bitrate up to 1 Mbit/s and 20 mA output driver I/Os
– 7-bit and 10-bit addressing mode
– Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
– All 7-bit address acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
System management Bus (SMBus) specification rev 2.0 compatibility:
–
–
–
–
–
•
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent from the PCLK reprogramming
Programmable analog and digital noise filters
1-byte buffer with DMA capability
•
•
1.20
Hardware PEC (Packet Error Checking) generation and verification with ACK control
Address resolution protocol (ARP) support
Host and device support
SMBus alert
Timeouts and idle condition detection
Universal synchronous/asynchronous receiver transmitter (USART)
USART offers flexible full-duplex data exchange with external equipment requiring an industry standard NRZ
asynchronous serial data format. USART is able to communicate with a speed up to 2 Mbit/s. Furthermore,
USART is able to detect and automatically set its own baud rate, based on the reception of a single character.
The USART peripheral supports:
•
•
•
•
•
•
•
•
•
Synchronous one-way communication
Half-duplex single wire communication
Local interconnection network (LIN) master/slave capability
Smart card mode, ISO 7816 compliant protocol
IrDA (infrared data association) SIR ENDEC specifications
Modem operations (CTS/RTS)
RS485 driver enable
Multiprocessor communications
SPI-like communication capability
High speed data communication is possible by using DMA (direct memory access) for multibuffer configuration.
DS13282 - Rev 5
page 18/73
BlueNRG-LP
LPUART
1.21
LPUART
LPUART is a UART which allows bidirectional UART communications. It supports half-duplex single wire
communications and modem operations (CTS/RTS). It also supports multiprocessor communications. DMA (direct
memory access) can be used for data transmission/reception.
1.22
Serial peripheral interface (SPI)
The BlueNRG-LP has three SPI interfaces (SPI1, SPI2, SPI3) allowing communication up to 32 Mbit/s in both
master and slave modes. The SPI peripheral supports:
•
•
•
•
•
•
•
•
•
•
Master or slave operation
Multimaster support
Full-duplex synchronous transfers on three lines
Half-duplex synchronous transfer on two lines (with bidirectional data line)
Simplex synchronous transfers on two lines (with unidirectional data line)
Serial communication with external devices
NSS management by hardware or software for both master and slave: dynamic change of master/slave
operations
SPI Motorola support
SPI TI mode support
Hardware CRC feature for reliable communication
All SPI interfaces can be served by the DMA controller.
DS13282 - Rev 5
page 19/73
BlueNRG-LP
Inter-IC sound (I2S)
1.23
Inter-IC sound (I2S)
The BlueNRG-LP SPI interfaces: SPI2 and SPI3 support the I2S protocol. The I2S interface can operate in slave
or master mode with half-duplex communication. It can address four different audio standards:
•
•
•
•
Philips I2S standard
MSB-justified standards (left-justified)
LSB-justified standards (right-justified)
PCM standard.
The I2S interfaces DMA capability for transmission and reception.
1.24
Serial wire debug port
The BlueNRG-LP embeds an ARM SWD interface that allows interactive debugging and programming of the
device. The interface is composed of only two pins: SWDIO and SWCLK. The enhanced debugging features for
developers allow up to 4 breakpoints and up to 2 watchpoints.
1.25
TX and RX event alert
The BlueNRG-LP is provided with the TX_SEQUENCE and RX_SEQUENCE signals which alert, respectively,
transmission and reception activities.
A signal can be enabled for TX and RX on two pins, through alternate functions:
•
•
TX_SEQUENCE is available on PA10 (AF2) or PB15 (AF1).
RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2).
The signal is high when radio is in TX (or RX), low otherwise.
The signals can be used to control external antenna switching and support coexistence with other wireless
technologies.
DS13282 - Rev 5
page 20/73
BlueNRG-LP
Pinouts and pin description
2
Pinouts and pin description
The BlueNRG-LP comes in three package versions: QFN48 offering 32 GPIOs, WCSP49 offering 30 GPIOs and
QFN32 offering 20 GPIOs.
Figure 7. Pinout top view (QFN48 package)
DS13282 - Rev 5
PB4
PB5
PB6
PB7
PB8
PB9 PB10 PB11 VDDA VDD1 RSTN VDD3
48
47
46
45
44
43
42
41
40
39
38
37
PB3
1
36
VDDSD
PB2
2
35
VLXSD
PB1
3
34
VSS
PB0
4
33
NC
PA15
5
32
VFBSD
PA14
6
31
VCAP
PA13
7
30
PB12/XTAL0
PA12
8
29
PB13/XTAL1
PA11
9
28
PB14
PA10
10
27
PB15
PA9
11
26
VDD4
PA8
12
25
OSCIN
GND
15
16
17
18
19
20
PA2
PA3
PA4
PA5
PA6
PA7 VDD2
21
22
23
24
OSCOUT .
14
PA1
VDDRF .
13
PA0
RF1 .
pad
page 21/73
BlueNRG-LP
Pinouts and pin description
Figure 8. Pinout top view (QFN32 package)
VDD1 PB4
32
DS13282 - Rev 5
31
PB5
PB6
PB7 VCAP RSTN VDDSD
30
29
28
27
26
25
PB3
1
24
VLXSD
PB2
2
23
VSS
PB1
3
22
VFBSD
PB0
4
21
PB12/XTAL0
PA11
5
20
PB13/XTAL1
PA10
6
19
PB14
PA9
7
18
PB15
PA8
8
17
OSCIN
GND
11
12
13
PA0
PA1
PA2
PA3 VDD2
14
15
16
OSCOUT.
10
VDDRF
9
RF1
pad
page 22/73
BlueNRG-LP
Pinouts and pin description
Figure 9. Pinout top view (WLCSP49 package)
1
2
3
4
A
VDDSD
VLXSD
VSSIO
B
VSSSD
PB7
C
VFBSD
D
5
6
7
VDD3
RSTN
VDDA
VSSA
PB6
PB5
PB4
PB3
PB2
PB12
PB9
PB1
PB0
PA15
PA14
VCAP
PB13
PA11
PB8
PA13
PA12
PA9
E
OSCOUT
PB14
PA4
PA3
PA2
PA10
PA8
F
OSCIN
PB15
VSSRF
VSS
IFADC
PA5
PA0
VSSIO
G
VSSSX
VDDRF
VSSRFT
RX
RF1
PA7
PA1
VDD2
5
Table 3. Pin description
Pin number
DS13282 - Rev 5
QFN48
QFN32
WLCSP49
Pin name
(function
after reset)
1
1
B6
PB3
I/O
FT_a
USART_CTS,
LPUART_TX, TIM1_CH4
ADC_VINP0, wakeup
2
2
B7
PB2
I/O
FT_a
USART_RTS_DE,
PDM_DATA, TIM1_CH3
ADC_VINM0, wakeup
3
3
C4
PB1
I/O
FT_a
SPI1_NSS, PDM_CLK,
TIM1_ETR
ADC_VINP1, wakeup
4
4
C5
PB0
I/O
FT_a
USART_RX,
LPUART_RTS_DE,
TIM1_CH2N
ADC_VINM1, wakeup
5
-
C6
PA15
I/O
FT_a
I2C2_SMBA, SPI1_MOSI,
TIM1_BKIN2
ADC_VINP2, wakeup
6
-
C7
PA14
I/O
FT_a
I2C2_SDA, SPI1_MISO,
TIM1_BKIN
ADC_VINM2, wakeup
7
-
D5
PA13
I/O
FT_a
I2C2_SCL, SPI1_SCK,
SPI2_MISO, TIM1_ETR,
I2S2_MISO
ADC_VINP3, wakeup
8
-
D6
PA12
I/O
FT_a
I2C1_SMBA, SPI1_NSS,
SPI2_MOSI,TIM1_CH1,
I2S2_SD
ADC_VINM3, wakeup
Pin
type
I/O
structure
Alternate functions
Additional functions
page 23/73
BlueNRG-LP
Pinouts and pin description
Pin number
QFN48
WLCSP49
Pin
type
I/O
structure
Alternate functions
Additional functions
Wakeup, GPIO in
DEEPSTOP, RTC_OUT
9
5
D3
PA11
I/O
FT
MCO, SPI1_NSS,
RX_SEQUENCE,
SPI3_MOSI, TIM1_CH6,
I2S3_SD
10
6
E6
PA10
I/O
FT
LCO, SPI1_MISO,
TX_SEQUENCE,
SPI3_MCK, TIM1_CH5,
I2S3_MCK
BOOT, wakeup, GPIO
in DEEPSTOP, LCO
11
7
D7
PA9
I/O
FT
USART_TX, SPI1_SCK,
RTC_OUT, SPI3_NSS,
TIM1_CH4, I2S3_WS
Wakeup, GPIO in
DEEPSTOP, LCO
Wakeup, GPIO in
DEEPSTOP, RTC_OUT
12
8
E7
PA8
I/O
FT
USART_RX, SPI1_MOSI,
RX_SEQUENCE,
SPI3_MISO, TIM1_CH3,
I2S3_MISO
13
9
F6
PA0
I/O
FT_f
I2C1_SCL, USART_CTS,
SPI2_MCK, TIM1_CH3,
I2S2_MCK
Wakeup
14
10
G6
PA1
I/O
FT_f
I2C1_SDA, SPI2_MISO,
USART_TX, TIM1_CH4,
I2S2_MISO
Wakeup
15
11
E5
PA2
I/O
FT
SWDIO, USART_CK,
TIM_BKIN, SPI3_MCK,
TIM1_CH5, I2S3_MCK
Wakeup
16
12
E4
PA3
I/O
FT
SWCLK, USART_RTS_DE,
TIM_BKIN2, SPI3_SCK,
TIM1_CH6, I2S3_SCK
Wakeup
17
-
E3
PA4
I/O
FT
LCO, SPI2_NSS,
LPUART_TX, TIM1_CH1,
I2S2_WS
Wakeup, GPIO in
DEEPSTOP, LCO
18
-
F5
PA5
I/O
FT
MCO, SPI2_SCK,
LPUART_RX, TIM1_CH2,
I2S2_SCK
Wakeup, GPIO in
DEEPSTOP, LCO
FT
LPUART_CTS,
SPI2_MOSI, SPI2_NSS,
TIM1_CH1, I2S2_SD,
I2S2_WS
Wakeup, GPIO in
DEEPSTOP, LCO
Wakeup, GPIO in
DEEPSTOP, RTC_OUT
19
DS13282 - Rev 5
QFN32
Pin name
(function
after reset)
-
-
PA6
I/O
20
-
G5
PA7
I/O
FT
LPUART_RTS_DE,
SPI2_MISO, SPI2_SCK,
TIM1_CH2, I2S2_MISO,
I2S2_SCK
21
13
G7
VDD2
S
-
--
1.7-3.6 battery voltage
input
22
14
G4
RF1
I/O
RF
-
RF input/output.
Impedance 50 Ω
23
15
G2
VDDRF
S
-
-
1.7-3.6 battery voltage
input
24
16
E1
OSCOUT
I/O
RF
-
32 MHz crystal
25
17
F1
OSCIN
I/O
RF
-
32 MHz crystal
26
-
-
VDD4
S
-
-
1.7-3.6 battery voltage
input
page 24/73
BlueNRG-LP
Pinouts and pin description
Pin number
QFN48
QFN32
WLCSP49
Pin
type
I/O
structure
Alternate functions
Additional functions
-
27
18
F2
PB15
I/O
FT
I2C1_SMBA,
TX_SEQUENCE, MCO,
TIM1_CH4N, TIM1_CH6,
USART_TX
28
19
E2
PB14
I/O
FT_a
SPI1_MOSI, I2C2_SDA,
TIM1_ETR, TIM1_CH3N,
TIM1_CH5, USART_RX
VIN_PVD
29
20
D2
PB13
I/O
FT
SPI1_MISO, I2C2_SCL,
PDM_CLK, TIM1_BKIN2,
TIM1_CH4
SXTAL1
30
21
C2
PB12
I/O
FT
SPI1_SCK, LCO,
PDM_DATA, TIM1_BKIN,
TIM1_CH3
SXTAL0
31
27
D1
VCAP
S
-
-
1.2 Vdigital core
32
22
C1
VFBSD
S
-
-
SMPS output
NC
S
-
-
-
33
DS13282 - Rev 5
Pin name
(function
after reset)
34
23
B1
VSSSD
S
-
-
SMPS Ground
35
24
A2
VLXSD
S
-
-
SMPS input/output
36
25
A1
VDDSD
S
-
-
1.7-3.6 battery voltage
input
37
-
A4
VDD3
S
-
-
1.7-3.6 battery voltage
input
38
26
A5
RSTN
I/O
RST
-
Reset pin
39
32
-
VDD1
S
-
-
1.7-3.6 battery voltage
input
40
-
A6
VDDA
S
-
-
1.2 V analog ADC core
41
-
-
PB11
I/O
FT
SPI1_SCK, SPI2_NSS,
I2C1_SCL, TIM1_CH1,
TIM1_CH4N, I2S2_WS
Wakeup
42
-
-
PB10
I/O
FT
SPI1_NSS, SPI2_SCK,
I2C1_SDA, TIM1_CH2,
TIM1_CH3N, I2S2_SCK
Wakeup
Wakeup
43
-
C3
PB9
I/O
FT
USART_TX,
LPUART_CTS, SPI2_MCK,
TIM1_CH1N, TIM1_CH2N,
I2S2_MCK
44
-
D4
PB8
I/O
FT
USART_CK, LPUART_RX,
TIM1_CH4, TIM1_CH1N
Wakeup
45
28
B2
PB7
I/O
FT_f
I2C2_SDA, SPI2_SCK,
LPUART_RX, TIM1_CH2,
I2S2_SCK
Wakeup
46
29
B3
PB6
I/O
FT_f
I2C2_SCL, SPI2_NSS,
LPUART_TX, TIM1_CH1,
I2S2_WS
Wakeup
47
30
B4
PB5
I/O
TT
LPUART_RX, SPI2_MOSI,
PDM_CLK, I2S2_SD
PGA_VBIAS_MIC(1),
wakeup
48
31
B5
PB4
I/O
FT
LPUART_TX, SPI2_MISO,
PDM_DATA, I2S2_MISO
PGA_VIN, wakeup
-
-
A7
VSSA
S
-
-
Ground analog ADC
core
-
-
A3
VSSIO
S
-
-
Ground I/O
page 25/73
BlueNRG-LP
Pinouts and pin description
Pin number
QFN48
QFN32
WLCSP49
Pin name
(function
after reset)
-
-
F7
VSSIO
S
-
-
Ground I/O
-
-
F4
VSSIFADC
S
-
-
Ground analog RF
-
-
G1
VSSSX
S
-
-
Ground analog RF
-
-
G3
VSSRFTRX
S
-
-
Ground analog RF
-
-
F3
VSSRF
S
-
-
Ground analog RF
Exposed
pad
Exposed
pad
-
GND
S
-
-
Ground
Pin
type
I/O
structure
Alternate functions
Additional functions
1. This pin is not 5 V tolerant.
Table 4. Legend/abbreviations used in the pinout table
Name
Abbreviation
Pin name
Pin type
I/O structure
Definition
Unless otherwise specified in brackets below, the pin name and the pin function during
and after reset are the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TT
3.6 V tolerant I/O
RF
RF I/O
RST
Bidirectional reset pin with weak pull-up resistor
Options for TT or FT I/Os
Notes
Pin functions
_f(1).
I/O, Fm+ capable
_a(2).
I/O, with analog switch function supplied by IO
BOOSTER(3)
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
reset
Alternate functions Functions selected through GPIOx_AFR registers
Additional functions Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 3. Pin description are: FT_f
2. The related I/O structures in Table 3. Pin description are: FT_a
3. IO BOOSTER block allows the good behavior of those switches to be guaranteed when the VBAT goes below 2.7 V. Refer
to the BlueNRG-LP reference Manual (RM0479) for more details.
DS13282 - Rev 5
page 26/73
BlueNRG-LP
Pinouts and pin description
Table 5. Alternate function port A
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
I2C1/I2C2/SYS_AF
LPUART/ USART
SPI1/SPI2/
SYS_AF/USART/
I2S2
SPI1/SPI2/RTC
USART/
SPI2/ SPI3
LPUART/
I2S2/ I2S3
TIM1
SYS_AF
-
SYS_AF
PA0
I2C1_SCL
USART_CTS
SPI2_MCK/
I2S2_MCK
-
TIM1_CH3
-
-
-
PA1
I2C1_SDA
SPI2_MISO/
I2S2_MISO
USART_TX
-
TIM1_CH4
-
-
-
PA2
TMS_SWDIO
USART_CK
TIM_BKIN
SPI3_MCK/
I2S3_MCK
TIM1_CH5
TMS_SWDIO
-
TMS_SWDIO
PA3
TCK_SWCLK
USART_RTS_DE
TIM_BKIN2
SPI3_SCK/
I2S3_SCK
TIM1_CH6
TCK_SWCLK
-
TCK_SWCLK
PA4
LCO
SPI2_NSS/
I2S2_WS
-
LPUART_TX
TIM1_CH1
-
-
-
PA5
MCO
SPI2_SCK/
I2S2_SCK
-
LPUART_RX
TIM1_CH2
-
-
-
PA6
LPUART_CTS
SPI2_MOSI/
I2S2_SD
-
SPI2_NSS/
I2S2_WS
TIM1_CH1
-
-
-
PA7
LPUART_RTS_DE
SPI2_MISO/
I2S2_MISO
-
SPI2_SCK/
I2S2_SCK
TIM1_CH2
-
-
-
PA8
USART_RX
SPI1_MOSI
RX_SEQUENCE
SPI3_MISO/
I2S3_MISO
TIM1_CH3
-
-
-
PA9
USART_TX
SPI1_SCK
RTC_OUT
SPI3_NSS/
I2S3_WS
TIM1_CH4
-
-
-
PA10
LCO
SPI1_MISO
TX_SEQUENCE
SPI3_MCK/
I2S3_MCK
TIM1_CH5
-
-
-
PA11
MCO
SPI1_NSS
RX_SEQUENCE
SPI3_MOSI/
I2S3_SD
TIM1_CH6
-
-
-
PA12
I2C1_SMBA
TMS_SWDIO
SPI1_NSS
SPI2_MOSI/
I2S2_SD
TIM1_CH1
-
-
-
PA13
I2C2_SCL
TCK_SWCLK
SPI1_SCK
SPI2_MISO/
I2S2_MISO
TIM1_ETR
-
-
-
PA14
I2C2_SDA
-
SPI1_MISO
TIM1_BKIN
-
-
-
PA15
I2C2_SMBA
-
SPI1_MOSI
TIM1_BKIN2
-
-
-
Port
Port
A
DS13282 - Rev 5
TIM/ I2S2
-
page 27/73
BlueNRG-LP
Pinouts and pin description
Table 6. Alternate function port B
AF0
AF1
AF2
AF3
AF4
SPI1/I2C2 USART/
LPUART
PDM/SYS_AF/I2C2
LPUART/SPI2/I2S2
SPI2/I2C1/PDM
TIM1/SYS_AF/
I2S2
TIM1/PDM
LPUART
TIM1
-
-
USART
PB0
USART_RX
LPUART_RTS_DE
-
TIM1_CH2N
-
-
-
-
PB1
SPI1_NSS
PDM_CLK
-
TIM1_ETR
-
-
-
-
PB2
USART_RTS_DE
PDM_DATA
-
TIM1_CH3
-
-
-
-
PB3
USART_CTS
LPUART_TX
-
TIM1_CH4
-
-
-
-
PB4
LPUART_TX
SPI2_MISO/I2S2_MISO
-
PDM_DATA
-
-
-
-
PB5
LPUART_RX
SPI2_MOSI/I2S2_SD
-
PDM_CLK
-
-
-
-
PB6
I2C2_SCL
SPI2_NSS/I2S2_WS
-
LPUART_TX
TIM1_CH1
-
-
-
PB7
I2C2_SDA
SPI2_SCK/IS2S_SCK
-
LPUART_RX
TIM1_CH2
-
-
-
PB8
USART_CK
LPUART_RX
-
TIM1_CH4
TIM1_CH1N
-
-
-
PB9
USART_TX
LPUART_CTS
SPI2_MCK/
I2S2_MCK
TIM1_CH1N
TIM1_CH2N
-
-
-
PB10
SPI1_NSS
SPI2_SCK/I2S2_SCKK
I2C1_SDA
TIM1_CH2
TIM1_CH3N
-
-
-
PB11
SPI1_SCK
SPI2_NSS/I2S2_WS
I2C1_SCL
TIM1_CH1
TIM1_CH4N
-
-
-
PB12
SPI1_SCK
LCO
PDM_DATA
TIM1_BKIN
TIM1_CH3
-
-
-
PB13
SPI1_MISO
I2C2_SCL
PDM_CLK
TIM1_BKIN2
TIM1_CH4
-
-
-
PB14
SPI1_MOSI
I2C2_SDA
TIM1_ETR
TIM1_CH3N
TIM1_CH5
-
-
USART_RX
PB15
I2C1_SMBA
TX_SEQUENCE
MCO
TIM1_CH4N
TIM1_CH6
-
-
USART_TX
Port
Port B
DS13282 - Rev 5
AF5 AF6
AF7
page 28/73
BlueNRG-LP
Memory mapping
3
Memory mapping
Program memory, data memory and registers are organized within the same linear 4-Gbyte address space. The
detailed memory map and the peripheral mapping of the BlueNRG-LP can be found in the reference manual
(RM0479).
Figure 10. Memory map
0xFFFF FFFF
Reserved
0xE00F FFFF
0xE000 0000
0x8FFF FFFF
0x6002 0000
TM
Cortex M0+
Internal
Peripherals
0x6000 0000
Reserved
0x4800 0000
Reserved
0x4100 2000
0x4100 0000
0x4002 0000
0x8FFF FFFF
Reserved
APB2 (RF)
AHB0
Reserved
APB1
Reserved
APB0
0x4000 0000
0x2FFF FFFF
0x2000 FFFF
Peripherals
0x2000 C000
0x2000 8000
0x2000 4000
0x4000 0000
Reserved
SRAM3 (16 kB)
0x2000 0000
SRAM2 (16 kB)
SRAM1 (16 kB)
SRAM0 (16 kB)
Reserved
0x2FFF FFFF
Reserved
SRAM
0x1007 FFFF
Reserved
0x1004 0000
CODE
0x1000 0000
0x2000 0000
Main FLASH (256 kB)
0x1007 FFFF
Reserved
Reserved
0x0000 0000
0x0000 3FFF
0x0000 0000
DS13282 - Rev 5
CortexTM M0+
Flash or SRAM0,
depending on REMAP
configuration
page 29/73
BlueNRG-LP
Application circuits
4
Application circuits
The schematics below are purely indicative.
Figure 11. Application circuit: DC-DC converter, QFN48 package
1.7 V to 3.6 V Power Supply
C5
C2
C1
C4
C3
XTAL_LS
C6
C7
Q1
Q2
36
35
34
33
32
31
30
29
28 PB14
27 PB15
26
25
L1
VDDSD
VLXSD
VSS
NC
VFBSD
VCAP
PB12/XTAL0
PB13/XTAL1
PB14
PB15
VDD4
OSCIN
C8
C9
C10
RSTN
C13
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
37
38
39
40
41
42
43
44
45
46
47
48
BlueNRG-LP
24
OSCOUT
23
VDDRF
22
RF1
21
VDD2
20
PA7
19
PA6
18
PA5
17
PA4
16
PA3
15
PA2
14
PA1
13
PA0
C11
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
C14
L2
C15
L3
C12
C16
GND
U1
PB3
PB2
PB1
PB0
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
1
2
3
4
5
6
7
8
9
10
11
12
PB3
PB2
PB1
PB0
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
49
VDD3
RSTN
VDD1
VDDA
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
XTAL_HS
DS13282 - Rev 5
page 30/73
BlueNRG-LP
Application circuits
Figure 12. Application circuit: DC-DC converter, WCSP49 package
C13
C10
1.7 V to 3.6 V Power Supply
Q1
PB14
PB15
XTAL_LS
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB12
PB13
PB14
PB15
A5
A6
D1
RSTN
VDDA
VCAP
G7
A4
G2
A1
VDD2
VDD3
VDDRF
VDDSD
F6
G6
E5
E4
E3
F5
G5
E7
D7
E6
D3
D6
D5
C7
C6
C5
C4
B7
B6
B5
B4
B3
B2
D4
C3
C2
D2
E2
F2
RSTN
L1
A2
VLXSD C1
VFBSD
C6
C11
RF1
G4
BlueNRG-LP
L2
C15
L3
C12
C16
Q2
OSCIN
OSCOUT
F1
E1
XTAL_HS
F3
F7
A7
B1
F4
G3
A3
G1
C2
C8
VSSRF
VSSIO
VSSA
VSSSD
VSSIFADC
VSSRFTRX
VSSIO
VSSSX
C3
C9
C5
C1 U1
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
C14
Figure 13. Application circuit: DC-DC converter, QFN32 package
1.7 V to 3.6 V Power Supply
C1
C19
C20
XTAL_LS
C23
C7
Q1
Q2
24
23
22
21
20
19 PB14
18 PB15
17
L4
RSTN
C5
PB7
PB6
PB5
PB4
25
26
27
28
29
30
31
32
VLXSD
VSS
VFBSD
PB12/XTAL0
PB13/XTAL1
PB14
PB15
OSCIN
C8
VDDSD
RSTN
VCAP
PB7
PB6
PB5
PB4
VDD1
BlueNRG-LP
XTAL_HS
OSCOUT
VDDRF
RF1
VDD2
PA3
PA2
PA1
PA0
16
15
14
13
12
11
10
9
C11
PA3
PA2
PA1
PA0
L3
C12
C16
C14
GND
U1
PB3
PB2
PB1
PB0
PA11
PA10
PA9
PA8
1
2
3
4
5
6
7
8
33
PB3
PB2
PB1
PB0
PA11
PA10
PA9
PA8
C10
C15
L2
DS13282 - Rev 5
page 31/73
BlueNRG-LP
Application circuits
Table 7. Application circuit external components
Note:
DS13282 - Rev 5
Component
Description
C1
Decoupling capacitor
C2
32 kHz crystal loading capacitor
C3
32 kHz crystal loading capacitor
C4
Decoupling capacitor
C5
Decoupling capacitor for digital regulator
C6
DC – DC converter output capacitor
C7
Decoupling capacitor
C8
Decoupling capacitor
C9
DC-DC converter output inductor
C10
Decoupling capacitor
C11
Decoupling capacitor
C12
RF matching capacitor
C13
Decoupling capacitor
C14
Decoupling capacitor
C15
RF matching capacitor
C16
RF matching capacitor
L1
DC-DC converter output inductor
L2
RF matching inductor
L3
RF matching capacitor
Q1
Low speed crystal
Q2
High speed crystal
U1
BlueNRG-LP
U2
Low/band pass filter
In order to make the board DC–DC OFF, the inductance L1 must be removed and the supply voltage must be
applied to the VFBSD pin.
page 32/73
BlueNRG-LP
Electrical characteristics
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to ground (GND).
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the following standard
conditions:
•
Ambient temperature is TA = 25 °C
•
Supply voltage is VDD: 3.3 V
•
•
System clock frequency is 32 MHz (clock source HSI)
SMPS clock frequency is 4 MHz
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes and are not tested in production. Based on characterization, the minimum and maximum values
refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V. They are given only as design
guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean ± 2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are only given as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in the figure below.
Figure 14. Pin loading conditions
DS13282 - Rev 5
page 33/73
BlueNRG-LP
Parameter conditions
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in the figure below.
Figure 15. Pin input voltage
DS13282 - Rev 5
page 34/73
BlueNRG-LP
Absolute maximum ratings
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in the tables below, may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 8. Voltage characteristics
Symbol
Ratings
Min.
Max.
VDD1, VDD2, VDD3, VDD4, VDDRF, VDDSD
DC-DC converter supply voltage input and output
-0.3
+3.9
VCAP, VDDA
DC voltage on linear voltage regulator
-0.3
+1.32
FXTALOUT, FXTALIN
DC Voltage on HSE
-0.3
+1.32
PA0 to PA15, PB0 to PB4, PB6 to PB15
DC voltage on digital input/output pins
VLXSD, VFBSD
DC voltage on analog pins
-0.3
+3.9
XTAL0/PB12, XTAL1/PB13, PB5
DC voltage on XTAL pins and PGA_VBIAS_MIC
RF1
DC voltage on RF pin
V
+3.6
+1.4
Variations between different VDDX
|ΔVDD|
Note:
-0.3
Unit
50
power pins of the same domain
mV
All the main power and ground pins must always be connected to the external power supply, in the permitted
range.
Table 9. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD power lines (source)
130
ΣIVGND
Total current out of sum of all ground lines (sink)
130
IVDD(PIN)
Maximum current into each VDD power pin (source)
100
IVGND(PIN)
Maximum current out of each ground pin (sink)
100
Output current sunk by any I/O and control pin
20
Output current sourced by any I/O and control pin
20
Total output current sunk by sum of all I/Os and control pins
100
Total output current sourced by sum of all I/Os and control pins
100
IIO(PIN)
ΣIIO(PIN)
Unit
mA
Table 10. Thermal characteristics
DS13282 - Rev 5
Symbol
Ratings
Value
TSTG
Storage temperature range
-40 to -125
TJ
Maximum junction temperature
125
Unit
°C
page 35/73
BlueNRG-LP
Operating conditions
5.3
Operating conditions
5.3.1
Summary of main performance
Table 11. Main performance SMPS ON
Symbol
ICORE
IDYNAMIC
DS13282 - Rev 5
Parameter
Core current
consumption
Dynamic current
Typ.
Typ.
VDD = 1.8 V
VDD = 3.3 V
SHUTDOWN
8
19
DEEPSTOP, no timer, wake-up
GPIO, RAM0 retained
0.44
0.46
DEEPSTOP, no timer, wakeup
GPIO, all RAM retained
0.62
0.64
DEEPSTOP (32 kHz LSI), RAM0
retained
0.94
1.06
DEEPSTOP (32 kHz LSI), all
RAMs retained
1.12
1.24
DEEPSTOP (32 kHz LSE),
RAM0 retained
0.64
0.75
DEEPSTOP (32 kHz LSE), all
RAM retained
0.83
0.94
Test conditions
Unit
nA
µA
CPU in RUN (64 MHz).
Dhrystone, clock source PLL64
2719
CPU in RUN (32 MHz).
Dhrystone, clock source PLL64
2188
CPU in WFI (64 MHz), all
peripherals off, clock source
PLL64
1708
CPU in WFI (16 MHz), all
peripherals off, clock source
Direct HSE
1092
Radio RX at sensitivity level
3350
Radio TX 0 dBm output power
4300
Computed value: (CPU 64 MHz
Dhrystone - CPU 32 MHz
Dhrystone) / 32
18
uA
µA/MHz
page 36/73
BlueNRG-LP
Operating conditions
Table 12. Main performance SMPS bypassed
Symbol
ICORE
DS13282 - Rev 5
Parameter
Core current
consumption
Typ.
Typ.
VDD = 1.8 V
VDD = 3.3 V
SHUTDOWN
8
19
DEEPSTOP, no timer,
wake-up GPIO, RAM0
retained
0.44
0.46
DEEPSTOP, no timer,
wake-up GPIO, all
RAM retained
0.62
0.64
DEEPSTOP (32 kHz
LSI), RAM0 retained
0.94
1.06
DEEPSTOP (32 kHz
LSI), all RAMs
retained
1.12
1.24
DEEPSTOP (32 kHz
LSE ), RAM0 retained
0.64
0.75
DEEPSTOP (32 kHz
LSE), all RAM retained
0.83
0.94
Test conditions
CPU in RUN (64
MHz). Dhrystone,
clock source PLL64
4482
CPU in WFI (64 MHz),
all peripherals off,
clock source PLL64
2230
CPU in WFI (16
MHz), all peripherals
off, clock source direct
HSE
757
Radio RX at sensitivity
level
6700
Radio TX 0 dBm
output power
8900
Unit
nA
µA
page 37/73
BlueNRG-LP
Operating conditions
Table 13. Peripheral current consumption at VDD = 3.3 V, sysclk at 32 MHz, SMPS on
Parameter
DS13282 - Rev 5
Test conditions
Typ.
ADC
80
DMA
39
GPIOA
2
GPIOB
2
I2C1
40
I2C2
39
I2S2
Peripheral clock at 32 MHz
46
I2S3
Peripheral clock at 32 MHz
47
IWDG
11
LPUART
52
PVD
0.8
PKA
50
RNG
64
RTC
14
SPI1
35
SPI2
Peripheral clock at 16 MHz
40
SPI3
Peripheral clock at 16 MHz
42
Systick
8
TIM1
248
USART
81
SYSCFG
33
THSENS
301
CRC
9
Unit
µA
page 38/73
BlueNRG-LP
Operating conditions
5.3.2
General operating conditions
Table 14. General operating conditions
Symbol
Parameter
fHCLK
Conditions
Min.
Max.
Internal AHB clock frequency
1
64
fPCLK0
Internal APB0 clock
1
64
fPCLK1
Internal APB1 clock frequency
1
64
fPCLK2
Internal APB2 clock frequency
16
32
VDD
Standard operating voltage
1.7
3.6
VFBSMPS
SMPS feedback voltage
1.4
3.6
VDDRF
Minimum RF voltage
1.7
3.6
VIN
I/O input voltage
-0.3
VDD+0.3
PD
Power dissipation at TA=105 °C(1)
TA
Ambient temperature
TJ
Junction temperature range
QFN48 package
MHz
V
30
mW
-40
105
°C
-40
105
QFN32 package
Maximum power dissipation
Unit
1. TA cannot exceed the TJ max.
DS13282 - Rev 5
page 39/73
BlueNRG-LP
Operating conditions
5.3.3
RF general characteristics
All performance data are referred to a 50 Ω antenna connector, via reference design.
Table 15. Bluetooth Low Energy RF general characteristics
Symbol
Parameter
FRANGE
Frequency range(1)
RFCH
RF channel center
Test conditions
frequency(1)
Min. Typ.
Max.
2400
2483.5
2402
2480
Unit
MHz
PLLRES
RF channel spacing(1)
2
MHz
ΔF
Frequency deviation(1)
250
kHz
Δf1
Frequency deviation average(1)
CFdev
Center frequency deviation(1)
Δfa
Frequency deviation Δf2 (average) / Δf1
(average)(1)
0.80
Rgfsk
On-air data rate(1)
1
STacc
Symbol time
During the packet and including
both initial frequency offset and drift
accuracy(1)
MOD
Modulation scheme
BT
Bandwidth-bit period product
Mindex
450
Modulation
550
kHz
±150
kHz
2
Mbps
±50
ppm
GFSK
0.5
index(1)
0.45
0.5
0.55
PMAX
Maximum output
At antenna connector, VSMPS =
1.9 V, LDO code
+8
dBm
PMIN
Minimum output
At antenna connector
-20
dBm
PRFC
RF power accuracy
@ 27 °C
±1.5
All temperatures
±2.5
dB
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
DS13282 - Rev 5
page 40/73
BlueNRG-LP
Operating conditions
5.3.4
RF transmitter characteristics
All performance data are referred to a 50 Ω antenna connector, via reference design.
Table 16. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps not coded
Symbol
Parameter
Test conditions
PBW1M
6 dB bandwidth for modulated
carrier
Using resolution bandwidth of 100 kHz
PRF1, 1 Ms/s
In-band emission at ±2 MHz(1)
Using resolution bandwidth of 100 kHz and
average detector
-20
dBm
PRF2, 1 Ms/s
In-band emission at ±[3+n]MHz,
where n=0,1,2..(1)
Using resolution bandwidth of 100 kHz and
average detector
-30
dBm
PSPUR
Spurious emission
Harmonics included. Using resolution
bandwidth of 1 MHz and average detector
-41
dBm
Freqdrift
Frequency drift(1)
Integration interval #n – integration interval
#0, where n=2,3,4..k
-50
+50
kHz
IFreqdrift
Initial carrier frequency drift(1)
Integration interval #1 – integration interval
#0
-23
+23
kHz
IntFreqdrift
Intermediate carrier frequency
drift(1)
Integration interval #n – integration interval
#(n-5), where n=6,7,8..k
-20
+20
kHz
Drift Rate max
Maximum drift rate(1)
Between any two 10-bit groups separated by
50 µs
-20
+20
kHz/50
µs
ZRF1
Optimum RF load
(impedance at RF1 pin)
Min. Typ. Max.
Unit
500
kHz
@ 2440 MHz
40
Ω
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
Table 17. Bluetooth Low Energy RF transmitter characteristics at 2 Mbps not coded
Symbol
Parameter
Test conditions
PBW1M
6 dB bandwidth for modulated
carrier
Using resolution bandwidth of 100 kHz
PRF1, 2 Ms/s
In-band emission at ±4 MHz(1)
Using resolution bandwidth of 100 kHz and
average detector
-20
dBm
PRF2, 2 Ms/s
In-band emission at±5 MHz(1)
Using resolution bandwidth of 100 kHz and
average detector
-20
dBm
PRF3, 2 Ms/s
In-band emission at ±[6+n]MHz,
where n=0,1,2..(1)
Using resolution bandwidth of 100 kHz and
average detector
-30
dBm
PSPUR
Spurious emission
Harmonics included. Using resolution
bandwidth of 1 MHz and average detector
-41
dBm
Freqdrift
Frequency drift(1)
Integration interval #n – integration interval
#0, where n=2,3,4..k
-50
+50
kHz
IFreqdrift
Initial carrier frequency drift(1)
Integration interval #1 – integration interval #0
-23
+23
kHz
IntFreqdrift
Intermediate carrier frequency
drift(1)
Integration interval #n – integration interval
#(n-5), where n=6,7,8..k
-20
+20
kHz
DriftRatemax
Maximum drift rate(1)
Between any two 20-bit groups separated by
50 µs
-20
+20
kHz/50µs
ZRF1
Optimum RF load
(impedance at RF1 pin)
@ 2440 MHz
Min. Typ. Max.
Unit
670
kHz
40
Ω
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
DS13282 - Rev 5
page 41/73
BlueNRG-LP
Operating conditions
Table 18. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps LE coded (S=8)
Symbol
Parameter
Test conditions
PBW
6 dB bandwidth for modulated
carrier
Using resolution bandwidth of 100 kHz
PRF1, LE coded
In-band emission at ±2 MHz(1)
Using resolution bandwidth of 100 kHz and
average detector
-20
dBm
PRF2, LE coded
In-band emission at ±[3+n]
MHz, where n=0,1,2..(1)
Using resolution bandwidth of 100 kHz and
average detector
-30
dBm
PSPUR
Spurious emission
Harmonics included. Using resolution
bandwidth of 1 MHz and average detector
-41
dBm
Freqdrift
Frequency drift(1)
Integration interval #n – integration interval
#0, where n=1,2,3..k
-50
+50
kHz
IFreqdrift
Initial carrier frequency drift(1)
Integration interval #3 – integration interval
#0
-19.2
+19.2
kHz
IntFreqdrift
Intermediate carrier frequency
drift(1)
Integration interval #n – integration interval
#(n-3), where n=7,8,9..k
-19.2
+19.2
kHz
DriftRatemax
Maximum drift rate(1)
Between any two 16-bit groups separated
by 48 µs
-19.2
+19.2
kHz/48
µs
ZRF1
Optimum RF load
(Impedance at RF1 pin)
@ 2440 MHz
Min. Typ. Max.
Unit
500
kHz
40
Ω
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
DS13282 - Rev 5
page 42/73
BlueNRG-LP
Operating conditions
5.3.5
RF receiver characteristics
All performance data are referred to a 50 Ω antenna connector, via reference design.
Table 19. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s uncoded
Symbol
Parameter
Test conditions
RXSENS
Sensitivity
PER < 30.8%
PSAT
Saturation
ZRF1
Optimum RF source
(impedance at RF1 pin)
Min. Typ. Max. Unit
-
-97
dBm
PER < 30.8%
8
dBm
@ 2440 MHz
40
Ω
Wanted signal = -67 dBm, PER < 30.8%
8
dBc
Wanted signal = -67 dBm, PER < 30.8%
-1
dBc
Wanted signal = -67 dBm, PER < 30.8%
-35
dBc
Wanted signal = -67 dBm, PER < 30.8%
-47
dBc
Wanted signal = -67 dBm, PER < 30.8%
-25
dBc
Wanted signal= -67 dBm, PER < 30.8%
-25
dBc
RF selectivity with BLE equal modulation on interfering signal
C/ICO-channel
C/I1 MHz
C/I2 MHz
Co-channel interference
fRX = finterference
Adjacent interference
finterference = fRX ± 1 MHz
Adjacent Interference
finterference = fRX ± 2 MHz
Adjacent interference
C/I3 MHz
finterference = fRX ± (3+n) MHz
[n = 0,1,2…]
C/IImage
C/IImage±1 MHz
Image frequency interference
finterference = fimage
Adjacent channel-to-image frequency
finterference = fimage ± 1 MHz
Out of band blocking (interfering signal CW)
C/IBlock
Interfering signal frequency 30 MHz –
2000 MHz
Wanted signal = -67 dBm, PER < 30.8%,
measurement resolution 10 MHz
5
dB
C/IBlock
Interfering signal frequency 2003 MHz –
2399 MHz
Wanted signal = -67 dBm, PER < 30.8%,
measurement resolution 3 MHz
-5
dB
C/IBlock
Interfering signal frequency 2484 MHz –
2997 MHz
Wanted signal = -67 dBm, PER < 30.8%,
measurement resolution 3 MHz
-5
dB
C/IBlock
Interfering signal frequency 3000 MHz –
12.75 GHz
Wanted signal = -67 dBm, PER < 30.8%,
measurement resolution 25 MHz
10
dB
Intermodulation characteristics (CW signal at f1, BLE interfering signal at f2)
P_IM(3)
Input power of IM interferer at 3 and 6
MHz distance from wanted signal
Wanted signal = -64 dBm, PER < 30.8%
-27
dBm
P_IM(-3)
Input power of IM interferer at -3 and -6
MHz distance from wanted signal
Wanted signal = -64 dBm, PER < 30.8%
-40
dBm
P_IM(4)
Input power of IM interferer at ±4 and ±8
MHz distance from wanted signal
Wanted signal= -64 dBm, PER < 30.8%
-32
dBm
P_IM(5)
Input power of IM interferer at ±5 and ±10
MHz distance from wanted signal
Wanted signal = -64 dBm, PER < 30.8%
-32
dBm
Table 20. Bluetooth Low Energy RF receiver characteristics at 2 Msym/s uncoded
DS13282 - Rev 5
Symbol
Parameter
Test conditions
RXSENS
Sensitivity
PER < 30.8%
Min. Typ. Max. Unit
-94
dBm
page 43/73
BlueNRG-LP
Operating conditions
Symbol
Parameter
Test conditions
PSAT
Saturation
PER < 30.8%
8
dBm
@ 2440 MHz
40
Ω
Wanted signal= -67 dBm, PER < 30.8%
8
dBc
Wanted signal = -67 dBm, PER <
30.8%
-14
dBc
Wanted signal = -67 dBm, PER <
30.8%
-41
dBc
Wanted signal = -67 dBm, PER <
30.8%
-45
dBc
Wanted signal = -67 dBm, PER <
30.8%
-25
dBc
Wanted signal= -67 dBm, PER < 30.8%
-14
dBc
ZRF1
Optimum RF source
(impedance at RF1 pin)
Min. Typ. Max. Unit
RF selectivity with BLE equal modulation on interfering signal
C/ICO-channel
C/I2 MHz
C/I4 MHz
Co-channel interference
fRX = finterference
Adjacent interference
finterference = fRX ± 2 MHz
Adjacent interference
finterference = fRX ± 4 MHz
Adjacent interference
C/I6 MHz
finterference = fRX ± (6+2n) MHz
[n = 0,1,2…]
C/IImage
C/IImage±1 MHz
Image frequency interference
finterference = fimage-2M
Adjacent channel-to-image frequency
finterference = fimage-2M ± 2 MHz
Out of band blocking (interfering signal CW)
C/IBlock
Interfering signal frequency 30 MHz –
2000 MHz
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 10
MHz
5
dB
C/IBlock
Interfering signal frequency 2003 MHz –
2399 MHz
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 3 MHz
-5
dB
C/IBlock
Interfering signal frequency 2484 MHz –
2997 MHz
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 3 MHz
-5
dB
C/IBlock
Interfering signal frequency 3000 MHz –
12.75 GHz
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 25
MHz
10
dB
Intermodulation characteristics (CW signal at f1, BLE interfering signal at f2)
DS13282 - Rev 5
P_IM(6)
Input power of IM interferer at 6 and 12
MHz distance from wanted signal
Wanted signal= -64 dBm, PER < 30.8%
-27
dBm
P_IM(-6)
Input power of IM interferer at -6 and -12
MHz distance from wanted signal
Wanted signal= -64 dBm, PER < 30.8%
-30
dBm
P_IM(8)
Input power of IM interferer at ±8 and ±16
MHz distance from wanted signal
Wanted signal= -64 dBm, PER < 30.8%
-30
dBm
P_IM(10)
Input power of IM interferer at ±10 and
±20 MHz distance from wanted signal
Wanted signal= -64 dBm, PER < 30.8%
-28
dBm
page 44/73
BlueNRG-LP
Operating conditions
Table 21. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2)
Symbol
Parameter
Test conditions
RXSENS
Sensitivity
PER < 30.8%
PSAT
Saturation
PER < 30.8%
ZRF1
Optimum RF source
(impedance at RF1 pin)
Min. Typ. Max. Unit
-100
dBm
8
dBm
40
Ω
Wanted signal = -79 dBm, PER < 30.8%
2
dBc
Wanted signal = -79 dBm, PER < 30.8%
-5
dBc
Wanted signal = -79 dBm, PER < 30.8%
-38
dBc
Wanted signal = -79 dBm, PER < 30.8%
-50
dBc
Wanted signal = -79 dBm, PER < 30.8%
-30
dBc
Wanted signal = -79 dBm, PER < 30.8%
-34
dBc
-
@ 2440 MHz
RF selectivity with BLE equal modulation on interfering signal
C/ICO-channel
C/I1 MHz
C/I2 MHz
Co-channel interference
fRX = finterference
Adjacent interference
finterference = fRX ± 1 MHz
Adjacent interference
finterference = fRX ± 2 MHz
Adjacent interference
C/I3 MHz
finterference = fRX ± (3+n) MHz
[n = 0,1,2…]
C/IImage
C/IImage±1 MHz
Image frequency interference
finterference = fimage
Adjacent channel-to-image frequency
finterference = fimage ± 1 MHz
Table 22. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8)
Symbol
Parameter
Test conditions
RXSENS
Sensitivity
PER < 30.8%
PSAT
Saturation
PER < 30.8%
ZRF1
Optimum RF source
(impedance at RF1 pin)
Min. Typ. Max. Unit
-104
dBm
8
dBm
40
Ω
Wanted signal = -79 dBm, PER < 30.8%
1
dBc
Wanted signal = -79 dBm, PER < 30.8%
-4
dBc
Wanted signal = -79 dBm, PER < 30.8%
-39
dBc
Wanted signal = -79 dBm, PER < 30.8%
-53
dBc
Wanted signal = -79 dBm, PER < 30.8%
-33
dBc
Wanted signal = -79 dBm, PER < 30.8%
-32
dBc
@ 2440 MHz
-
RF selectivity with BLE equal modulation on interfering signal
C/ICO-channel
C/I1 MHz
C/I2 MHz
Co-channel interference
fRX = finterference
Adjacent interference
finterference = fRX ± 1 MHz
Adjacent interference
finterference = fRX ± 2 MHz
Adjacent interference
C/I3 MHz
finterference = fRX ± (3+n) MHz
[n = 0,1,2…]
C/IImage
C/IImage ± 1 MHz
DS13282 - Rev 5
Image frequency interference
finterference = fimage
Adjacent channel-to-image frequency
finterference = fimage ± 1 MHz
page 45/73
BlueNRG-LP
Operating conditions
5.3.6
Embedded reset and power control block characteristics
Table 23. Embedded reset and power control block characteristics
5.3.7
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
TRSTTEMPO
Reset temporization after PDR
is detected
VDD rising
VPDR
Power-down reset threshold
VPVD0
PVD0 threshold
PVD0 threshold at the falling edge of VDDIO
2.05
VPVD1
PVD1 threshold
PVD1 threshold at the falling edge of VDDIO
2.21
VPVD2
PVD2 threshold
PVD2 threshold at the falling edge of VDDIO
2.36
VPVD3
PVD3 threshold
PVD3 threshold at the falling edge of VDDIO
2.53
VPVD4
PVD4 threshold
PVD4 threshold at the falling edge of VDDIO
2.64
VPVD5
PVD5 threshold
PVD5 threshold at the falling edge of VDDIO
2.82
VPVD6
PVD6 threshold
PVD6 threshold at the falling edge of VDDIO
2.91
VPVD7
PVD threshold for VIN_PVD
PVD7 threshold (VBGP) at the falling edge of
VIN_PVD
1.2
500
us
1.63
V
Supply current characteristics
The current consumption is a function of several parameters and factors such as: the operating voltage, ambient
temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program
location in memory and executed binary code.
The MCU is put under the following conditions:
•
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number
When the peripherals are enabled fPCLK = fHCLK
Table 24. Current consumption
Symbol
Parameter
Conditions
25 °C
85 °C
105 °C
2.40
2.49
2.54
1.98
2.03
2.08
1.62
1.67
1.71
Timer OFF
0.65
6.73
15.73
Timer source LSI
1.25
7.41
16.46
1.30
7.56
16.70
fHCLK = 64 MHz
All peripherals disabled
IDD(RUN)
Supply current in RUN mode
fHCLK = 32 MHz
All peripherals disabled
fHCLK = 16 MHz
All peripherals disabled
Timer source LSI
IDD(DEEPSTOP)
Supply current in
DEEPSTOP(1)
RTC ON
Timer source LSI
IWDG ON
Timer source LSI
RTC and IWDG ON
DS13282 - Rev 5
Typ.
Unit
mA
µA
1.27
7.47
16.55
1.33
7.61
16.79
page 46/73
BlueNRG-LP
Operating conditions
Symbol
Parameter
Typ.
Conditions
Timer source LSE
Timer source LSE
RTC ON
IDD(DEEPSTOP)
Supply current in DEEPSTOP(1)
Timer source LSE
IWDG ON
Timer source LSE
RTC and IWDG ON
25 °C
85 °C
105 °C
1.00
7.16
16.22
1.06
7.31
16.45
1.02
7.22
16.30
1.07
7.36
16.54
IDD(SHUTDOWN)
Supply current in SHUTDOWN
0.02
0.46
1.36
IDD(RST)
Current under reset condition
1.34
1.45
1.55
Unit
µA
mA
1. The current consumption in DEEPSTOP is measured considering the entire SRAM retained.
5.3.8
Wake-up time from low power modes
The wake-up times reported are the latency between the event and the execution of the instruction. The device
goes to low-power mode after WFI (wait for interrupt) instructions.
Table 25. Low power mode wake-up timing
5.3.9
Symbol
Parameter
Conditions
TWUDEEPSTOP
Wake-up time from DEEPSTOP mode to RUN
mode
Typ. Unit
Wake-up from GPIO VDD = 3.3 V Flash memory 110
µs
High speed crystal requirements
The high speed external oscillator must be supplied with an external 32 MHz crystal that is specified for a 6 to
8 pF loading capacitor. The BlueNRG-LP includes internal programmable capacitances that can be used to tune
the crystal frequency in order to compensate the PCB parasitic one. These internal load capacitors are made by
a fixed one, in parallel with a 6-bit binary weighted capacitor bank. Thanks to low CL step size (LSB is typically
0.07 pF), very fine crystal tuning is possible. With a typical XTAL sensitivity of -14 ppm/pF, it is possible to trim a
32 MHz crystal, with a resolution of 1 ppm.
The requirements for the external 32 MHz crystal are reported in the table below.
Table 26. HSE crystal requirements
Symbol
Parameter
fNOM
Oscillator frequency
fTOL
Frequency tolerance
ESR
Conditions
Min. Typ. Max. Unit
32
Includes initial accuracy, stability over temperature,
aging and frequency pulling due to incorrect load
capacitance
MHz
±50
ppm
Equivalent series resistance
100
Ω
PD
Drive level
100
µW
CL
HSE crystal load capacitance
9.2(3)
pF
CLstep
HSE crystal load capacitance LSB
value
27 °C, typical corner
GMCONF = 3
5 (1)
7(2)
27 °C,
GMCONF = 3
0.07
pF
XOTUNE code between 32 and 33
1. XOTUNE programed at minimum code = 0
2. XOTUNE programed at center code = 32
3. XOTUNE programed at maximum code = 63
DS13282 - Rev 5
page 47/73
BlueNRG-LP
Operating conditions
5.3.10
Low speed crystal requirements
Low speed clock can be supplied with an external 32.768 kHz crystal oscillator. Requirements for the external
32.768 kHz crystal are reported in the table below.
Table 27. LSE crystal requirements
5.3.11
Symbol
Parameter
Conditions
Min.
Typ.
Max.
fNOM
Nominal frequency
ESR
Equivalent series resistance
90
kΩ
PD
Drive level
0.1
µW
32.768
Unit
kHz
High speed ring oscillator characteristics
Table 28. HSI oscillator characteristics
5.3.12
Symbol
Parameter
fNOM
Nominal frequency
Conditions
Min.
Typ.
Max.
64
Unit
MHz
Low speed ring oscillator characteristics
Table 29. LSI oscillator characteristics
5.3.13
Symbol
Parameter
Conditions
fNOM
Nominal frequency
ΔFRO_ΔT/FRO
Frequency spread vs. temperature
Min.
Standard deviation
Typ.
Max.
Unit
33
kHz
140
ppm/ºC
PLL characteristics
Characteristics measured over recommended operating conditions unless otherwise specified.
Table 30. PLL characteristics
Symbol
Parameter
Conditions
At ±1 MHz offset from carrier
Unit
-114
dBc/Hz
-128
dBc/Hz
At ±25 MHz offset from carrier
-135
dBc/Hz
(measured at 2.4 GHz)
At 2.4 GHz±6 MHz offset from carrier
(measured at 2.4 GHz)
DS13282 - Rev 5
Max.
dBc/Hz
At 2.4 GHz ±3 MHz offset from carrier
RF carrier phase noise
Typ.
-110
(measured at 2.4 GHz)
PNSYNTH
Min.
LOCKTIMETX
PLL lock time to TX
With calibration @2.5 ppm
150
µs
LOCKTIMERX
PLL lock time to RX
With calibration @2.5 ppm
110
µs
LOCKTIMERXTX
PLL lock time RX to TX
Without calibration @2.5 ppm
47
µs
LOCKTIMETXRX
PLL lock time TX to RX
Without calibration @2.5 ppm
32
µs
page 48/73
BlueNRG-LP
Operating conditions
5.3.14
Flash memory characteristics
The characteristics below are guaranteed by design.
Table 31. Flash memory characteristics
Symbol
Parameter
tprog
Typ.
Max.
32-bit programming time
20
40
tprog_burst
4x32-bit burst programming time
4x20
4x40
tERASE
Page (2 kbyte) erase time
20
40
tME
Mass erase time
20
40
IDD
Test conditions
Average consumption from VDD
Write mode
3
Erase mode
3
Mass erase
5
Unit
µs
ms
mA
Table 32. Flash memory endurance and data retention
5.3.15
Symbol
Parameter
Test conditions
Min.
Unit
NEND
Endurance
TA = -40 to +105 ºC
10
kcycles
tRET
Data retention
TA = 105 ºC
10
Years
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each
sample according to each pin combination. The sample size depends on the number of supply pins in the device
(3 parts x (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard.
Table 33. ESD absolute maximum ratings
Class Max.(1) Unit
Symbol
Parameter
Conditions
VESD(HBM)
Electrostatic discharge voltage (human body
model)
Conforming to ANSI/ESDA/JEDEC JS-001
2
2000
VESD(CBM)
Electrostatic discharge voltage (charge
device model)
Conforming to ANSI/ESDA/STM5.3.1
JS-002
C2a
500
V
1. Guaranteed by design.
5.3.16
I/O port characteristics
Unless otherwise specified, the parameters given in the tables below are derived from tests performed under the
conditions summarized in Section 5.3.2 General operating conditions. All I/Os are designed as CMOS-compliant.
The characteristics below are guaranteed by characterization.
Table 34. I/O static characteristics
Symbol
Parameter
VIL
I/O input low level voltage
VIH
I/O input high level voltage
Conditions
Min.
Typ.
0.7 x VDD
0
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