HDMI2C4-5F2

HDMI2C4-5F2 Datasheet ESD protection and signal booster for HDMI™ source control stage interface Features • • • • • WLCSP (12 bumps) package • • • • For HDMI™ 1.4, 2.0 & 2.1 application, operating temperature from -40 to 85 °C 8 kV contact ESD protection on connector side (IEC 61000-4-2 level 4) DDC (I2C) buffers with level shifter and backdrive protection High integration level in 1 package DDC (I2C) link protection, bi-directional signal conditioning circuit and dynamic pull-up HPD pull down, signal conditioning with level shifter and backdrive protection Enable function available for power consumption control and optimization (=ENABLE_IC) 325 mA Short-circuit protection on 5V output with backdrive protection Proposed in 500 µm pitch WLCSP package 12 bumps Benefits • Minimal PCB footprint in tablet, set top box, game console and other consumer application • Protection of ultra-sensitive HDMI™ ASICs • Ultra low power consumption in stand-by mode thanks to Enable function • Improved HDMI™ interface ruggedness and user experience • Long and/or poor quality cable support with dynamic pull-up on DDC bus Product status link HDMI2C4-5F2 Complies with the following standards • Dedicated for HDMI™ 1.4, 2.0 and 2.1 version • IEC 61000-4-2 level 4 • JESD22-A114D level 2 HDMI logo and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC. Applications Consumer and computer electronics HDMI™ Source device such as: • Tablet and smartphone • HD set-top boxes • Game console • DVD and Blu-Ray Disk systems • Notebook • PC graphic cards Description The HDMI2C4-5F2 is an integrated ESD protection and signal conditioning device for control links of HDMI™ transmitters (Source). This device is a simple solution that provides HDMI™ designers with an easy and fast way to reach full compliance with the stringent HDMI™ CTS on a wide temperature range. DS12652 - Rev 1 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com HDMI2C4-5F2 Functional description 1 Functional description The HDMI2C4-5F2 is a fully integrated ESD protection and signal conditioning device for control stage of HDMI™ transmitters (Source). The component offers two buffers, integrating signal conditioning dynamic pull-up on DDC bus for maximum system robustness and signal integrity. These buffers embed also a protection to prevent from connector backdrive current when the ENABLE_IC input is low. This component is compliant with clock stretching mode. The +5 V supplied to the cable is protect against accidental surge current and short circuit. Enable function is available to allow power consumption control and to prevent from connector backdrive current. All these features are provided in a single 12 bumps WLCSP package featuring natural PCB routing, cost optimization and saving space on the board. The HDMI2C4-5F2 is a simple solution that provides HDMI™ designers with an easy and fast way to reach full compliance with the stringent HDMI™ CTS on a wide temperature range. STMicroelectronics proposes also a large range of high speed ESD protections and common mode filter (ECMF™ series) dedicated to the TMDS lanes giving the flexibility to the designer to filter and protect these (high speed video link against ESD strikes and EMC issues). Figure 1. Pin configuration (bump side) GND SDA HPD CEC 5V_OUT SCL ENABLE_IC VDD_5V SDA_IC HPD_IC SCL_IC VDD_IC DS12652 - Rev 1 page 2/24 HDMI2C4-5F2 Application information 2 Application information 2.1 DDC bus description The DDC bus is described in the HDMI™ standards as the display data channel. The topology corresponds to an I2C bus that must be compliant with the I2C bus specification UM10204 revision 5 (October 2012). The DDC bus is made of 2 lines; data line (SDA) and clock line (SCL). It is used to create a point to point communication link from the source to the sink. EEDID and HDCP protocols are especially flowing through this link, making this I2C communication channel a key element in the HDMI™ application. The DDC block integrated in the HDMI2C4-5F2 allows a bidirectional communication between the cable and the ASIC. It is fully compliant with the HDMI™ 2.0 standard (I2C bus specification) and its CTS. It is shifting the 5 V voltage from the cable (V5V_OUT) down to the ASIC voltage level (VDD_IC) that can be as low as 1.8 V. During clock stretching operation, when the sink pulls-down the bus, thanks to the comparator and level shifter, the ASIC input is pulled-down to avoid any glitch. The Figure 2. shows the functional diagram of the DDC block integrated in the HDMI2C4-5F2 device. Figure 2. DDC buffer functional diagram (SCL and SDA lines) +5V decoupling capacitance VDD_5V VDD_IC ENABLE_IC 5V_OUT UVLO HBM HBM SCL : dV/dt limiter Drive 6 18 16 14 12 10 19 17 15 13 11 RPU_BUS 9 8 7 - up SCL SDA reshaping circuit IEC61000-4-2 SCL_IC SDA_IC dynamic pull 5V_OUT Enable 5 5V_OUT AND HDMI ASIC 4 3 RPU_AS IC 2 1 VDD_IC HDMI connecto r The Figure 3. illustrates the electrical parameter of the DDC block specified by the Table 8.. DS12652 - Rev 1 page 3/24 HDMI2C4-5F2 DDC bus description ASIC side Figure 3. Simplified view of the electrical parameters of the SDA level shifter SDA_IC V DD_IC V tup_IC V Tdown_ IC t SDA VDD_5V Cable side 5V_OUT 70% V tup_BU S V Tdown_ BUS V HYST_B US 30% t T FALL_B US T RISE_B US Source IC drives Sink drives through HDMI cable Capacitance measured at the HDMI connector output is equal to the sum of HDMI2C4-5F2 capacitance plus bus capacitance between HDMI2C4-5F2 and HDMI connector output. Thanks to the internal structure of the integrated DDC block, measured capacitance is equal to the input capacitance and then independent from the IC actual capacitance. For compliance test, capacitance on DDC bus must be measured with HDMI2C4-5F2 powered on. The HDMI™ standard specifies that the max capacitance of the cable can reach up to 700 pF. Knowing that the max capacitance of the sink input can reach up to 50 pF, this means that the I2C buffer must be able to drive a load capacitance up to 750 pF. On the other hand, the I2C standard specifies a maximum rise time (30%-70%) of the signal must be lower than 1 µs in order to keep the signal integrity. Taking into account the max cable capacitance of 750 pF, it is not possible to guarantee a rise time lower than 1µs in worst case. Therefore, a dynamic pull-up has been integrated at the output of SDA and SCL lines and synchronized with the I2C driver. This signal booster accelerates for a short period the charging time of the equivalent cable capacitance, allowing driving any HDMI™ cable. The Figure 4. illustrates the benefit of the dynamic pull-up integrated in the HDMI2C4-5F2 device. DS12652 - Rev 1 page 4/24 HDMI2C4-5F2 DDC bus description Figure 4. Benefit of the dynamic pull-up on the DDC bus I2C driver without dynamic pull-up I2C driver with dynamic pull-up 5V_ OUT 5V_ OUT dynamic pull - up RPU_BUS 750pF RPU_BUS 750pF HDMI™ cable model IC control HDMI™ cable model IC control VDD_IC Signal on the cable Signal on the cable 5V_OUT Rise time out of I2C specification Risk of communication failure Rise time compliant with I2C specification Signal integrity even on 750pF load capacitance Before activating the DDC buffers, three following conditions must be respected: • VDD_5V must be higher than the VDD_ON threshold (Table 4.) • • • DS12652 - Rev 1 ENABLE_IC input must be set to a high level All inputs and outputs (SDA, SCL, SDA_IC, SCL_IC) must be set to a high level at the same time as well as HPD input The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is compliant with ‑IEC61000-4-2 standard, level 4 (8 kV contact). page 5/24 HDMI2C4-5F2 HDP line description 2.2 HDP line description The HDMI2C4-5F2 proposes a unique solution to manage and to protect HPD link. The Figure 5. shows an overview of the function diagram of the integrated block. Figure 5. HPD line functional diagram VDD_IC HDMI connecto r decoupling capacitance 4 18 16 14 12 10 8 7 19 17 15 13 11 9 IEC61000-4-2 HBM ENABLE_I C VDD_IC 6 5 HPD_IC or IC 3 HPD HDMI ASIC 2 1 VDD_IC Simply connect the PIN3 of the HDMI™ connector to one side of the device, and then use the HPD_IC and VDD_IC outputs on the other side of the device to manage HPD link. HPD input (cable side) integrates a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8 kV contact). When the ENABLE_IC input is set at a low level, the HPD is not pulled down and the HPD_IC output is forced at a low level. The integrated HPD block is pulling down the line via a current source. When the input voltage is detected to be higher than a threshold level, the signal is converted into a high state level on the ASIC side, at the voltage level of the ASIC power supply‑VDD_IC. The electrical parameters relevant to the HPD block and specified by the Table 7. are shown by the Figure 6.. DS12652 - Rev 1 page 6/24 HDMI2C4-5F2 +5 V protection Figure 6. Simplified view of the electrical parameters of the HPD block Signal on HPD link 5V VTH_HPD HPD_IC signal VDD_IC 2.3 +5 V protection The +5 V power supply that the source device has to provide to the HDMI™ cable is described by the HDMI™ standard. It must be protected against accidental short circuit that could occur on the cable side. The HDMI2C4-5F2 device embeds a low drop current limiter. If an overcurrent is detected, the HDMI2C4-5F2 limits the current through the +5 V power supply. If the current is too high (short circuit), the device opens the +5V. Furthermore, the HDMI2C4-5F2 device embeds also an over temperature protection (OTP). If the internal temperature of the device is reaching a too high value, the +5 V supply is opened in order to protect the application. An under voltage lockout (UVLO) is also integrated in the block. It checks the main +5 V power supply state, and enable the +5V_OUT only if the main power supply has reach a minimal value VDD_5V_ON. When the ENABLE_IC input is set at a low level, the 5 V supply is opened to prevent from connector backdrive current. The Figure 7. shows the functional diagram of the current limiter block. Figure 7. 5 V link functional diagram HDMI connecto r 2 4 3 6 5 18 16 14 12 10 8 7 19 17 15 13 11 9 decoupling capacitance IEC61000-4-2 OTP UVLO Ctrl DS12652 - Rev 1 +5V_OUT Low drop current limiter Current sensor HBM decoupling capacitance VDD_5V 1 5V page 7/24 HDMI2C4-5F2 +5 V protection To summarize, the short circuit protection and the over temperature protection features are providing a high robustness level of the application. The 5V_OUT pin integrates also a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8 kV contact). The decoupling capacitance is mandatory accordingly to the power management state of the art. The OUT_5V pin is pulled down when EN = 0 or VDD_5V < UVLO threshold level. DS12652 - Rev 1 page 8/24 HDMI2C4-5F2 Backdrive protection 2.4 Backdrive protection Thanks to the innovative switch architecture, when the ENABLE_IC input is set at a low level, backdrive current is blocked whatever backdrive current is coming from +5V_OUT and/or DDC lines (see Figure 8.). Back-drive function is activated as soon as UVLO function is turned ON. Figure 8. Backdrive current diagram 5V_OUT 5V_IN 5V_Sink Cable SDA / SCL SDA / SCL Back -drive current path 2.5 Enable function Enable function is available to allow user control to switch on or switch off the device even if VDD_5V and VDD_IC are supplied. When the device is disabled, 5V_OUT output is pulled-down by an internal 1.4 kΩ resistor. DS12652 - Rev 1 page 9/24 HDMI2C4-5F2 Application block diagrams 2.6 Application block diagrams The Figure 9. shows an application block diagram proposal, with all possible options implemented. Thanks to ENABLE_IC signal control, the designer has then the tools to optimize the power consumption of the global application with a stand-by mode. Figure 9. Application block diagram VDD_IC VDD_IC +5V HDMI2C4-5F2 +5V pow er C1 C2 R3 R4 VDD_IC C3 HPD_IC HPD HPD HPD / HEAC- SDA SDA SCL SCL CEC CEC bus VDD_IC R1 R2 DDC data SDA_IC DDC clo ck SCL_IC HDMI connector HDMI ASIC 5V_OUT VDD_5V ENABLE_IC GND ENABLE_IC Table 1. External component recommendations Note: DS12652 - Rev 1 Ref. Typical value R1 and R2 10 kΩ Pull-up resistance on DDC bus, ASIC side, value selected to be compliant with I2C levels. C1 and C2 100 nF Decoupling capacitance on power supplies. R3 and R4 1.8 kΩ Pull-up resistances on DDC bus, specified by the HDMI™ standard. C3 1 µF, 10 V minimum, ‑10 % tolerance Comment ESD (low ESR) decoupling capacitance. SCL_IC, SDA_IC have to be driven with an ASIC working with open drain outputs. page 10/24 HDMI2C4-5F2 Application block diagrams Figure 10. Pin numbering (bump side) C B A GND HPD 500 SDA 1 SCL 2 SDA_IC 3 SCL_IC 4 500 5V_OUT CEC 650 VDD_5V ENABLE_IC HPD_IC VDD_IC Table 2. Pin numbering and description DS12652 - Rev 1 Pin Name A1 Description Pin Name Description SDA DDC output HDMI cable side A3 SDA_IC B1 GND Ground B3 ENABLE_IC C1 HPD HPD - input HDMI cable side C3 VDD_5V +5 V main power supply A2 SCL DDC output HDMI cable side A4 SCL_IC DDC input ASIC side B2 CEC CEC output HDMI cable side B4 VDD_IC HDMI ASIC power supply C2 5V_OUT +5 V power supply HDMI cable side C4 HPD_IC HPD output ASIC side DDC input ASIC side Enable all functions page 11/24 HDMI2C4-5F2 Electrical characteristics 3 Electrical characteristics Table 3. Absolute maximum ratings (limiting values) Symbol Parameter Contact discharge VPP_BUS ESD discharge on HDMI cable side (pins A1, C1, A2, B2 and C2) ±8(1) IEC 61000-4-2 level 4 Air discharge ±15 ESD discharge (all pins) Contact discharge ±2 HBM ‑JESD22-A114D, level 2 Air discharge ±2 VPP_IC Test conditions Value Unit kV kV TSTG Storage temperature range -55 to +150 °C TOP Operating temperature range -40 to +85 °C 260 °C 6 V -0.3 to 6 V TL Maximum lead temperature VDD_5V, VDD_IC Supply voltages Inputs Logical input min / max voltage range 1. With a 1 µF low ESR capacitor connected to the 5V_OUT pin Table 4. Power supply characteristics (Tamb = 25 °C) Symbol Parameter VDD_IC VDD_5V VDD_5V_ON (1) IQS_5V Test conditions Value Min. Low-voltage ASIC/HPD supply voltage 1.62 5 V input supply voltage range 4.9 +5 V power on reset 3.5 Quiescent currents on VDD_5V, VDD_IC Typ. V 5.0 5.3 V 3.8 4.1 V 700 µA 60 µA 150 °C VDD_IC = 5 V, VDD_IC = 1.8 V, idle-state on DDC links, HPD and 5V_OUT links open, ‑ENABLE_IC = 1.8 V Thermal Shutdown threshold Unit 5.3 IQS_IC TSD Max. 120 1. In order to activate the DDC lines, the VDD_5V has to reach the VDD_ON threshold. The inputs and outputs of the bidirectional level shifters must be set to a high level after the power-on, and the HPD line has to be activated one time. Table 5. HDMI 5V_OUT current limiter electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, unless otherwise specified) Pin number Description RPull_down(1) VDROP DS12652 - Rev 1 Test conditions Value Min. Typ. Max. Unit Output pull down resistor on 5V_OUT when the circuit is disabled VDD_5V = 5 V, VDD_IC = 1.8 V Idle-state on DDC links, HPD and 5V_OUT links open, ENABLE_IC = 0 V 1.1 1.4 1.7 kΩ Drop-out voltage I5V_OUT = 250 mA 42 79 125 mV page 12/24 HDMI2C4-5F2 Electrical characteristics Pin number Description IDC_MAX (1) I5V_OCP(1) Test conditions Max DC current on 5V_OUT pin without OCP or OTP activation Over current protection on 5V_OUT pin Value Min. Typ. Max. 250 V5V_OUT = 0 V 250 Unit mA 325 400 mA 1. for Tamb from -40 °C to +85 °C Table 6. Enable electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, unless otherwise specified) Symbol ILEAK IQS_5V_OFF IQS_IC_OFF VTH_EN / VDD_IC Value Parameter Test conditions Backdrive current for 5V_OUT, SDA, SCL, HPD ENABLE_IC=0 VDD_5V = 0 V, VDD_IC = 0 V, Tested pin = 5 V 1 µA Quiescent currents on VDD_5V, VDD_IC VDD_5V = 5 V, VDD_IC = 1.8 V, SCL, SCL_IC, SDA, SDA_IC, HPD = VDD_IC and ENABLE_IC = 0 V 95 µA 1 µA Min. Enable input VDD_IC = 1.8 V threshold level Typ. Max. Unit 30 50 70 % tON Turn on time VDD_5V = 5 V, CL = 1 µF and RL = 100 Ω, see Figure 11 and Figure 12 10 50 100 µs tOFF Turn off time VDD_5V = 5 V, CL = 1 µF and RL = 100 Ω, see Figure 11. and Figure 12. 50 250 500 µs Figure 11. Output rise and fall test load +5V_OUT RL DS12652 - Rev 1 CL page 13/24 HDMI2C4-5F2 Electrical characteristics Figure 12. Enable time 50% VENABLE 50% 50% 50% VENABLE t ON t OFF 90% 10% 5V_OUT t ON t OFF 90% 10% 5V_OUT t t Table 7. HPD line electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, unless otherwise specified) Symbol Parameter IPULL_DOWN Pull-down current in HPD block VTH_HPD HPD input low-level CIN_HPD Input capacitance Test conditions Value Min. Max. 15 25 µA 1.7 V 25 pF 15 %VDD_IC 1.0 VDD_5V = 0 V, VBIAS = 0 V, f = 1 MHz, VOSC = 30 mV VOL_HPD_IC HPD_IC output low- Current sunk by HPD_IC level pin is 500 µA VOH_HPD_IC HPD_IC output high-level Current sourced by HPD_IC pin is 500 µA Unit Typ. 21 %VDD_IC 80 Table 8. SDA line electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified) Symbol Parameter Test conditions VTup_BUS Upward input voltage threshold on bus side VDD_5V = 5 V Downward input VTdown_BUS voltage threshold on bus side Min. 1.5 Input hysteresis on bus side VDD_5V = 5 V 1.0 VOL_BUS Output low level TRISE_BUS Output rise-time (30%-70%) TFALL_BUS Output fall-time (70%-30%) VTup_IC Upward input voltage threshold on IC side Typ. Max. 3.5 VDD_5V = 5 V VHYST_BUS DS12652 - Rev 1 Value Unit V V 1.3 V Current sunk by SDA pin is 3 mA 0.35 V CBUS = 750 pF(1), RUP = 2 kΩ // 47 kΩ + 10 % (2) 500 ns 200 ns 65 %VDD_IC 55 60 page 14/24 HDMI2C4-5F2 Electrical characteristics Symbol Parameter Test conditions VTdown_IC Downward input voltage threshold on IC side VOL_IC Output low-level on IC side Current sunk by SDA_IC pin is 3 mA Input capacitance on DDC link VDD_5V = 0 V, VDD_IC = 0 V, VBIAS = 0 V, f = 1 MHz, VOSC = 30 mV CIN_DDC Value Unit Min. Typ. Max. 35 40 45 %VDD_IC 20 %VDD_IC 30(3) pF 25 1. Maximum load capacitance allowed on I2C entire link (cable plus connector) is 750 pF in HDMI™ 1.4 specification. 2. Two pull-up resistors in parallel (sink+source). Typical value is 47kΩ and maximum value is 47kΩ +10% in HDMI 1.4 specification. 3. Maximum capacitance allowed at connector output is 50 pF in HDMI™ 1.4 specification. Figure 13. SDA typical waveforms (IC to cable communication) Note: DS12652 - Rev 1 Measurements performed with 750 pF load, CSYSTEM = 15 pF and VDD_IC = 1.8 V page 15/24 HDMI2C4-5F2 Electrical characteristics Figure 14. SDA typical waveforms (Cable to IC communication) Note: Measurements performed with 750 pF load, CSYSTEM = 15 pF and VDD_IC = 1.8 V Table 9. SCL line electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified) Symbol Parameter Test conditions VTH_BUS Input voltage threshold on bus side VDD_5V = 5 V VOL_BUS Output low level TRISE_BUS Output rise-time (30%-70%) TFALL_BUS Output fall-time (70%-30%) VTH_IC Input voltage threshold on IC side VOL_IC Output low-level on IC side CIN_DDC Value Unit Min. Typ. Max. 1.5 2.0 2.5 V Current sunk by SCL pin is 3 mA 0.35 V CBUS = 750 pF(1) RUP = 2 kΩ // 47 kΩ + 10% (2) 500 ns 200 ns 30 %VDD_IC 20 %VDD_IC 30(3) pF 24 Current sunk by SCL_IC pin is 3 mA VDD_5V = 0 V, VDD_IC = 0 Input capacitance on V, VBIAS = 0 V,f = 1 MHz, DDC link VOSC=30 mV 25 1. Maximum load capacitance allowed on I2C entire link (cable plus connector) is 750 pF in HDMI™ 1.4 specification. 2. Two pull-up resistors in parallel (sink+source). Typical value is 47 kΩ and maximum value is ‑47 kΩ +10% in HDMI 1.4 specification. 3. Maximum capacitance allowed at connector output is 50 pF in HDMI™ 1.4 specification. DS12652 - Rev 1 page 16/24 HDMI2C4-5F2 Electrical characteristics Figure 15. SCL typical waveforms (IC to cable communication in normal mode - without clock stretching operation) When the source IC releases the clock line and SCL_IC rises up to VTH_IC level, the HDMI2C4-5F2 forces SCL_IC signal at low level and releases SCL on cable side. When the cable side reaches VTH_BUS level, the HDMI2C4-5F2 activates the dynamic pull-up on cable side and releases SCL_IC. A small parasitic spike occurs on SCL_IC with voltage below 0.3*VDD_IC. Figure 16. SCL typical waveforms (IC to cable communication in clock stretching operation) Note: DS12652 - Rev 1 Measurements performed with 750 pF load, CSYSTEM = 15 pF and VDD_IC = 1.8 V page 17/24 HDMI2C4-5F2 Electrical characteristics Figure 17. HPD typical waveform (Timing) DS12652 - Rev 1 page 18/24 HDMI2C4-5F2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 WLCSP 12 bumps package information Figure 18. WLCSP 12 bumps package outline GND SDA HPD 500 ± 10 CEC WLCSP number of bumps : 12 500 ± 10 650 ± 10 ENABLE_IC VDD_5V SDA_IC HPD_IC SCL_IC 2130 ± 50 µm SCL 5 V OUT Size : 1490 ± 50 x 2130 ± 50 µm 3.17 ± 0.18 mm² Thickness : 605 ± 55 µm Pitch : 500 ± 10 µm Bump diameter : 255 ± 10 µm VDD_IC 1490 ± 50 µm DS12652 - Rev 1 page 19/24 HDMI2C4-5F2 WLCSP 12 bumps packing information 4.2 WLCSP 12 bumps packing information Figure 19. Marking Note: More packing information is available in the application note: • AN2348 Flip-Chip: “Package description and recommendations for use” Figure 20. Footprint DS12652 - Rev 1 page 20/24 HDMI2C4-5F2 WLCSP 12 bumps packing information Figure 21. WLCSP 12 bumps tape and reel specification (all dimensions in mm) DS12652 - Rev 1 page 21/24 HDMI2C4-5F2 Ordering information 5 Ordering information Figure 22. Ordering information scheme HDMI2C 4 - 5 F2 HDMI and I2C compliant link HDMI port type Source ports // with 325mA current limiter (400mA max) Clock stretching mode Number of protected links 5 lines protected according to IEC 61000-4-2 Package typpe F = Flip Chip 2 : Lead-free, pitch = 500 µm, bump = 255 µm Table 10. Ordering information Note: DS12652 - Rev 1 Order code Marking Package Weight Base qty. Delivery mode HDMI2C4-5F2 PX WLCSP 4 mg 5000 Tape and reel More information is available in AN2348 application note : • STMicroelectronics 400 micro-meter Flip Chip: package description and recommendation for use page 22/24 HDMI2C4-5F2 Revision history Table 11. Document revision history DS12652 - Rev 1 Date Revision 10-Aug-2018 1 Changes Initial release. page 23/24 HDMI2C4-5F2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12652 - Rev 1 page 24/24