L4938ED013TR

L4938ED L4938EPD Advanced voltage regulator Features ■ Enable and sense inputs (EN, SI) protected against negative transients down to -5 V ■ Reset threshold adjustable from 3.8 V to 4.7 V ■ Extremely low quiescent current, 65 µA (less than 90 µA) in standby mode ■ Operating DC supply voltage range 5 V - 28 V ■ Operating transient supply voltage up to 40 V ■ High precision standby output voltage 5 V ± 1% with 100 mA current capability ■ Output 2 voltage 5 V ± 2% with 400 mA current capability (ADJ wired to VOUT2) ■ Output 2 voltage adjustable by external voltage divider ■ Output 2 disable function for standby mode PowerSO-20 SO-20 Description The L4938ED and L4938EPD are monolithic integrated dual voltage regulators with two very low dropout outputs and additional functions such as power-on reset and input voltage sense. They are designed for supplying microcomputer controlled systems especially in automotive applications. Table 1. Device summary Order codes Package September 2013 Tube Tape and reel SO-20 L4938ED L4938ED013TR PowerSO-20 L4938EPD L4938EPD13TR Doc ID 17243 Rev 2 1/20 www.st.com 1 Contents L4938ED, L4938EPD Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 2/20 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Standby regulator 3.3 Output 2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Sense comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Thermal protection 3.7 Transient sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8 Input protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 PowerSO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 17243 Rev 2 L4938ED, L4938EPD List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OUT1, OUT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Sense comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 17243 Rev 2 3/20 List of figures L4938ED, L4938EPD List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. 4/20 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input characteristics of SI, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PowerSO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 17243 Rev 2 L4938ED, L4938EPD 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram Figure 2. Configuration diagram (top view) PR 1 20 SI CT 2 19 VS1 EN 3 18 VS2 GND 4 17 GND GND 5 16 GND GND 6 15 GND GND 7 14 GND RES 8 13 N.C. SO 9 12 OUT2 OUT1 10 11 ADJ GND 1 20 GND N.C. 2 19 N.C. VS2 3 18 OUT2 VS1 4 17 ADJ SI 5 16 OUT1 PR 6 15 SO CT 7 14 RESET EN 8 13 N.C. N.C. 9 12 N.C. GND 10 11 GND PowerSO-20 SO-20 Doc ID 17243 Rev 2 5/20 Block diagram and pin description Table 2. L4938ED, L4938EPD Pin definitions and functions PIn number Name 6/20 Function SO-20 PowerSO-20 18 3 VS2 Supply voltage (400 mA regulator) 19 4 VS1 Supply voltage (100 mA regulator, reset, sense) 20 5 SI Sense input 1 6 PR Reset threshold programming 2 7 CT Reset delay capacitor 3 8 EN Enable (low activates the 400 mA regulator) 4, 5, 6, 7, 14, 15, 16, 17 1, 10, 11, 20 GND Ground 8 14 RES Reset output 9 15 SO Sense output 10 16 OUT1 11 17 ADJ 12 18 OUT2 13 2, 9, 19 NC 100 mA regulator output Feedback of 400 mA regulator 400 mA regulator output Not connected Doc ID 17243 Rev 2 L4938ED, L4938EPD Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute maximum ratings Symbol Parameter VINDC DC operating supply voltage VINTR Transient operating supply voltage (T < 400 ms) IO VSI ISI Output current Sense input voltage (voltage forced) Sense input current (current forced)(1) forced)(1) Enable input voltage (voltage IEN Sense input current (current forced)(1) IRES, ISO Unit 28 V -14 to 40 V internally limited (1) VEN VRES, VSO Value Output voltages Output currents (output low) °C(2) -20 to 20 V ±1 mA -20 to 20 V ±1 mA -0.3 to 20 V 5 mA 875 mW PO Power dissipation at Tamb = 80 Tstg Storage temperature -65 to 150 °C TJ Operating junction temperature -40 to 150 °C 165 °C TJSD Thermal shutdown junction temperature output 2 will shutdown typically at TJ 10 K lower than output 1 1. Current forced means voltage unlimited but current limited to the specified value voltage forced means voltage limited to the specified values while the current is not limited 2. Typical value soldered on a PC board with 8 cm2 copper ground plane (35 mm thick). Note: The circuit is ESD protected according to MIL-STD-883C. Doc ID 17243 Rev 2 7/20 Electrical specifications 2.2 L4938ED, L4938EPD Thermal data Table 4. Thermal data Symbol Parameter Rthj-amb Thermal resistance junction to ambient Rthj-case Thermal resistance junction to case SO-20 PowerSO-20 Unit 50 - °C/W - 1.3 V 65 90 µA TJ < 85 °C; RPR = 0 75 VDP1 Drop output voltage 1 VOL01 Load regulation 1 IOUT1 = 1 to 100 mA (after regulation setting) VLIM1 Current limit 1 VOUT1 = 0.8 to 4.5 V IQSB Quiescent current in standby mode Table 6. Symbol 100 Max. Unit µA OUT2 Parameter Test condition Enable = low; VS = 6 to 28 V; IO2 = 5 to 400 mA VO2 Output voltage 2 ADJ connected to OUT2 VDP2 Drop output voltage 2 VOL02 Load regulation 2 RADJ Adjust input resistance ILIM2 Current limit 2 V02 = 0.8 to 4.5 V Quiescent current IOUT1 = 100 mA; IOUT2 = 400 mA IQ 8/20 Parameter Min. Typ. 4.9 Max. Unit 5.1 V IOUT2 = 100 mA 0.2 0.3 V IOUT2 = 400 mA; VS = 4.8 V 0.3 0.6 V 50 mV IOUT1 = 5 to 400 mA (after regulation setting) Doc ID 17243 Rev 2 60 100 150 mA 450 650 1300 mA 20 mA L4938ED, L4938EPD Table 7. Symbol VOLi 1,2 Table 8. Symbol Electrical specifications OUT1, OUT2 Parameter Test condition Min. Typ. VS = 6 to 28 V; IO1 = 1 mA, IO2 = 5 mA, (after regulation setting) Line regulation Max. Unit 20 mV Max. Unit Enable input Parameter Test condition Min. Typ. VENL Enable input low voltage (output 2 active) -20 1 V VENH Enable input high voltage 1.4 20 V VENhyst Enable hysteresis 20 30 60 mV IEN LOW Enable input current low VEN = 0 -20 -8 -3 µA VEN = 1.1 to 7 V; TJ < 130 °C; -1 0 1 µA VEN = 1.1 to 7 V; TJ = 130 to 150 °C; -10 0 10 µA Min. Typ. Max. Unit RPR = ∞ 4.5 VO10.3 VO10.2 V RPR = 0 3.65 3.8 3.95 V 30 60 120 mV 40 60 100 ms IEN HIGH Table 9. Symbol VRT VRTH Enable input current high Reset circuit Parameter Test condition Reset threshold voltage(1) Reset threshold hysteresis RPR = ∞ µs(2) tRD min Reset pulse delay CRES = 47 nF; t r ≤ 30 tRD nom Reset pulse delay CRES = 47 nF(3) 60 100 140 ms tRR Reset reaction time CRES = 47 nF 10 50 150 µs ICT Pull down capability of the discharge circuit VOUT1 < VRT 3 6 15 mA ICT Charge current VOUT1 > VRT -1.3 -1 0.7 µA VRESL Reset output low voltage RRES = 10 KΩ to VOUT1 VOUT1 ≥ 1.5 V 0.4 V VRESH Reset output high leakage current VRES = 5 V 1 µA 1. The reset threshold can be programmed continuously from typ 3.8 V to 4.7 V by changing a value of an external resistor from pin PR to GND. 2. This is a minimum reset time according to the hysteresis of the comparator. Delay time starts with VOUT1 exceeding VRT. 3. This is the nominal reset time depending on the discharging limit of CT (saturation voltage) and the upper threshold of the timer comparator. Delay time starts with VOUT1 exceeding VRT. Doc ID 17243 Rev 2 9/20 Electrical specifications Table 10. Symbol VSI 10/20 L4938ED, L4938EPD Sense comparator Parameter Test condition Functional range Min. Typ. -20 1.24 V Falling edge; TJ < 130 to 150 °C 1.05 1.16 1.29 V 10 30 60 mV 0.4 V 1 µA Sense threshold hysteresis VSOL Sense output low voltage VSI ≤ 1.05 V; RSO = 10 KΩ connected to 5 V; VS ≥ 5 V ISOH Sense output leakage VSO = 5 V; VSI ≥ 1.5 V Sense input current low V 1.16 VSITH ISI LOW 20 1.08 Sense threshold voltage Sense input current high Unit Falling edge; TJ < 130 °C VSIT ISI HIGH Max. VSI = 1.1 to 7 V; TJ < 130 °C -1 0 1 µA VSI = 1.1 to 7 V; TJ < 130 to 150 °C -10 0 10 µA VSI = 0 V -20 -8 -3 µA Doc ID 17243 Rev 2 L4938ED, L4938EPD Application information 3 Application information Figure 3. Application diagram (See note 2) (See note 1) 1. The leakage of CT must be less than 0.5 mA (2 V). If an external resistor between CT and V OUT1 is applied, the leakage current may be increased. The external resistor should have more than 30 KΩ. For stability: Cs ≥ 1 µF, C01 ≥ 10 µF, C02 ≥ 10 µF, ESR ≤ 5Ω (designed target). 2. For transients exceeding 20 V or -20 V external protection is required at the pins SI and EN as shown at pin EN. The protection proposed provides proper function for transients in the range of ±200 V. If the zener diode is omitted the external resistor should be raised to 200 KΩ to limit the current to 1 mA. Without the zener diode, the function 20 V or -20 V can not be guaranteed. 3.1 Functional description The L4938ED and L4938EPD are monolithic integrated dual voltage regulators, based on the STM modulator voltage regulator approach. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. Nevertheless, it is suitable also in other applications where two stabilized voltages are required. The modular approach of this device allows to get easy also other features and functions when required. 3.2 Standby regulator The standby regulator uses an isolated collector vertical PNP transistor as a regulating element. With this structure very low dropout voltage at currents up to 100 mA is obtained. The dropout operation of the standby regulator is maintained down to 3 V input supply voltage. The output voltage is regulated up to the transient input supply voltage of 40 V. With this feature no functional interruption due to overvoltage pulses is generated. Doc ID 17243 Rev 2 11/20 Application information L4938ED, L4938EPD In the standby mode when the output 2 is disabled, the current consumption of the device (quiescent current) is less than 90 µA (14 V supply voltage). To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled. A second regulation path keeps the output voltage without load below 5.5 V even at high temperatures. 3.3 Output 2 voltage The output 2 regulator uses the same output structure as the standby regulator but rated for the output current of 400 mA. The output voltage is internally fixed to 5 V if ADJ is connected to VOUT2. The output 2 regulator can be switches OFF via the enable input. Figure 4. OUT2 Connecting a resistor divider R1E, R2E to the ADJ, OUT2 pin the output voltage 2 can be programmed to the value of R 1E ( R 2E + R ADJ )  V OUT2 = V OUT1  1 + ------------------------------------------------- R 2E ⋅ R ADJ   with RADJ = 60 K to 150 K and VOUT1 = 4.95 to 5.05 V. For an exact calculation the temperature coefficient (TC - 2000 pprm) of the internal resistor (RADJ) must be taken into account. Pin ADJ in this mode should not have a capacitive burden because this would reduce the phase margin of the regulator loop. 3.4 Reset circuit The reset circuit supervises the standby output voltage. The reset output (RES) is defined from VOUT ≥ 1 V. Even if VS is lacking, the reset generator is supplied by the output voltage VOUT1. The reset threshold of 4.7 V is defined with the internal reference voltage(a) and standby output divider, when pin PR is left open. The reset threshold voltage can be programmed in the range from 3.8 V to 4.7 V by connecting an external resistor from pin PR to GND. 12/20 Doc ID 17243 Rev 2 L4938ED, L4938EPD Application information The value of the programming resistor RPR can be calculated with: 22K R PR = ---------------------- – 92.9K 4.7K ------------ – 1 V RT 3.8V ≤ V RT ≤ 4.7V The reset pulse delay time tRD, is defined with the charge time of an external capacitor CT: C T ⋅ 0.6V t RDmin = -----------------------1μA C T ⋅ 1.4V t RDnom = -----------------------1μA The reaction time of the reset circuit originates from the noise immunity. Standby output voltage drops below the reset threshold only a bit longer than the reaction time results in a shorter reset delay time. The nominal reset delay time is generated for standby output voltage drops longer than approximately 50 µs. The minimum reset time is generated if reset condition only occurs for a short time triggering a reset pulse but not completely discharging CT. The reset can be related to output2 on request. If higher charge currents for the reset capacitor are required a resistors from pin CT to OUT1, may be used to increase the current. We recommended the use of 10 KΩ to 5 V as an output pull up. 3.5 Sense comparator The sense comparator compares an input signal with an internal voltage reference of typical 1.23 V. The use of an external voltage divider makes this comparator very flexible in the application. It can be used to supervise the input voltage either before or after the protection diode and to give additional information to the microprocessor like low voltage warnings. We recommended the use of 10 KΩ to 5 V as an output pull up. 3.6 Thermal protection Both outputs are provided with an overtemperature shutdown regulation power dissipation down to uncritical values. Output 2 shuts down approximately 10 K before output 1. Under normal conditions shutdown of output 2 allows the chip to cool down again. Thus output 1 is unaffected. The thermal shutdown reduces the output voltages until power dissipation and the flow of thermal energy out of the chip balance. 3.7 Transient sensitivity In proper operation (VOUT > 4.5 V) the reference is supplied by VOUT1 thus reducing sensitivity to input transients. a. The reference is alternatively supplied from VS or VOUT1. If one supply is present, the reference is operating. Doc ID 17243 Rev 2 13/20 Application information Figure 5. Reset generator Figure 6. Waveforms 14/20 L4938ED, L4938EPD Doc ID 17243 Rev 2 L4938ED, L4938EPD 3.8 Application information Input protection The Inputs Enable (EN) and Sense In (SI) are protected against negative transients. Figure 7 is showing the simplified schematic Figure 7. Input protection Figure 8. Input characteristics of SI, EN Doc ID 17243 Rev 2 15/20 Package and packing information L4938ED, L4938EPD 4 Package and packing information 4.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.2 SO-20 package information Table 11. SO-20 mechanical data mm Dim. Min. Max. A 2.35 2.65 A1 0.1 0.3 B 0.33 0.51 C 0.23 0.32 D 12.6 13 E 7.4 7.6 e 16/20 Typ. 1.27 H 10 10.65 h 0.25 0.75 L 0.4 1.27 K 0° 8° Doc ID 17243 Rev 2 L4938ED, L4938EPD Package and packing information Figure 9. 4.3 SO-20 package dimensions PowerSO-20 package information Table 12. PowerSO-20 mechanical data mm Dim. Min. Typ. A a1 Max. 3.6 0.1 0.3 a2 3.3 a3 0 0.1 b 0.4 0.53 c 0.23 0.32 D(1) 15.8 16 D1 9.4 9.8 E 13.9 14.5 e 1.27 e3 11.43 E1 (1) 10.9 E2 E3 11.1 2.9 5.8 Doc ID 17243 Rev 2 6.2 17/20 Package and packing information Table 12. L4938ED, L4938EPD PowerSO-20 mechanical data (continued) mm Dim. Min. Typ. Max. G 0 0.1 H 15.5 15.9 h 1.1 L 0.8 1.1 N 10° S 8° T 10 1. "D and F" do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006"). - Critical dimensions: "E", "G" and "a3" Figure 10. PowerSO-20 package dimensions N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 h x 45˚ 1 0 PSO20MEC D1 0056635 I 18/20 Doc ID 17243 Rev 2 L4938ED, L4938EPD 5 Revision history Revision history Table 13. Document revision history Date Revision Changes 10-Mar-2010 1 Initial release. 20-Sep-2013 2 Updated disclaimer. Doc ID 17243 Rev 2 19/20 L4938ED, L4938EPD Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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