L99MM70XP
Integrated microprocessor driven device intended
for LIN controlled exterior mirrors
Features
■
5 V low-drop voltage regulator (150 mA max.)
■
Embedded LIN transceiver: 2.0/2.1 compliant
and SAEJ2602 compatible
■
Independent control of mirror adjustment
motors
■
Charge pump output for active reverse polarity
protection via an external N-channel MOSFET
■
One full bridge for 3 A load (Ron = 300 m)
■
■
Two (three) half bridges for 0.5 A load
(Ron = 1.6 )
STM standard serial peripheral interface for
control and diagnosis
■
INH input for external CAN transceiver
■
One configurable high-side driver for up to
1.5 A load (Ron = 500 m/ 10 Watt bulb
control, or 1600 m / LED control)
Two high-side driver for 0.5 A load
(Ron = 1600 m)
■
One low-side driver 0.5 A load
(Ron = 1600 m) used as half bridge with highside driver for independent mirror axis control
■
One high-side driver for 6 A load
(Ron = 90 m)
■
One high-side driver for 0.5 A load
(Ron = 1600 m) to supply an external
MOSFET to drive an EC-glass
■
Integrated EC glass control via an external
MOSFET with fast discharge path: EC-glass
can be discharged to GND or to -1 V
■
Programmable soft start function to drive loads
with higher inrush currents (>6 A, >1.5 A)
■
Very low current consumption modes
■
All outputs short-circuit and overtemperature
protected
Two thermal shutdown thresholds and early
temperature warning
■
Current monitor output for all high-side drivers
■
Open-load diagnostic for all outputs
■
Overload diagnostic for all outputs
■
3 PWM control signals for all outputs
September 2013
Applications
■
■
■
PowerSSO-36
LIN controlled mirror
Description
The L99MM70XP is a microcontroller driven
multifunctional system ASSP dedicated for LIN
controlled wing mirror applications. The device
contains a voltage regulator to supply the
microcontroller and a LIN2.1 physical layer. Up to
3 DC motors and five grounded resistive loads
can independently be driven with four (five) half
bridges and five high-side driver. The EC-glass
control block provides overvoltage protection with
a fast discharge path versus GND and a negative
discharge path for future EC-glass characteristics.
The integrated ST SPI controls all operation
modes (forward, reverse, brake and highimpedance) and provides all the diagnostic
information.
Table 1.
Device summary
Order codes
Package
PowerSSO-36
Doc ID 022637 Rev 2
Tube
Tape and reel
L99MM70XP
L99MM70XPTR
1/68
www.st.com
1
Contents
L99MM70XP
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3
VCC-standby mode
3.2.4
VBAT-standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6
Time-out watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7
Passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
Reset output (NRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
VCC fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10
Output drivers OUT1 … OUT9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.1
Load condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.2
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.3
PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.4
Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.5
Programmable soft start function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11
Controller for electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12
LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12.1
General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12.2
LIN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12.3
Wake-up (from LIN bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 23
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1
2/68
Active mode
3.3
3.13
4
3.2.1
Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 022637 Rev 2
L99MM70XP
Contents
4.1.1
Overvoltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2
Diagnosis functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 28
4.4
Half bridge outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5
High-side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.3
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.4
Voltage regulator VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.5
Reset output (VCC supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.6
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.7
Current monitor output CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.8
Charge pump output CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.9
Outputs OUT1 – OUT9, ECV, ECFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
On-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.9.2
Switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.9.3
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.9.4
Electrochrome control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.9.5
INH/PWM3 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.10
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.11
SPI and PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.12
9
8.9.1
8.11.1
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.11.2
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.11.3
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Input PWM2 for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 022637 Rev 2
3/68
Contents
L99MM70XP
9.1
10
11
4/68
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1.1
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1.2
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1.3
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1.4
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1.5
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1.6
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1.7
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Package and packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.2
PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Doc ID 022637 Rev 2
L99MM70XP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Voltage regulator VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset output (VCC supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current monitor output CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Charge pump output CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
On-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Electrochrome control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
INH/PWM3 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Input PWM2 for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Control registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Control registers 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Control registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Control registers 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Configuration register, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Status register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Doc ID 022637 Rev 2
5/68
List of tables
Table 49.
Table 50.
Table 51.
6/68
L99MM70XP
Status register 4, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Doc ID 022637 Rev 2
L99MM70XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage regulator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Example of programmable soft start function for inductive loads . . . . . . . . . . . . . . . . . . . . 20
SPI global error information output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal data of PowerSSO-36 and PowerSO-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Watchdog late and safe window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrochrome mirror driver with mirror referenced to ground . . . . . . . . . . . . . . . . . . . . . . 42
Electrochrome mirror driver with mirror referenced to ECFD for negative discharge . . . . . 42
LIN transmit and receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SPI input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SPI maximum clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Doc ID 022637 Rev 2
7/68
Block diagram
L99MM70XP
1
Block diagram
Figure 1.
Block diagram
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Doc ID 022637 Rev 2
L99MM70XP
Pin definitions and functions
2
Pin definitions and functions
Table 2.
Pin definition and functions
Pin
Symbol
Function
1, 18,
19, 36
GND
Ground:
reference potential
Note: For the capability of driving the full current at the outputs all pins of GND must be
externally connected!
2, 7, 32
VS (Power1)
22
VS (Power2)
3, 4
35, 5,
6, 21,
20
OUT9
Power supply voltage for outputs OUTX and ECFD (external reverse protection required):
for this input a ceramic capacitor as close as possible to GND is recommended.
Note: For the capability of driving the full current at the outputs all pins of VS must be
externally connected! Pins 2, 7 and 32 are internally connected, too. Pin 22 is the
power supply for outputs OUT4, 5 and 6.
High-side driver output 9:
the output is built by a high-side switch and is intended for resistive loads, hence the
internal reverse diode from GND to the output is missing.For ESD reason a diode to GND
is present but the energy which can be dissipated is limited. The high-side driver is a
power DMOS transistor with an internal parasitic reverse diode from the output to VS
(bulk-drain-diode). The output is overcurrent and open-load protected.
Note: For the capability of driving the full current at the outputs both pins of OUT9 must
be externally connected!
Half bridge outputs 1,2,3,4,5:
the output is built by a high-side and a low-side switch, which are internally connected.
OUT1, OUT2, The output stage of both switches is a power DMOS transistor.
OUT3, OUT4,
Each driver has an internal parasitic reverse diode (bulk drain diode: high-side driver from
OUT5
output to VS, low-side driver from GND to output). This output is overcurrent and openload protected.
CSN
Chip select not input:
this input is low active and requires CMOS logic levels. The serial data transfer between
the L99MM70XP and the microcontroller is enabled by pulling the input CSN to low-level.
9
CM
Current monitor output:
depending on the selected multiplexer bits of the control register this output sources an
image of the instant current through the corresponding high-side driver with a ratio of
1/10000 or 1/2000.
10
DO
Serial data output:
the diagnosis data is available via the SPI and this 3-state output. The output remains in
3-state, if the chip is not selected by the input CSN (CSN = high).
11
DI
Serial data input:
the input requires CMOS logic levels and receives serial data from the microcontroller.
The data is a 24 bit control word and the most significant bit (MSB, bit 23) is transferred
first.
12
CLK
Serial clock input:
this input controls the internal shift register of the SPI and requires CMOS logic levels.
13
VCC
Voltage regulator output:
5 V supply e.g. microcontroller, CAN transceiver.
14
RXD
Receiver output of the LIN 2.1 transceiver.
15
TXD
Transmitter input of the LIN 2.1 transceiver
8
Doc ID 022637 Rev 2
9/68
Pin definitions and functions
Table 2.
L99MM70XP
Pin definition and functions (continued)
Pin
Symbol
Function
16
VS (Reg)
Power supply voltage (external reverse protection required):
for this input a ceramic capacitor as close as possible to GND and an electrolytic capacitor
to buffer the voltage during negative transients is recommended.
17
LIN
LIN bus line
23
OUT6
High-side driver output 6:
The output is built by a high-side switch and is intended for resistive loads; hence the
internal reverse diode from GND to the output is missing. For ESD reason a diode to GND
is present but the energy which can be dissipated is limited.
The high-side driver is a power DMOS transistor with an internal parasitic reverse diode
from the output to VS (bulk-drain-diode). The output is overcurrent and open-load
protected.
24
INH/PWM3
Inhibit input:
wake-up from external CAN transceiver. This pin has a second functionality. The
microcontroller can use the INH signal to provide a third PWM input for the output OUT8.
25
CP
26
PWM1
PWM1 input:
This input signal can be used to control the drivers OUT1-OUT5, OUT7, and OUT9 by an
external PWM signal.
27
NRES
Low active reset output to the microcontroller:
internal pull up of typ. 100k
28
PWM2
PWM2 input:
This input signal can be used to control the driver OUT6 by an external PWM signal.
29
ECDR
ECDR: using the device in EC control mode this pin is used to control the gate of an
external MOSFET.
OUT8
High-side driver output 8:
see OUT6
Note: This output can be configured to supply a bulb with low on-resistance or a LED
with higher on-resistance in a different application.
30
31
33
34
10/68
Charge pump output:
This output is provided to drive the gate of an external n-channel power MOS used for
reverse polarity protection (see Figure 1).
OUT7/EC
High-side driver output 7:
see OUT6
Note: Beside the bit 8 in control register 2 this output can be switched on setting bit 0 for
electrochrome control mode with higher priority.
ECFD
ECFD:
using the device in EC control mode this pin is used as “virtual GND” for the EC-glass. For
EC-glasses, that require a negative discharge voltage, this supplies the fast discharge
voltage. If no EC-glass is used, this pin must be connected to ground.
ECV
ECV:
Using the device in EC control mode this pin is used as voltage monitor input. For fast
discharge an additional low-side-switch is implemented.
This pin can be used as “stand alone” low-side as well. This output is intended for resistive
loads only
Doc ID 022637 Rev 2
L99MM70XP
Figure 2.
Pin definitions and functions
Pin connection (top view)
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Doc ID 022637 Rev 2
11/68
Description
L99MM70XP
3
Description
3.1
Voltage regulator
The L99MM70XP contains a fully protected low drop voltage regulator, which is designed for
very fast transient response.
The output voltage is stable with load capacitors > 220 nF.
The voltage regulator provides 5 V supply voltage and up to 100 mA continuous load current
for the external digital logic (microcontroller, etc...). In addition the regulator VCC drives the
L99MM70XP internal 5 V loads. The voltage regulator is protected against overload and
overtemperature. An external reverse current protection has to be provided by the
application circuitry to prevent the input capacitor from being discharged by negative
transients or low input voltage. The output voltage precision is better than ±2 % (incl.
temperature drift and line-/load regulation) for operating mode; respectively ±3 % during low
current mode. Current limitation of the regulator ensures fast charge of external bypass
capacitors. The output voltage is stable for ceramic load capacitors > 220 nF.
If device temperature exceeds TSD1 threshold, all outputs (OUTx, LIN) are deactivated
except VCC. Hence the microcontroller has the possibility for interaction or error logging. In
case of exceeding TSD2 threshold (TSD2 > TSD1), also VCC is deactivated (see Figure 8).
A timer is started and the voltage regulator is deactivated for tTSD = 1 s.
During this time, all other wake-up sources (LIN) are disabled. After 1 s, the voltage
regulator tries to restart automatically. If the restart fails 6 times without clearing and thermal
shutdown condition still exists, the L99MM70XP enters the VBAT-standby mode.
In case of short to GND at VCC after initial turn on (VCC < 2 V for at least 4 ms) the
L99MM70XP enters the VBAT-standby mode. Reactivation (wake-up) of the device can be
achieved with signals from LIN or INH.
12/68
Doc ID 022637 Rev 2
L99MM70XP
Figure 3.
Description
Voltage regulator operation
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3.2
Power control in operating modes
The L99MM70XP can be operated in 4 different operating modes:
3.2.1
●
Active
●
Flash
●
VCC-standby
●
VBAT-standby
Active mode
All functions are available. After at most 300 µs, the outputs can be enabled.
3.2.2
Flash mode
To disable the watchdog feature a Flash program mode is available. The mode can be
entered if the following condition occurs:
VPWM2 VFlash
Watchdog is disabled but all other functions are the same as in active mode.
Doc ID 022637 Rev 2
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Description
L99MM70XP
Note:
“High” level for flash mode selection is VPWM2 VFlash. For all other operation modes,
standard 5 V logic signals are required.
3.2.3
VCC-standby mode
Outputs and internal loads are switched off. To supply the microcontroller in a low power
mode, the voltage regulator (VCC) remains active. The intention of the VCC-standby mode is
to preserve the RAM contents.
A LIN wake-up event sets the device into the active mode and forces the RXD pin to the
low-level.
A wake-up over INH switches device in active mode and start the watchdog.
The wake-up via SPI switches device in active mode. A status bit indicates the wake-up
source.
During the VCC-standby mode, the current at VCC is monitored.
The transition from active mode to VCC-standby mode is controlled by SPI.
3.2.4
VBAT-standby mode
To achieve minimum current consumption during VBAT-standby mode, all L99MM70XP
functions are switched off.
In VBAT-standby mode the current consumption of the L99MM70XP is reduced to 8 µA.
The transition from active mode to VBAT-standby mode is controlled by SPI.
3.3
Wake-up events
A wake-up from standby mode switches the device to active mode. This can be initiated by
one or more of the following sources:
●
Change of the LIN state at LIN bus interfaces
●
SPI access in VCC-standby mode (CSN is low and first rising edge on CLK)
●
A current at the INH pin (I > 120 µA) controlled by the CAN-transceiver (the CAN
transceiver is not a part of the IC).
Table 3.
Wake-up events
Wake-up source
Description
LIN
Always active
INH
Always active
VCC ICMP
Device remains in VCC-standby mode with
watchdog enabled (If ICMP = 0) and VCC goes
into high current mode (increased current
consumption). No interrupt is generated.
SPI access
Always active (except in VBAT-standby mode)
LIN wake-up events in VCC-standby mode generate a low-pulse at RXD for 56 µs.
Wake-up from VCC-standby by SPI access might be used to check the interrupt service
handler.
14/68
Doc ID 022637 Rev 2
L99MM70XP
3.4
Description
Functional overview (truth table)
Table 4.
Functional overview (truth table)
Operating modes
Function
Comments
Active mode
VCC-standby
static mode
VBAT-standby
static mode
Voltage regulator, VCC VOUT = 5 V
On
On(1)
Off
NRES
On
On
Off
Window watchdog
VCC monitor
On
Off (ON if ICC > ICMP
and ICMP = 0)
Off
LIN
LIN 2.1
On
Off(2)
Off(2)
1. Supply the processor in low current mode.
2. The bus state is internally stored when going to standby mode. A change of bus state leads to a wake-up
after exceeding of internal filter time.
Doc ID 022637 Rev 2
15/68
Description
Figure 4.
L99MM70XP
Operating modes, main states
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3.5
Interrupt
In case of VCC-standby mode and (ICC > ICMPris), the device remains in standby mode, the
VCC regulator switches to high current mode and the watchdog is started. No interrupt is
generated.
16/68
Doc ID 022637 Rev 2
L99MM70XP
Description
If bit NINTEN (CR1/Bit5, default value is set) is set, the RXD pin works also as interrupt
output in case of wake-up by LIN or INH or SPI in VCC-standby mode. This pin is pulled down
for 56 µs.
If it is not set, RXD is pulled down for 56us only for LIN wake-up.
3.6
Time-out watchdog
During normal operation, the watchdog monitors the microcontroller within a 100 ms trigger
cycle.
In VBAT-standby and flash program modes, the watchdog circuit is automatically disabled.
After power on or standby mode, the watchdog is started immediately with the normal cycle
time (100 ms). The microcontroller has to run its own setup and then to trigger the watchdog
via the SPI. The trigger is finally accepted when the CSN input becomes high after the
transmission of the SPI word.
Writing ‘1’ to the watchdog trigger bit restarts the watchdog. Subsequently, the
microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the
safe trigger area (refer to Figure 10). A correct watchdog trigger signal immediately starts
the next cycle.
If the micro does not serve the watchdog in time, the watchdog pulls low the NRES output
for 2 ms. At the same time, the watchdog failure counter (WDFAIL) is incremented by 1 and
the device enters passive mode.
After 8 watchdog failures in sequence, the VCC regulator is switched off for 200 ms. If
subsequently, 7 additional watchdog failures occur, the VCC regulator is completely turned
off and the device goes into VBAT-standby mode until a wake-up occurs.
In case of a watchdog failure, the outputs (OUTx) are switched off and the device enters
passive mode (i.e. all control registers are set to default values).
Doc ID 022637 Rev 2
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Description
Figure 5.
L99MM70XP
Watchdog state diagram
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3.7
Passive mode
L99MM70XP enters passive mode in case of:
●
Watchdog failure
●
VCC under voltage (NRES)
●
Thermal shutdown TSD2
●
SPI data in stuck at 0 or 1
In passive mode all control registers (except the reset level bit RSTLVL) and the
configuration register are set to default so that all outputs are switched off. The PASSIVE bit
inside the global status byte is set to “1”. The first valid SPI frame after entering the passive
mode resets the PASSIVE bit to “0” and leaves passive.
3.8
Reset output (NRES)
If VCC is turned on and the voltage exceeds the VCC reset threshold, the reset output NRES
is pulled up by internal pull up resistor to VCC voltage after a 2 ms reset delay time. This is
necessary for a defined start of the microcontroller when the application is switched on.
A low active reset pulse (2 ms) is generated in case of:
18/68
●
VCC drops below Vrth (configurable by SPI) for more than 8 µs (VCC under voltage)
●
Watchdog failure
Doc ID 022637 Rev 2
L99MM70XP
Description
If NRES is pulled low, all control registers (except the reset level bit RSTLVL) and the
configuration register are set to default. In both cases, the device enters passive mode.
3.9
VCC fail
The VCC regulator output voltage is monitored.
In case of a drop below the VCC fail threshold (VCC < 2 V typ. for t > 2 µs), the VCC fail bit is
latched. The fail bit is cleared by a dedicated SPI command.
If 4 ms after turn on of the regulator the VCC voltage is below the VCC fail threshold, the
L99MM70XP identifies a short circuit condition at the regulator output and switch it off.
In case of VCC short to GND failure the device enters VBAT-standby mode automatically.
3.10
Output drivers OUT1 … OUT9
3.10.1
Load condition
Each half bridge is built by internally connected high-side and low-side power DMOS
transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can
be driven at the outputs OUT1 to OUT5 without external free-wheeling diodes. The drivers
OUT6, OUT7, OUT8, OUT9, ECV and ECFD are intended to drive resistive loads. Therefore
only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in
freewheeling condition. For inductive loads (L > 100 µH) an external free wheeling diode
connected between GND and the corresponding output is required.
3.10.2
Current monitor
The current monitor output sources a current image at the current monitor output, which has
two fixed ratios of the instantaneous current of the selected high-side driver. Outputs with a
resistance of 500 m and higher have a ratio of 1/2000 and those with a lower resistance of
1/10000. The signal at output CM is blanked after switching on the driver until correct
settlement of the circuitry (at least for 32 µs). The bits 0 to 3 of the control register 3 define
which of the outputs are multiplexed to the current monitor output CM. The current monitor
output allows a more precise analysis of the actual state of the load rather than the detection
of an open-load or overload condition. For example, it can be used to detect the motor state
(starting, free running, stalled). Moreover, it is possible to control the power of the defroster
more precisely by measuring the load current.
3.10.3
PWM inputs
Each driver has a corresponding PWM enable bit, which can be programmed by the SPI
interface. If the PWM enable bit is set in control register 2 or 3, the output is controlled by the
logically AND-combination of the PWM signal and the output control bit in control register 0
or 1. The outputs OUT1-5, 7, 9, ECV are controlled by the PWM1 input, the output OUT6 is
controlled by the input PMW2 and output OUT8 is controlled by INH/PWM3. Thus, the three
PWM inputs can be used to dim three lamps independently by external PWM signals.
Switching off the outputs, a delay of maximum 300 µs is introduced (see also Table 18 in
Section 8.9.2: Switching times), hence the off time of the PWM input signal should be at
least 300 µs.
Doc ID 022637 Rev 2
19/68
Description
3.10.4
L99MM70XP
Cross current protection
The half bridges of the device are cross current protected by an internal delay time. If one
driver (LS or HS) is turned off, the activation of the other driver of the same half bridge is
automatically delayed by the cross current protection time. After the cross current protection
time is expired, the slew-rate limited switch off phase of the driver is changed to a fast turnoff phase and the opposite driver is turned on with slew-rate limitation. Due to this behavior,
it is always guaranteed that the previously activated driver is completely turned off before
the opposite driver starts to conduct.
3.10.5
Programmable soft start function
Loads with startup currents higher than the overcurrent limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable soft start function (i.e. overcurrent recovery mode). Each driver has a
corresponding overcurrent recovery bit. If this bit is set, the device automatically switches
the outputs on again after a programmable recovery time. The duty cycle in overcurrent
condition can be programmed by the SPI interface to about 12 % or 25 %. The PWM
modulated current provides sufficient average current to power-up the load (e.g. heat up the
bulb) until the load reaches operating condition. The PWM frequency settles at 1.7 kHz and
3 kHz.
The device itself cannot distinguish between a real overload and a non-linear load like a light
bulb. A real overload condition can only be qualified by time. As an example, the
microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the
first 50 ms. After clearing the recovery bit, the output is automatically switched off, if the
overload condition remains.
Figure 6.
Example of programmable soft start function for inductive loads
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20/68
Doc ID 022637 Rev 2
L99MM70XP
3.11
Description
Controller for electrochromic glass
The voltage of an electrochromic element connected at pin ECV can be controlled to a
target value, which is set by the bits EC (Control register 2, bits 6 down to 1). Setting
bit ECON (control register 2, bit 0) enables this function. An on-chip differential amplifier and
an external MOS source follower, with its gate connected to pin ECDR, and which drives the
electrochrome mirror voltage at pin ECV, form the control loop. The drain of the external
MOS transistor is supplied by OUT7. A diode from pin ECV (anode) to pin ECDR (cathode)
has been placed on the chip to protect the external MOS source follower. A capacitor of at
least 5 nF has to be added to pin ECDR for loop-stability. The target voltage is binary coded
with a full-scale range of 1.5 V. If bit ECVL (control register 3, bit 5) is set to '1', the maximum
controller output voltage is clamped to 1.2 V without changing the resolution of bits
EC. When programming the ECVLS driver to on-state, the voltage at pin ECV is pulled
to ground by a 1.6 Ohm low-side switch until the voltage at pin ECV is less than dVECVhi
higher than the target voltage (fast discharge).
The status of the voltage control loop is reported via SPI. Bit ECVO (status register 3, bit 4)
is set, if the voltage at pin ECV is higher, whereas bit ECVNR (status register 3, bit 5) is set,
if the voltage at pin ECV is lower than the target value. Both status bits are valid, if the
voltage is stable for at least the ECVO/ECVNR filter time and are not latched.
Since OUT7 is the output of a high-side driver, it contains the same diagnose functions as
the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched
off). In electrochrome mode, OUT10 cannot be controlled by PWM mode. For EMS reasons
the loop capacitor at pin ECDR as well as the capacitor between ECV and GND have to be
placed to the respective pins as close as possible (see Figure 13 for details).
If the electrochrome element is connected between the pins ECV and ECFD instead
between ECV and ground, a negative voltage can be applied to the device by pulling ECFD
to a higher value than ECV, which is connected to ground by a 1.6 Ohm low-side switch. In
this mode the voltage at pin ECFD is controlled to the target value defined by the register
EC. This is done using an on-chip source-follower transistor (see Figure 14 for
details). The negative discharge is enabled by setting bit ECND (control register 2, bit 7) to
‘1’.
During normal (positive) voltage control the low-side driver at pin ECFD must be switched
on to connect the electrochrome element to ground.
Pin ECDR is pulled resistively (RECDRDIS) to ground while not in electrochrome mode.
Doc ID 022637 Rev 2
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Description
L99MM70XP
3.12
LIN bus interface
3.12.1
General features
●
Speed communication up to 20 kbit/s
●
High speed Flash mode 100 kbit/s
●
LIN 2.1 compliant (SAEJ2602 compatible) transceiver
●
Function range from +40 V to -18 V DC at LIN pin
●
GND disconnection fail safe at module level
●
Off mode: does not disturb network
●
GND shift operation at system level
●
Microcontroller Interface with CMOS compatible I/O pins
●
Pull up internal resistor
●
ESD: immunity against automotive transients per ISO7637 specification
●
Matched output slopes and propagation delay
In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
3.12.2
LIN error handling
The L99MM70XP provides the following 3 error handling features which are not described in
the LIN Specifications V2.1, but are realized in different stand alone LIN
transceivers/microcontrollers to switch the application back to normal operation mode.
Dominant TXD time out
A permanent low-level on pin TXD would force the bus into a permanent dominant state,
blocking all network communication. If pin TXD remains at low-level for longer than the TXD
dominant timeout tdom(TXD), the transmitter is disabled. The status bit is latched and can be
read and optionally cleared by SPI. The transmitter remains disabled until the status register
is cleared. This feature can be disabled via SPI.
LIN BUS permanent recessive
If TXD changes to low-level but the bus does not follow within trec(LIN), the transmitter is
disabled. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter remains disabled until the status register is cleared.
LIN BUS permanent dominant
If a dominant state on the bus persists for longer than tdom(LIN) a permanent dominant status
is detected. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter of the transceiver is not disabled.
Note:
A wake-up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.
3.12.3
Wake-up (from LIN bus)
In standby mode the L99MM70XP can receive a wake-up from LIN bus. For the wake-up
feature the L99MM70XP logic differentiates two different conditions.
22/68
Doc ID 022637 Rev 2
L99MM70XP
Description
Normal wake-up
Normal wake-up can occur when the L99MM70XP was set in standby mode while a
recessive (state was present on the bus. A dominant level at LIN for t > tlinbus, switches the
L99MM70XP to active mode. An interrupt is generated at the RXD/NINT pin.
Wake-up from short to GND condition
If the L99MM70XP was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for tlinbus, switches the L99MM70XP to active mode. An interrupt is
generated at the RXD/NINT pin.
3.13
Serial peripheral interface (ST SPI standard)
A 24 bit ST-SPI is used for bi-directional communication with the microcontroller.
During active mode, the SPI
Note:
●
Triggers the watchdog
●
Controls the modes and status of all L99MM70XP modules (incl. input and output
drivers)
●
Provides driver output diagnostic
●
Provides L99MM70XP diagnostic (incl. overtemperature warning, L99MM70XP
operation status)
During standby modes, the SPI is generally deactivated.
The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:
CPOL = 0 and CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin are needed to communicate with the device. A fault condition
can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the global error flag
(fault condition) of the device (see Figure 7). This operation does not cause the
communication error bit in the global status byte to be set.
Doc ID 022637 Rev 2
23/68
Description
L99MM70XP
Figure 7.
SPI global error information output
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Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal activates the output driver and a
serial communication can be started. The state during CSN = 0 is called a communication
frame.
Serial Data In (DI)
The input pin is used to transfer data serially into the device. The data applied to the DI are
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register is transferred to data
input register. The writing to the selected data input register is only enabled if exactly 24 bits
are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses
are counted within one frame the complete frame is ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
24/68
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Doc ID 022637 Rev 2
L99MM70XP
Description
Serial Data Out (DO)
The data output driver is activated by a logical low-level at the CSN input and goes from high
impedance to a low or high-level depending on the global error flag (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin transfers the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK shifts out the next bit.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The Data Input
(DI) is sampled at the rising edge of the CLK and the Data Output (DO) changes with the
falling edge of the CLK signal.
Doc ID 022637 Rev 2
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Protection and diagnosis
L99MM70XP
4
Protection and diagnosis
4.1
Power supply fail
Overvoltage and undervoltage detection on VS (Power1).
4.1.1
Overvoltage
If the supply voltage VS rises above the overvoltage threshold (VSOV) for more than 56 µs
(typ.)
4.1.2
●
The outputs OUT1-9, ECV, ECFD and LIN are switched to high impedance state (load
protection). Electrochrome mode is switched off. If the bit OVUVR is set to 0, the
outputs are re-enabled automatically if the overvoltage condition is removed. If it is set
to 1, then the overvoltage bit has to be cleared to re-enable the outputs. LIN is always
automatically re-enabled.
●
The overvoltage bit is set and can be cleared with a “read and clear” command.
Undervoltage
If the supply voltage VS drops below the under voltage threshold voltage (VSUV) for more
than 56 µs (typ.)
26/68
●
The outputs OUT1-9, ECV, ECFD and LIN are switched to high impedance state.
Electrochrome mode is switched off. If the bit OVUVR is set to 0, the outputs are reenabled automatically if the under voltage condition is removed. If it is set to 1, then the
under voltage bit has to be cleared to re-enable the outputs. LIN is always automatically
re-enabled.
●
The under voltage bit is set and can be cleared with the “read and clear” command.
Doc ID 022637 Rev 2
L99MM70XP
4.2
Protection and diagnosis
Diagnosis functions
Digital diagnosis features are provided by SPI:
●
VCC reset (threshold programmable)
●
Overtemperature including pre warning
●
Open-load status separately for each output OUT1-9, ECV, ECFD
●
Overload status separately for each output OUT1-9, ECV, ECFD
●
VS-supply overvoltage undervoltage
●
VCC fail bit
●
Chip reset bit (start from power-on reset)
●
Number of unsuccessful VCC restarts after thermal shutdown
●
Number of sequential watchdog failures
●
LIN diagnosis (permanent recessive/dominant, dominant TXD)
●
Device state (wake-up from VCC-standby or VBAT-standby)
●
Forced VBAT-standby after WD-fail, forced VBAT-standby after overtemperature
●
Watchdog timer state (diagnosis of watchdog)
●
Passive mode
●
SPI communication error
Doc ID 022637 Rev 2
27/68
Protection and diagnosis
Figure 8.
L99MM70XP
Thermal shutdown protection and diagnosis
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4.3
Temperature warning and thermal shutdown
See Figure 8.
4.4
Half bridge outputs
The device provides a total of 5 half bridge outputs OUT1,2,3,4,5 to drive inductive loads
(e.g. motor).
The half bridges are protected against
28/68
●
Overvoltage and undervoltage
●
Overload (short circuit)
●
Overtemperature with pre warning
Doc ID 022637 Rev 2
L99MM70XP
Protection and diagnosis
If the output current exceeds the current shutdown threshold the output transistor is turned
off and the corresponding diagnosis bit of the output is latched. The status can be read and
cleared from SPI. If the overcurrent recovery mode is set for this output, the output is
switched on again in order to provide a soft start function (see Section 3.10.5:
Programmable soft start function) and the status bit is cleared automatically. Otherwise the
output stays off until the status bit is cleared.
The outputs are automatically switched off in case of passive mode, VS undervoltage, VS
overvoltage, thermal shutdown (TSD1 and TSD2) or stuck at 1/0 condition at DI.
4.5
High-side driver outputs
The device provides a total of 4 high-side outputs OUT6,7,8,9 to drive LED or defroster.
The high-side outputs are protected against
●
Overvoltage and undervoltage (can be masked by SPI)
●
Overload (short circuit)
●
Overtemperature with pre warning
If the output current exceeds the current shutdown threshold the output transistor is turned
off and the corresponding diagnosis bit of the output is latched. The status can be read and
cleared from SPI. If the overcurrent recovery mode is set for this output, the output is
switched on again in order to provide a soft start function (see Section 3.10.5:
Programmable soft start function) and the status bit is cleared automatically. Otherwise the
output stays off until the status bit is cleared.
The outputs are automatically switched off in case of passive mode, VS undervoltage, VS
overvoltage, thermal shutdown (TSD1 and TSD2) or stuck at 1/0 condition at DI.
Note:
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds, the
current load must be limited to this nominal current.
Doc ID 022637 Rev 2
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Absolute maximum ratings
5
L99MM70XP
Absolute maximum ratings
Table 5.
Absolute maximum ratings
Value
[DC voltage]
Unit
DC supply voltage/jump start
-0.3 to +28
V
Load dump
-0.3 to +40
V
VS < 5.2 V
-0.3 to VS + 0.3
V
VS > 5.2 V
-0.3 to 5.5
V
VDI, VCLK, VTXD,
VCSN, VDO,
Logic input/output voltage range
VRXD, VNRES,
VCM, VPWM1
-0.3 to VCC + 0.3
V
VPWM2, VPWM3
Logic input voltage
-0.3 to VS + 0.3
V
VCP
Charge pump output
-25 to 39
V
VOUTn,ECDR,ECV,
Static output voltage (n = 1 to 9)
-0.3 to VS + 0.3
V
Symbol
VS
VCC
Parameter/test condition
Stabilized supply voltage, logic supply
ECFD
IOUT2,3,4,6,7,ECV,
ECFD, IVS(REG)
Output current(1)
±1.25
A
IOUT1,5,8,9,
IVS(Power),IGND
Output current(1)
±5
A
IPin to Pin
Maximum output current between pin 2 and 32 or 7
and 32(1)
±1
A
VLIN
LIN bus I/O voltage range
-20 to +40
V
1. Values for the absolute maximum current through bond wire. It doesn’t consider maximum power
dissipation or other limits.
Note:
30/68
All maximum ratings are absolute ratings. Exceeding the limitation of any of these values
may cause an irreversible damage of the integrated circuit!
Doc ID 022637 Rev 2
L99MM70XP
6
ESD protection
ESD protection
Table 6.
ESD protection
Parameter
All pins(1)
All output pins
(2)
(OUT1-OUT9, ECV, ECFD)
LIN(2)
All pins (charge device model)
Value
Unit
±2
kV
±4
kV
±8
(4)
Corner pins (charge device model)(4)
(3)
kV
±500
V
±750
V
1. HBM (human body model, 100 pF, 1.5 k) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.
2. HBM with all unzapped pins grounded.
3. With external components.
4. According charged device model: JEDEC JESD22-C101D.
For detailed information please see EMC report from IBEE Zwickau (available on request).
Doc ID 022637 Rev 2
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Thermal data
7
L99MM70XP
Thermal data
Table 7.
Operating junction temperature
Symbol
Tj
Note:
Parameter
Operating junction temperature
Value
Unit
-40 to 150
°C
RthjA, typical value, without PCB.
Table 8.
Temperature warning and thermal shutdown
Symbol
TW ON
TSD1 OFF
TSD2 OFF
Parameter
Min.
Typ.
Max.
Unit
Tj(1)
130
140
150
°C
Thermal shutdown junction temperature 1
Tj
(1)
140
150
160
°C
Thermal shutdown junction temperature 2
Tj(1)
150
160
170
°C
Thermal overtemperature warning threshold
1. Non-overlapping.
Figure 9.
Thermal data of PowerSSO-36 and PowerSO-36
GAPGMS 00013
32/68
Doc ID 022637 Rev 2
L99MM70XP
Electrical characteristics
8
Electrical characteristics
8.1
Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V VS 18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
Table 9.
Supply and supply monitoring
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSUV ON
VS undervoltage threshold voltage
VS increasing
5.7
7.2
V
VSUV OFF
VS undervoltage threshold voltage
VS decreasing
5.5
6.9
V
VSUV hyst
VS undervoltage hysteresis
VSUV ON - VSUV OFF
VSOV OFF
VS overvoltage threshold voltage
VS increasing
18.1
24.5
V
VSOV ON
VS overvoltage threshold voltage
VS decreasing
17.5
23.5
V
VSOV hyst
VS overvoltage hysteresis
VSOV OFF - VSOV ON
IVS(act)
IVSREG(act)
V
1
V
high(1)(2)
7
20
mA
VSREG = 13.5 V, TXD LIN high
IVCC = 0(2)
6
12
mA
Current consumption in active mode VS = 13.5 V, TXD LIN
Current consumption in active mode
0.5
IVS(BAT)
Current consumption in VBAT-standby
VS = 13.5 V(1)(2)
mode
1
µA
IVS(BAT)
Current consumption in VBAT-standby
VS = 13.5 V(1)(3)
mode
2
µA
IVSREG(BAT)
Current consumption in VBAT-standby
VSREG = 13.5 V(2)
mode
1
8
16
µA
IVSREG(BAT)
Current consumption in VBAT-standby
VSREG = 13.5 V(3)
mode
2
12
24
µA
Current consumption in VBAT-standby
VS, VSREG = 13.5 V,
mode with a pending wake-up
2 V < LIN < VS - 3.5 V
request
800
1200
µA
Current consumption in VCC-standby
mode with a pending wake-up
request
VS, VSREG = 13.5 V,
2 V < LIN < VS - 3.5 V
800
1200
µA
IVS(VCC)
Current consumption in VCC-standby
mode
VS = 13.5 V, voltage regulator VCC
active, no wake-up request
IVSREG(VCC)
Current consumption in VCC-standby
mode
VS = 13.5 V, voltage regulator VCC
active, no wake-up request,
IVCC = 0(2)
10
45
70
µA
IVSREG(VCC)
Current consumption in VCC-standby
mode
VS = 13.5 V, voltage regulator VCC
active, no wake-up request,
IVCC = 0(3)
15
67
105
µA
IVS(VBAT)
wupend
IVS(VCC)
wupend
1
µA
1. OUT1 – OUT9, ECDR ECV, ECFD floating.
2. TTest = -40 °C, 25 °C.
3. TTest = 85 °C. This parameter is guaranteed by design.
Doc ID 022637 Rev 2
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Electrical characteristics
8.2
L99MM70XP
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V VS 28 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
Table 10.
Symbol
fCLK
8.3
Oscillator
Parameter
Test condition
Oscillation frequency
Min.
Typ.
Max.
Unit
1.6
2.0
2.70
MHz
Power-on reset (VSREG)
All outputs open; Tamb = -40 °C...125 °C, unless otherwise specified (see Figure 3).
Table 11.
Symbol
VPOR
8.4
Power-on reset (VSREG)
Parameter
Test condition
VSREG increasing
VPOR threshold
Min.
Typ.
Max.
Unit
2.8
3.8
4.5
V
VSREG decreasing
3.2
V
Voltage regulator VCC
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V VSREG 28 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 12.
Symbol
Parameter
Test condition
VCC
Output voltage
VCC
Output voltage tolerance
active mode
ILOAD = 6 mA...50 mA,
VSREG = 13.5 V
Vhc
Output voltage tolerance
active mode, high current
ILOAD = 50 mA...100 mA,
VSREG = 13.5 V
VSTB
Output voltage tolerance
VCC-standby mode
ILOAD = 0 µA...6 mA,
VSREG = 13.5 V
VDP
Drop-out voltage
ICC
34/68
Voltage regulator VCC
Min. Typ. Max. Unit
5.0
-2.5
%
3.5
%
V
ILOAD = 100 mA, VSREG = 4.5 V
0.3
0.5
V
100
mA
950
mA
Current limitation
400
Cload1
Load capacitor1
Ceramic
0.22
Current consumption rising
threshold
±2.5
0.4
Short circuit output current
ICMPris
%
0.2
ICCmax
VCC deactivation time after
thermal shutdown
±2
ILOAD = 50 mA, VSREG = 4.5 V
Output current in active mode Max. continuous load current
tTSD
V
600
µF
1
Rising current (deactivated
current monitor)
Doc ID 022637 Rev 2
1.6
3.2
s
5.2
mA
L99MM70XP
Electrical characteristics
Table 12.
Voltage regulator VCC (continued)
Symbol
8.5
Parameter
ICMPfal
Current consumption falling
threshold
ICMPhys
Current consumption
hysteresis
VCCfail
VCC fail threshold
Test condition
Min. Typ. Max. Unit
Falling current (deactivated
current monitor)
1.3
VCC forced
2.7
mA
0.5
mA
2
V
Reset output (VCC supervision)
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4 V VS 28 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 13.
Reset output (VCC supervision)
Symbol
VRT1
VRT1HYST
VRT2
Parameter
Test condition
Min.
Typ. Max. Unit
VVCC increasing
CR1/Bit4 = 0(1)
4.6
4.7
4.85
V
VVCC decreasing
CR1/Bit4 = 0
4.5
4.6
4.7
V
Reset threshold voltage1
Threshold voltage 1
hysteresis
0.1
V
VVCC increasing
CR1/Bit4 = 1(1)
3.6
3.7
3.9
V
VVCC decreasing
CR1/Bit4 = 1
3.0
3.3
3.5
V
Reset threshold voltage2
Threshold voltage 2
hysteresis
0.4
VNRES
Reset Pin low output voltage VCC > 1 V, INRES = 1 mA
0.2
0.4
V
RNRES
Reset pull up int. resistor
VNRES = 4 V
110
204
k
Reset reaction time
CNRES = 100 pF,
INRES = 1 mA
40
µs
VRT2HYST
tRR
60
V
1. Delay time see tWDR below (Section 8.6: Watchdog).
8.6
Watchdog
4.5 V VS 28 V; Tamb = -40 °C...125 °C, unless otherwise specified, see Figure 10 and
Figure 11.
Table 14.
Symbol
tLW
tWDR
Watchdog
Parameter
Test condition
Min.
Typ.
Max.
Unit
Watchdog cycle time
100
134
180
ms
Watchdog reset pulse time
1.5
2.3
2.9
ms
Doc ID 022637 Rev 2
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Electrical characteristics
L99MM70XP
Figure 10. Watchdog timing
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8.7
Current monitor output CM
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 15.
Current monitor output CM
Symbol
ICM r
Parameter
Current monitor output ratio:
ICM/IOUT1,5,9 and 8 (low on-resistance)
Test condition
0 V VCM VCC - 1 V
ICM/IOUT2,3,4,6,7 and 8 (high onresistance)
36/68
Doc ID 022637 Rev 2
Min.
Typ.
—
1/10000
—
1/2000
Max.
Unit
L99MM70XP
Table 15.
Electrical characteristics
Current monitor output CM (continued)
Symbol
Parameter
Current monitor accuracy
accICMOUT1,5,9 and 8 (low on-res.)
ICM acc
Test condition
Min.
0 V VCM VCC - 1 V;
IOUTmin = 500 mA;
IOUT9max = 5.9 A;
IOUT1,5max = 2.9 A;
IOUT8max = 1.3 A
0 V VCM VCC - 1 V;
IOUT.min = 100 mA;
accICMOUT2,3,4,6,7 and 8 (high on-res.)
IOUT2,3,4,6,7max = 0.6 A;
IOUTXmax = 0.3 A
Typ.
Max.
4% + 1%
FS(1)
8% + 2%
FS(1)
Unit
—
—
1. FS(full scale) = IOUTmax * ICM r
8.8
Charge pump output CP
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 16.
Charge pump output CP
Symbol
Parameter
Test condition
VS = 8 V, ICP = -60 µA
VCP
Charge pump output voltage VS = 10 V, ICP = -80 µA
VS 12 V, ICP = -100 µA
ICP
Charge pump output current
VCP = VS + 10 V,
VS = 13.5 V
8.9
Outputs OUT1 – OUT9, ECV, ECFD
8.9.1
On-resistance
Min.
Max.
Unit
VS + 6
VS + 13
V
VS + 8
VS + 13
V
VS + 10
VS + 13
V
300
µA
95
Typ.
150
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 17.
Symbol
RON OUT1,5
On-resistance
Parameter
Test condition
On-resistance to supply or GND
RON OUT2,3,4 On-resistance to supply or GND
Typ.
Max.
Unit
VS = 13.5 V, Tamb = +25 °C
IOUT1,5 = ±1.5 A
300
400
m
VS = 13.5 V, Tamb = +125 °C
IOUT1,5 = ±1.5 A
450
600
m
VS = 13.5 V, Tamb = +25 °C
IOUT2,3,4 = ±0.4 A
1600
2200
m
VS = 13.5 V, Tamb = +125 °C
IOUT2,3,4 = ±0.4 A
2500
3400
m
Doc ID 022637 Rev 2
Min.
37/68
Electrical characteristics
Table 17.
On-resistance (continued)
Symbol
RON OUT6,7
L99MM70XP
Parameter
Test condition
On-resistance to supply
On-resistance to supply in low
resistance mode
RON OUT8
RON OUT9
IQLL
8.9.2
Typ.
Max.
Unit
VS = 13.5 V, Tamb = +25 °C
IOUT6,7 = -0.4 A
1600
2200
m
VS = 13.5 V, Tamb = +125 °C
IOUT6,7 = -0.4 A
2500
3400
m
VS = 13.5 V, Tamb = +25 °C
IOUT8 = -3.0 A
500
700
m
VS = 13.5 V, Tamb = +125 °C
IOUT8 = -3.0 A
700
950
m
1800
2400
m
2500
3400
m
VS = 13.5 V, Tamb = +25 °C
IOUT9 = -3.0 A
90
130
m
VS = 13.5 V, Tamb = +125 °C
IOUT9 = -3.0 A
130
180
m
VS = 13.5 V, Tamb = +25 °C
IOUTECV,ECFD = +0.4 A
1600
2200
m
VS = 13.5 V, Tamb = +125 °C
IOUTECV,ECFD = +0.4 A
2500
3400
m
VS = 13.5 V, Tamb = +25 °C
On-resistance to supply in high IOUT8 = -0.8 A
resistance mode
VS = 13.5 V, Tamb = +125 °C
IOUT8 = -0.8 A
On-resistance to supply
RON ECV,ECFD On-resistance to GND
IQLH
Min.
Switched-off output current
high-side drivers of OUT1-9
VOUT = 0 V, standby mode
Switched-off output current
low-side drivers of OUT1-5
VOUT = VS, standby mode
VOUT = VS, active mode
-10
Switched-off output current
low-side drivers of ECV
VOUT = VS, standby mode
-15
VOUT = VS, active mode
-10
Switched-off output current
low-side drivers of ECFD
VOUT = 4V, standby mode
VOUT = 0 V, active mode
VOUT = 4V, active mode
-5
-2
µA
-10.5
-7
µA
80
120
-7
µA
15
-7
µA
µA
80
-10
µA
120
-7
µA
µA
Switching times
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 18.
Symbol
38/68
Switching times
Parameter
Test condition
Min.
Typ. Max.
Unit
td ON H
Output delay time high-side
driver on
VS = 13.5 V,
corresponding low-side
driver is not active (1)(2)(3)
20
40
80
µs
td OFF H
Output delay time high-side
driver off
VS = 13.5 V (1)(2)(3)
45
150
300
µs
Doc ID 022637 Rev 2
L99MM70XP
Electrical characteristics
Table 18.
Switching times (continued)
Symbol
Parameter
Test condition
Min.
Typ. Max.
Unit
td ON L
Output delay time low-side
driver on
VS = 13.5 V,
corresponding low-side
driver is not active (1)(2)(3)
15
30
70
µs
td OFF L
Output delay time low-side
driver off
VS = 13.5 V (1)(2)(3)
80
150
300
µs
200
410
µs
0.2
0.6
V/µs
td HL
Cross current protection time
td LH
dVOUT/dt
tcc ONLS_OFFHS – td OFF H(4)
tcc ONHS_OFFLS – td OFF L(4)
VS = 13.5 V (1)(2)(3)
Slew rate of OUTx
0.1
1. Rload = 16 at OUT1,5 and OUT8 in low on-resistance mode.
2. Rload = 4 at OUT9.
3. Rload = 64 at OUT2,3,4,6,7, ECV, ECFD and OUT8 in high on-resistance mode.
4. tCC is the switch-on delay time if complement in half bridge has to switch off.
Figure 12. Output switching times
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Doc ID 022637 Rev 2
39/68
Electrical characteristics
8.9.3
L99MM70XP
Current monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 19.
Symbol
Current monitoring
Max.
Unit
3
5
A
0.75
1.25
A
VS = 13.5 V, source
0.75
1.25
A
Overcurrent threshold to supply in
low on-resistance mode
VS = 13.5 V, source
1.5
2.5
A
Overcurrent threshold to supply in
high on-resistance mode
VS = 13.5 V, source
0.35
0.65
A
|IOC9|
Overcurrent threshold to supply
VS = 13.5 V, source
6
10
A
|IOCECV|,
|IOCECFD|
Output current limitation to GND
VS = 13.5 V, sink
0.72
1.25
A
tFOC
Filter time of overcurrent signal
Duration of overcurrent
condition to set the status bit
100
µs
frec0
Recovery frequency for OC recovery
duty cycle bit = 0
1
4
kHz
frec1
Recovery frequency for OC recovery
duty cycle bit = 1
2
6
kHz
|IOC1|, |IOC5|
|IOC2|,
|IOC3|, |IOC4|
Parameter
Test condition
Overcurrent threshold to supply or
GND
|IOC6|, |IOC7| Overcurrent threshold to supply
|IOC8|
|IOLD1|,
|IOLD5|
|IOLD2|,
|IOLD3|,
|IOLD4|
|IOLD6|,
|IOLD7|
|IOLD9|
10
Typ.
55
9
30
80
mA
10
20
30
mA
10
20
30
mA
15
40
60
mA
Under-current threshold to supply in
high on-resistance mode
5
10
15
mA
Under-current threshold to supply
30
150
300
mA
Under-current threshold to supply or
VS = 13.5 V, sink and source
GND
Under-current threshold to supply
Under-current threshold to supply in
low on-resistance mode
|IOLD8|
VS = 13.5 V, sink and source
Min.
VS = 13.5 V, source
|IOLDECV|,
|IOLDECFD|
Under-current threshold to GND
VS = 13.5 V, sink
10
20
30
mA
tFOL
Filter time of under-current signal
Duration of under-current
condition to set the status bit
0.5
2.0
3.0
ms
40/68
Doc ID 022637 Rev 2
L99MM70XP
8.9.4
Electrical characteristics
Electrochrome control
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 20.
Electrochrome control
Symbol
Parameter
Test condition
ECVL = ‘1’
VCTRLmax
Maximum EC-control voltage
DNLECV
Differential non linearity
|dVECV|
Voltage deviation between
target and ECV
(1)
ECVL = ‘0’ (1)
dVECV = Vtarget(3) - VECV,
|IECDR| < 1 µA
Min.
Typ.
Max.
Unit
1.4
1.6
V
1.12
1.28
V
-1
1
LSB(2)
-5% 1LSB(2)
+5% +
1LSB(2)
mV
dVECV = Vtarget(3) - VECV
Toggle bit5 = 1 Status reg. 3
120
mV
dVECV = Vtarget(3) - VECV
Toggle bit4 = 1 Status reg. 3
-120
mV
dVECVhi
Difference voltage below it
between target
and ECV sets flag
above it
if VECV is
tFECVNR
ECVNR filter time
32
µs
ECVO filter time
32
µs
dVECVnr
tFECO
VECDRminHIGH
Output voltage range
VECDRmaxLOW
IECDR = -10 µA
4.1
5.5
V
IECDR = 10 µA
0
0.7
V
> VECV + 500 mV,
VECDR = 3.5 V
-100
-10
µA
Vtarget(3) < VECV - 500 mV,
VECDR = 1.0 V; Vtarget = 0 V,
VECV = 0.5 V
10
100
µA
10
k
-1
1
LSB(2)
-5% 1LSB(2)
+5% +
1LSB(2)
mV
Vtarget(3)
IECDR
Recdrdis
Current into ECDR
Pull down resistance at ECDR
VECDR = 0.7 V, ECON = ‘1’,
in fast discharge mode and
EC = 0 or ECON = ‘0’
while EC-mode is off
DNLECFD
Differential non linearity
|dVECFD|
Voltage deviation between
target and ECFD
dVECFDnr(4)
dVECFDhi
Difference voltage below it
between target
and ECFD sets
above it
flag if VECFD is
dVECFD = Vtarget(3) - VECFD,
IECFD = 100 µA
dVECFD = Vtarget(3) - VECFD
toggle status bit ECVNR = ’1’
120
mV
dVECFD = Vtarget(3) - VECFD
toggle status bit ECVO = ‘1’
-120
mV
1. Bit ECVL = ‘1’ or ‘0’: ECV voltage, where IECDR can change sign.
2. 1 LSB (Least Significant Bit) = 23.8 mV.
3. Vtarget is set by bits EC and bit ECVL; tested for each individual bit.
4. Not tested since pulling pin ECFD to a low voltage against the internal source follower may lead to an overcurrent at pin
ECFDHS or thermal shutdown.
Doc ID 022637 Rev 2
41/68
Electrical characteristics
L99MM70XP
Figure 13. Electrochrome mirror driver with mirror referenced to ground
96
287
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42/68
Doc ID 022637 Rev 2
L99MM70XP
8.9.5
Electrical characteristics
INH/PWM3 input
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 8 V VS 16 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 21.
INH/PWM3 input
Symbol
8.10
Parameter
Test condition
IINHth
Wake-up activate threshold
current
IINHPd
INH pull down current
IINHhys
Wake-up current hysteresis
tWU
Minimum time for wake-up
Min.
Typ.
Max.
Unit
30
75
120
µA
30
70
120
µA
10
20
µA
64
77
µs
VINH = 13.5 V
50
LIN
Compatible to LIN 2.1 for baud rates up to 20 kBit/s
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 7 V VS 18 V; Tamb = -40 °C...125 °C, unless otherwise specified.
Table 22.
Symbol
LIN
Parameter
Test condition
Min.
Typ.
Max.
Unit
0.3 VCC
V
LIN transmit data input: pin TXD
VTXDLOW
Input voltage
dominant level
Active mode
VTXDHIGH
Input voltage
recessive level
Active mode
0.7 VCC
V
VTXDHYS
VTXDHIGH - VTXDLOW
Active mode
500
mV
RTXDPU
TXD pull up resistor
Active mode, VS = 13.5 V,
0 < VCSN < 0.7 VCC
50
100
150
k
0.3 VCC
V
LIN receive data output: pin RXD
VRXDLOW
Output voltage
dominant level
Active mode, IRXD = 2 mA
VRXDHIGH
Output voltage
recessive level
Active mode, IRXD = 2 mA
0.7 VCC
V
LIN transmitter and receiver: pin LIN
VTHdom
Receiver threshold
voltage recessive to
dominant state
0.4 VS
0.45 VS
0.5 VS
V
VTHrec
Receiver threshold
voltage dominant to
recessive state
0.5 VS
0.55 VS
0.6 VS
V
Doc ID 022637 Rev 2
43/68
Electrical characteristics
Table 22.
Symbol
L99MM70XP
LIN (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTHhys
Receiver threshold
hysteresis:
VTHrec - VTHdom
0.07 VS
0.1 VS
0.175 VS
V
VTHcnt
Receiver tolerance
center value:
(VTHrec + VTHdom) / 2
0.475 VS
0.5 VS
0.525 VS
V
VTHwkup
Receiver wake-up
rising threshold
voltage
1.0
1.5
2
V
VTHwkdwn
Receiver wake-up
falling threshold
voltage
VS - 3.5
VS - 2.5
VS - 1.5
V
tLINBUS
Dominant time for
wake-up via bus
Sleep mode edge: recessivedominant
IBUS_LIM
Current limitation in
dominant state
VTXD = 0 V, VLIN = VSMAX = 18 V
40
Input leakage current
IBUS_PAS_dom at the receiver (incl.
pull up resistor)
VTXD = 5 V, VLIN = 0 V, VS = 13.5 V
-1
Transmitter input
IBUS_PAS_rec current in recessive
state
VTXD = 5 V, 8 V VLIN, VS 18 V,
VLIN VS
64*TOSC
100
µs
180
mA
mA
20
µA
1
mA
Input current if loss of
VS = GND, 0 V < VLIN < 18 V
VBAT at Device
100
µA
VLINdom
LIN voltage level in
dominant state
Active mode; VTXD = 0 V;
ILIN = 40 mA
1.3
V
VLINrec
LIN voltage level in
recessive state
Active mode; VTXD = 5 V; ILIN = 10 µA
VS
V
RLINup
LIN output pull up
resistor
VTXD = 5 V; VLIN = 0 V
60
k
6
µs
2
µs
Transceiver input
GND = VS, 0 V < VLIN < 18 V,
IBUS_NO_GND current if loss of GND
VS = 13.5 V
at device
IBUS_NO_BAT
-1
0.8 VS
20
40
LIN transceiver timing
tRXDpd
Receiver propagation
delay time
Active Mode;
tRXDpd = max(tRXDpdr, tRXDpdf);
tRXpdf = t(0.5 VRXD) - t(0.45 VLIN)
tRXpdr = t(0.5 VRXD) - t(0.55 VLIN)
VS = 13.5 V; CRXD = 20 pF;
RBUS = 1 k, CBUS = 1 nF;
tRXDpd_sym
Symmetry of receiver
propagation delay
time (rising vs. falling
edge)
tRXDpd_sym = tRXDpdr - tRXDpdf
44/68
Doc ID 022637 Rev 2
-2
L99MM70XP
Table 22.
Electrical characteristics
LIN (continued)
Symbol
D1
D2
D3
D4
Parameter
Test condition
Duty cycle 1
THRec(max) = 0.744 * VS;
THDom(max) = 0.581 * VS;
VS = 7 to 18 V, tbit = 50 µs;
D1 = tBUS_rec(min) / (2 * tbit);
RBUS = 1 k, CBUS = 1 nF;
RBUS = 660 , CBUS = 6.8 nF;
RBUS = 500 , CBUS = 10 nF
Duty cycle 2
THRec(min) = 0.422*VS;
THDom(min) = 0.284*VS;
VS = 7.6 to 18 V, tbit = 50 µs;
D2 = tBUS_rec(max)/(2*tbit);
RBUS = 1 k, CBUS = 1 nF;
RBUS = 660 , CBUS = 6.8 nF;
RBUS = 500 , CBUS = 10 nF
Duty cycle 3
THRec(max) = 0.778*VS;
THDom(max) = 0.616*VS;
VS = 7 to 18V, tbit = 96µs,
D3 = tBUS_rec(min)/(2*tbit)
RBUS = 1 k, CBUS = 1 nF;
RBUS = 660 , CBUS = 6.8 nF;
RBUS = 500 , CBUS = 10 nF
Duty cycle 4
THRec(min) = 0.389*VS;
THDom(min) = 0.251*VS;
VS = 7.6 to 18V, tbit = 96µs;
D4 = tBUS_rec(max)/(2*tbit)
RBUS = 1 k, CBUS = 1 nF;
RBUS = 660 , CBUS = 6.8 nF;
RBUS = 500 , CBUS = 10 nF
Min.
Typ.
Max.
Unit
0.396
0.581
0.417
0.590
tdom(TXD)
TXD dominant timeout
12
ms
tdom(LIN)
BUS dominant timeout
12
ms
trec(LIN)
BUS recessive timeout
40
µs
13
V/µs
LIN Flash mode
SRFLASH
LIN slew rate falling
edge in Flash mode
Active mode; LIN slew rate (80% to
20% VS); VS = 13.5 V,
RBUS = 150 , CBUS = 1 nF
Doc ID 022637 Rev 2
45/68
Electrical characteristics
L99MM70XP
Figure 15. LIN transmit and receive timing
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8.11
SPI and PWM inputs
8.11.1
DC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V VS 18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
Table 23.
DC characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
0.3 VCC
V
Inputs: CSN, CLK, DI, PWM1, PWM2, PWM3
VIL
Input voltage low-level
VS = 13.5 V
VIH
Input voltage high-level
VS = 13.5 V
0.7 VCC
V
Input hysteresis
VS = 13.5 V
500
mV
RCSN in
CSN pull up resistor
VS = 13.5 V, 0 < VCSN < 0.7 VCC
30
120
250
k
RCLK in
CLK pull down resistor
VS = 13.5 V, VCLK = 1.5 V
30
60
150
k
DI pull down resistor
VS = 13.5 V, VDI = 1.5 V
30
60
150
k
RPWM1 in
PWM1 pull down resistor
VS = 13.5 V, VPWM1 = 1.5 V
30
60
150
k
RPWM2 in
PWM2 pull down resistor
VS = 13.5 V, VPWM2 = 1.5 V
30
60
150
k
0.3 VCC
V
VIHYS
RDI in
PWM3
See Section 8.9.5: INH/PWM3 input
Output: DO
46/68
VOL
Output voltage low-level
IOL = 5 mA, VS = 13.5 V
VOH
Output voltage high-level
IOH = -5mA, VS = 13.5 V
Doc ID 022637 Rev 2
0.7 VCC
V
L99MM70XP
8.11.2
Electrical characteristics
AC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V VS 18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
Table 24.
Symbol
COUT
AC characteristics
Parameter
(1)
CIN(1)
Test condition
Min.
Typ.
Max.
Unit
Output capacitance (DO)
—
—
10
pF
Input capacitance (DI, CSN,
CLK, PWM1, PWM2, PWM3)
—
—
10
pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
8.11.3
Dynamic characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V VS 18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
For definition of the parameters please see Figure 16 and Figure 17.
Table 25.
Symbol
Dynamic characteristics
Parameter
Test condition
Min. Typ. Max. Unit
tCSNQVL
DO enable from 3-state to
low-level
CDO = 100 pF, IDO = 1 mA, pull
up load to VCC, VS = 13.5 V
100
250
ns
tCSNQVH
DO enable from 3-state to
high-level
CDO = 100 pF, IDO = -1 mA, pull
down load to GND, VS = 13.5 V
100
250
ns
tCSNQTL
DO disable from low-level to
3-state
CDO = 100 pF, IDO = 4 mA, pull
up load to VCC, VS = 13.5 V
380
450
ns
tCSNQTH
DO disable from high-level to CDO = 100 pF, IDO = -4 mA, pull
down load to GND, VS = 13.5 V
3-state
380
450
ns
tCLKQV CLK falling until DO valid
tSCSN
tSDI
tHDI
VDO < 0.3 VCC or VDO > 0.7 VCC
CDO = 5 pF, VS = 13.5 V
ns
VDO < 0.3 VCC or VDO > 0.7 VCC
CDO = 100 pF, VS = 13.5 V
CSN setup time, CSN low
VS = 13.5 V
before rising edge of CLK
DI setup time, DI stable before
VS = 13.5 V
rising edge of CLK
DI hold time, DI stable after
VS = 13.5 V
rising edge of CLK
50
250
ns
400
ns
200
ns
200
ns
tHCLK
minimum CLK high time
VS = 13.5 V
115
ns
tLCLK
minimum CLK low time
VS = 13.5 V
115
ns
tHCSN
minimum CSN high time
VS = 13.5 V
4
µs
tSCLK
CLK setup time before CSN
rising
VS = 13.5 V
400
ns
Doc ID 022637 Rev 2
47/68
Electrical characteristics
Table 25.
Symbol
L99MM70XP
Dynamic characteristics (continued)
Parameter
Test condition
Min. Typ. Max. Unit
tr DO
DO rise time
CDO = 100 pF, VS = 13.5 V
80
140
ns
tf DO
DO fall time
CDO = 100 pF, VS = 13.5 V
50
100
ns
VS = 13.5 V
100
ns
VS = 13.5 V
100
ns
tr in
tf in
rise time of input signal DI,
CLK, CSN
fall time of input signal DI,
CLK, CSN
Figure 16. SPI timing parameters
W+&61
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W &6149
W &6147
'DWDRXW
'DWDRXW
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W &/.49
W6&61
W6&/.
&/.
W6',
',
W+&/.
W/&/.
'DWDLQ
'DWDLQ
*$3*06
48/68
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L99MM70XP
Electrical characteristics
Figure 17. SPI input and output timing parameters
WU'2
9&&
'2
ORZWRKLJK
9&&
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9&&
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Figure 18. SPI maximum clock frequency
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W 6&.ULVH
W 6&.49
6&.
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0DVWHU
6ODYH
0,62
WVHWXS
*$3*06
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Electrical characteristics
L99MM70XP
The maximum SPI clock frequency can be calculated as follows (see Figure 18):
tCLKQV(total) = tCLKrise(µC) + tCLKfilt(PCB) + tCLKQV(slave) + tsetup(µC)
fCLK(max) < ½ x tCLKQV(total)
Example:
tCLKQV = 25 ns + 100 ns + 250 ns + 25 ns = 400 ns
fCLK(max) < 1.25 MHz
8.12
Input PWM2 for Flash mode
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V VS 18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
Table 26.
Symbol
Input PWM2 for Flash mode
Parameter
Test condition
Typ.
Max.
Unit
VflashL
Input low-level (PWM2
falling)(1)
VS = 13.5 V
6.1
7.25
8.4
V
VflashH
Input high-level (PWM2
rising)
VS = 13.5 V, VBAT-standby
mode, VCC switches on
7.4
8.4
9.4
V
0.6
0.8
1.0
V
VflashHYS Input voltage hysteresis(1) VS = 13.5 V
1. Parameter guaranteed by design.
50/68
Min.
Doc ID 022637 Rev 2
L99MM70XP
SPI control and status registers
9
SPI control and status registers
9.1
Functional description of the SPI
For a general description of the SPI please refer to chapter Serial peripheral interface (ST
SPI standard).
9.1.1
SPI communication flow
At the beginning of each communication the master can read the contents of the register (ROM address 3Eh) of the slave device. This 8 bit register indicates the
SPI frame length (24 bit) and the availability of additional features.
Each communication frame consists of a command byte which is followed by 2 data bytes.
The data returned on DO within the same frame always starts with the . It provides general status information about the device. It is followed by 2 data bytes
(i.e. “in-frame-response”).
For write cycles the is followed by the previous content of the
addressed register.
9.1.2
Command byte
Table 27.
Command byte
Command byte
Bit
23
22
Name OC1 OC0
Data byte 1
21
20
19
18
17
16
A5
A4
A3
A2
A1
A0
15
14
13
12
11
Data byte 2
10
D15 D14 D13 D12 D11 D10
9
8
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OCx: operation code
Ax: address
Dx: data bit
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (, , , ) and a 6 bit address. If less than 6 bits are required, the remaining bits are
unused but are reserved.
9.1.3
Operation code definition
Table 28.
Operation code definition
OC1
OC0
Meaning
0
0
0
1
1
1
0
1
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SPI control and status registers
L99MM70XP
The and operations allow access to the RAM of the device.
A operation is used to read a status register and subsequently
clear its content.
The allows access to the ROM area which contains device
related information such as , , and .
9.1.4
Global status byte
Table 29.
Global status byte
Global status byte
Bit
7
6
5
4
3
2
1
0
Name
GL_ER
CO_ER
NRECE
TSD
TW_OL
UV_OV_OC
VCC_FAIL
PASSIVE
Reset
1
0
0
0
0
0
0
0
GL_ER
Global error flag.
Failures of Bits 0-6 are always linked to the global error flag. This flag is generated by an OR
combination of all failure events of the device. If the TW_OL_MSK bit is set in the configuration
register, TW_OL is not used as an input to this bit.
GL_ER is reflected via the DO pin while CSN is held low and no clock signal is available. The flag
remains as long as CSN is low. This operation does not cause the communication error bit in the
to be set.
CO_ER
Communication error.
If the number of clock pulses within the previous frame is not 24, the frame is ignored, and this bit
is set.
CO_ER is not set, if CSN is held low without any clock to check the GL_ER bit.
Chip reset (C_RESET) = Registers have been set to default.
After power on NRECE is ‘0’ and is set to ‘1’ by a valid SPI communication.
NRECE = NOT
(C_RESET OR NRECE is also ‘0’ if there was a communication error or if there was a reset due to stuck-at-0 or
stuck-at-1 at the SPIDI input.
CO_ER)
When NRECE is active (‘0’), the gate drivers are switched off (resistive path to source). The gate
drivers can only be activated after NRECE has been reset with an SPI command.
TSD
TW_OL
UV_OV_OC
Thermal shut down due to an internal sensor. All the gate drivers and the charge pump are
switched off (resistive path to source). The TSD bit has to be cleared through a software reset to
reactivate the gate drivers and the charge pump.
Thermal warning OR open-load.
Under voltage OR overvoltage OR overcurrent
VCC_FAIL
VCC fail
PASSIVE
Device in passive mode.
This bit is set if the device enters passive mode (due to watchdog failure, VCC under voltage,
thermal shutdown TSD2 or SPI data in stuck at 0 or 1)
The bit is reset when the micro sends the first correct SPI frame after entering passive mode.
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L99MM70XP
9.1.5
SPI control and status registers
Address mapping
Table 30.
RAM memory map
Address
Name
Access
01h
Control register 1
Read/write
Bridge control, watchdog trigger
02h
Control register 2
Read/write
High/low-side control, EC control
03h
Control register 3
Read/write
Bridge recovery mode, bridge PWM mode, LIN
04h
Control register 4
Read/write
HS recovery and PWM mode, LS recovery and PWM
mode, current monitor
11h
Status register 1
Read/clear
Overcurrent diagnosis
12h
Status register 2
Read/clear
Open-load diagnosis
13h
Status register 3
Read/clear
WD status, supply voltage and EC diagnosis,
14h
Status register 4
Read/clear
LIN diagnosis, thermal status
3Fh
Configuration
register
Read/write
Table 31.
Content
ROM memory map
Address
Name
Access
Content
00h
ID Header
Read only
4300h (ASSP ST_SPI)
01h
Version
Read only
0000h (engineering sample)
02h
Product code 1
Read only
4800h (dec. 72)
03h
Product code 2
Read only
4800h (ASCII ‘H’)
3Eh
SPI frame ID
Read only
4200h (watchdog available, 24 bit ST-SPI)
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SPI control and status registers
9.1.6
Control registers
Table 32.
Control registers 1
L99MM70XP
Control register 1 (01h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset state
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
NINT
EN
RST
LEV
ICMP
Stby
Sel
Go
Stby
WD
Trig
Name
Table 33.
OUT5 OUT5 OUT4 OUT4 OUT3 OUT3 OUT2 OUT2 OUT1 OUT1
HS
LS
HS
LS
HS
LS
HS
LS
HS
LS
Control registers 1, bits
Bit name
Comment
OUT5HS
OUT5LS
OUT4HS
OUT4LS
OUT3HS
OUT3LS
OUT2HS
If a bit is set, the selected output driver is switched on. If the corresponding PWM enable bit is set
also, the driver is activated only if the associated PWM input signal is high.
The outputs of OUT1 – OUT5 are half bridges. If the bits of the HS and LS drivers of the same half
bridge are set, both drivers are deactivated and the output is set to high impedance.
OUT2LS
OUT1HS
OUT1LS
NINTEN
Enable NINT output
0: RXD output has only RXD functionality
1: RXD output can work also as NINT output
RSTLEV
Select VCC reset level
0: 4.7 V
1: 3.5 V
ICMP
Monitor the ICC current consumption during VCC-standby mode
0: watchdog disabled only if ICC < ICMP
1: watchdog disabled
STBYSEL
Standby select
0: VBAT-standby
1: VCC-standby
This bit is a one-shot bit, it is read always 0
GOSTBY
1: execute standby mode
This bit is a one-shot bit, it is read always 0
WDTRIG
Watchdog trigger
This bit has to be toggled regularly if the watchdog is active. The watchdog can be triggered either by
this bit or by bit 0 of the configuration register.
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L99MM70XP
Table 34.
SPI control and status registers
Control registers 2
Control register 2 (02h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EC4
EC3
EC2
EC1
Name
reserved ECFDLS ECVLS OUT9 OUT8HS2 OUT8HS1 OUT7 OUT6 ECND EC5
Table 35.
Control registers 2, bits
Bit name
Comment
reserved
Reserved bit, has always to be written to 0 and reads always 0
ECFDLS
1: switch on the ECFD LS driver
0: switch off the ECFD LS driver
ECVLS
OUT9
OUT8HS2
OUT8HS1
EC0 ECON
1: switch on the ECV LS driver
0: switch off the ECV LS driver
If the ECVPWM1 bit (CR4/Bit4) is also set, then the ECV output is controlled by the PWM1 input
1: switch on the OUT9 HS driver
0: switch off the OUT9 HS driver
If the OUT9PWM1 bit (CR4/Bit11) is also set, then the OUT9 output is controlled by the PWM1 input
11: switch off the OUT8 HS driver
10: switch on the OUT8 HS driver (high current mode)
01: switch on the OUT8 HS driver (low current mode)
00: switch off the OUT8 HS driver
If the OUT8PWM3 bit (CR4/Bit10) is also set, then the OUT8 output is controlled by the PWM3 input
OUT7
1: switch on the OUT7 HS driver
0: switch off the OUT7 HS driver
If the OUT7PWM1 bit (CR4/Bit9) is also set, then the OUT7 output is controlled by the PWM1 input
This bit is disabled if ECON = 1. In this case OUT7 is switched on permanently.
OUT6
1: switch on the OUT6 HS driver
0: switch off the OUT6 HS driver
If the OUT6PWM2 bit (CR4/Bit8) is also set, then the OUT6 output is controlled by the PWM2 input
ECND
EC negative discharge:
0: EC negative discharge off
1: EC negative discharge on
EC5
EC4
EC3
EC2
Reference value for difference voltage amplifier at pin ECV, binary coded. The full scale value is set in
ECVL (CR3/Bit5). If all EC bits are set to zero, the reference value is 0V.
EC1
EC0
ECON
1: EC control enabled
0: EC control disabled
If the EC control is enabled, the output OUT7 is switched on permanently.
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SPI control and status registers
Table 36.
L99MM70XP
Control register 3
Control register 3 (03h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset state
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Name
reserved
Table 37.
LIN
OCR
OUT5 OUT4 OUT3 OUT2 OUT1 LIN
OUT5 OUT4 OUT3 OUT2 OUT1
OVUVR
TXD ECVL
Freq
OR
OR
OR
OR
OR
Flash
PWM1 PWM1 PWM1 PWM1 PWM1
Tout
Control register 3, bits
Bit name
reserved
OCRFREQ
OVUVR
Comment
Reserved bit, has always to be written to 0 and reads always 0
OCR frequency:
This bit defines the overcurrent recovery frequency of a driver in overcurrent recovery mode
0: 1.7 kHz
1: 3 kHz
Overvoltage/undervoltage recovery:
1: clear status register to enable the outputs after an overvoltage/undervoltage event
0: outputs are enabled automatically after an overvoltage/undervoltage event
OUT5OR
OUT4OR
OUT3OR
OUT2OR
Overcurrent recovery enable:
1: the output is automatically reactivated after a delay time with programmable duty cycle
(CR3/Bit14)
0: clear status register to enable the output after an overcurrent event
OUT1OR
LINFLASH
LINTXDTout
ECVL
LIN flash mode:
0: 20 kbit/s
1: 100 kbit/s
Dominant TxD time-out for the LIN interface:
1: enable the dominant TXD time-out for the LIN interface
0: disable the dominant TXD time-out for the LIN interface
EC voltage limit:
0: max EC voltage = 1.2V
1: max EC voltage = 1.5V
OUT5PWM1
OUT4PWM1
OUT3PWM1
If the PWM enable bit is set and the output is enabled, the output is switched on only if the PWM1
input is high, and switched off if the PWM1 input is low.
OUT2PWM1
OUT1PWM1
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L99MM70XP
Table 38.
SPI control and status registers
Control register 4
Control register 4 (04h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ECV
OR
reserved
ECV
PWM1
CM3
CM2
CM1
CM0
Name
OUT9 OUT8 OUT7 OUT6 OUT9 OUT8 OUT7 OUT6
reserved
OR
OR
OR
OR PWM1 PWM3 PWM1 PWM2
Table 39.
Bit name
Control register 4, bits
Comment
OUT9OR
OUT8OR
OUT7OR
Overcurrent recovery enable:
1: the output is automatically reactivated after a delay time with programmable duty cycle
(CR3/Bit14)
0: clear status register to enable the output after an overcurrent event
OUT6OR
OUT9PWM1
OUT8PWM3 If the PWM1/2/3 enable bit is set and the output is enabled, the output is switched on only if the
PWM1/2/3 input is high, and switched off if the PWM1/2/3 input is low.
OUT7PWM1 OUT8 is controlled by PWM3, OUT7 is controlled by PWM1 and OUT6 is controlled by PWM2.
OUT6PWM2
reserved
Reserved bit, has always to be written to 0 and reads always 0
ECVOR
Overcurrent recovery enable:
1: the output is automatically reactivated after a delay time with programmable duty cycle
(CR3/Bit14)
0: clear status register to enable the output after an overcurrent event
reserved
Reserved bit, has always to be written to 0 and reads always 0
ECVPWM1
If the PWM1 enable bit is set and the output is enabled, the output is switched on only if the PWM1
input is high, and switched off if the PWM1 input is low.
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SPI control and status registers
Table 39.
L99MM70XP
Control register 4, bits (continued)
Bit name
Comment
Current monitor:
the current image of the selected high-side output is multiplexed to the CM output (see table below).
CM3
CM2
CM1
CM0
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CM3
CM2
CM1
CM0
Current image of
0
0
0
0
CM deactivated
0
0
0
1
CM HS1 active
0
0
1
0
CM HS2 active
0
0
1
1
CM HS3 active
0
1
0
0
CM HS4 active
0
1
0
1
CM HS5 active
0
1
1
0
CM HS6 active
0
1
1
1
CM HS7 active
1
0
0
0
CM HS8 active
1
0
0
1
CM HS9 active
1
0
1
0
reserved
1
0
1
1
reserved
1
1
0
0
reserved
1
1
0
1
reserved
1
1
1
0
reserved
1
1
1
1
reserved
Doc ID 022637 Rev 2
L99MM70XP
Table 40.
SPI control and status registers
Configuration register
Configuration register (3Fh)
Bit
7
6
5
4
3
2
1
0
Reset state
0
0
0
0
0
0
0
0
ECV
ECFD
OUT7
OLMASK
OUT1HS
OLMASK
OUT1LS
OLMASK
TW_OL
MASK
Name
Table 41.
Bit name
WD
TRIG
Configuration register, bits
Comment
The bits 15 to 8 of the configuration register have to be written to 0, and read always 0
ECV
ECFD
OUT7
OLMASK
Mask the ECV, ECFD (HS and LS) and OUT7 open-load diagnostics bits (status reg. 2, bits 11, 14,
15):
an open-load event is not considered in the open-load bit (TW_OL) of the global status register
OUT1HS
OLMASK
Mask the OUTHS1 open-load diagnostic bit (status reg. 1/bit 1):
an open-load event (under-current status bit of OUT1HS) is not considered in open-load bit (TW_OL)
of the global status register.
OUT1LS
OLMASK
Mask the OUTLS1 open-load diagnostic bit (status reg. 1/bit 0):
an open-load event (under-current status bit of OUT1LS) is not considered in open-load bit (TW_OL)
of the global status register.
TW_OL
MASK
WDTRIG
Mask the TW_OL bit in global status byte:
a temperature warning or open-load event is not considered in the “global error flag”
Trigger the watchdog.
This bit has to be toggled regularly if the watchdog is active. The watchdog can be triggered either by
this bit or by bit 0 of the Control Register 1.
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SPI control and status registers
9.1.7
Status registers
Table 42.
Status register 1
L99MM70XP
Status register 1 (11h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
ECFDLS
ECV
LS
OUT
9HS
OUT
8HS
OUT
7HS
OUT
6HS
OUT5
HS
Table 43.
Bit name
OUT5 OUT4 OUT4 OUT3 OUT3 OUT2 OUT2 OUT1 OUT1
LS
HS
LS
HS
LS
HC
LS
HS
LS
Status register 1, bits
Comment
ECFDLSOC
ECVLSOC
OUT9HSOC
OUT8HSOC
OUT7HSOC
OUT6HSOC
OUT5HSOC
OUT5LSOC
OUT4HSOC
OUT4LSOC
Overcurrent diagnosis:
In case of an overcurrent event the corresponding status bit is set and the output driver is disabled.
If the overcurrent recovery enable bit is set, the output is automatically reactivated after a delay time
resulting in a PWM modulated current with a programmable duty cycle.
If the overcurrent recovery bit is not set, the microcontroller has to clear the overcurrent bit to
reactivate the output driver.
OUT3HSOC
OUT3LSOC
OUT2HSOC
OUT2LSOC
OUT1HSOC
OUT1LSOC
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L99MM70XP
Table 44.
SPI control and status registers
Status register 2
Status register 2 (12h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
ECFD
LS
ECV
LS
Table 45.
Bit name
OUT9 OUT8 OUT7 OUT6
OUT5 OUT5 OUT4 OUT4 OUT3 OUT3 OUT2 OUT2 OUT1 OUT1
HS
LS
HS
LS
HS
LS
HS
LS
HS
LS
Status register 2, bits
Comment
ECFDLSOL
ECVLSOL
OUT9OL
OUT8OL
OUT7OL
OUT6OL
OUT5HSOL
OUT5LSOL
OUT4HSOL
OUT4LSOL
The open-load detection monitors the load current in each activated output stage. If the load current
is below the under current detection threshold for at least tdOL = 2ms, the corresponding open-load
bit is set. Due to the mechanical / electrical inertia of typical loads a short activation of the outputs
(e.g. 3 ms) can be used to test the open-load status without changing the mechanical / electrical
state of the loads.
The open-load detection of OUT1 HS and OUT1 LS can be masked by the configuration register
(Bit 4/5).
The open-load detection of ECFDLS, ECVLS and OUT7 can be masked by the configuration
register (Bit 6).
OUT3HSOL
OUT3LSOL
OUT2HSOL
OUT2LSOL
OUT1HSOL
OUT1LSOL
Maskable by the configuration register:
an open-load event is not considered in open-load bit (TW_OL) of global status register.
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SPI control and status registers
Table 46.
L99MM70XP
Status register 3
Status register 3 (13h)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
LIN
perm
dom
LIN
TXD
dom
LIN
prem
rec
VCC
fail
UV
OV
WD
timer
state
WD
timer
state
ECFD
HSOC
ECFD
HSOL
ECV
NR
ECVO
TSD2
TSD1
TW
Table 47.
Status register 3, bits
Bit name
Comment
LIN perm dom
If the bus state is dominant (low) for more than 12 ms a permanent dominant status is detected.
The status bit is set.
LIN TXD dom
If TXD is in dominant state (low) for more than 12 ms, the transmitter is disabled and this bit is set.
LIN perm rec
If TXD changes to dominant (low) state but RXD signal does not follow within 40 µs, the
transmitter is disabled and this bit is set.
VCCFail
VCCFail:
VCC < 2 V for more than 2 µs
UV
VS undervoltage detected
OV
VS overvoltage detected
WDTIM1
WDTIM0
If an over/under voltage event is detected, the outputs are
disabled and one of these bits is set.
If the OVUVR bit is 0, the outputs are enabled automatically after
an over/under voltage event and the UV/OV bit is reset.
If the OVUVR bit is 1, the outputs are enabled after clearing the
UV/OV bit by SPI command (read and clear operation)
Watchdog state:
Display which part of the total WD time (100 ms) has been elapsed:
WDTIM1
WDTIM0
Elapsed time
0
0
< 1/3 of the total WD time
0
1
< 2/3 of the total WD time
1
1
< 3/3 of the total WD time
ECFDHSOC
Overcurrent diagnosis:
In case of an overcurrent event on ECFDHS the status bit is set and the output driver is disabled.
ECFDHSOL
The open-load detection monitors the load current in the ECFDHS. If the load current is below the
under current detection threshold for at least tdOL = 2 ms, the open-load bit is set.
ECVNR
ECV voltage not reached
Two comparators monitor the voltage at pin ECV in electrochrome
mode. If this voltage is below / above the programmed target,
these bits signal the difference after at least 32 µs. The bits are
not latched and may toggle after at least 32 µs, if the ECV voltage
has not yet reached the target.
ECVO
ECV voltage too high
TSD2
Thermal shutdown 2 (> 160 °C)
TSD1
Thermal shutdown 1 (> 150 °C)
TW
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Thermal warning (> 140 °C)
Doc ID 022637 Rev 2
L99MM70XP
SPI control and status registers
All bits except the WDTIM1, WDTIM0, ECVNR and ECVO bits can be reset by a read and
clear operation on SR4.
Table 48.
Status register 4
Status register 4 (14h)
Bit
15
14
13
12
Reset state
0
0
0
0
Name
WD
fail
WD
fail
WD
fail
WD
fail
Table 49.
11
10
0
0
9
Forced
Forced
SleepWD SleepTSD
8
7
0
0
0
Dev
State
Dev
State
6
5
4
3
2
1
0
0
0
0
1
0
0
0
VCC
VCC
VCC NOT SPI
LIN
INH
Restart Restart Restart RDY Wake Wake Wake
Status register 4, bits
Bit name
Comment
WDFAIL3
These bits are not clearable, are
cleared with a proper watchdog trigger
or if the chip is sent to VBAT-standby by
the watchdog.
WDFAIL2
Nr of watchdog fails
WDFAIL1
WDFAIL0
Forced sleep This bit is set if the chip has been set to VBAT-standby mode
by the watchdog
WD
These bits are latched until a “read and
Forced sleep This bit is set if the chip has been set to V
mode clear” access on SR4.
BAT-standby
TSD
DEVSTATE1
by a thermal shutdown
Signal device state:
DEV
DEV
STATE1 STATE2
DEVSTATE0
State
0
0
Active
0
1
VCC-standby
1
0
VBAT standby or POR
1
1
Flash
These bits are latched until a “read and
clear” access on SR 4.
The device state is updated with any state transition and
with a read and clear command on status register 4.
Therefore, the first read operation after entering active
mode or flash mode reads the last device state. Read
operations after a read and clear operation reads the
current device state. After power-on reset, the device
state is VBAT-standby.
VCCRestart2
These bits are latched until a “read and
clear access” on SR 4.
VCCRestart1 Nr of TSD restart trials
VCCRestart0
NOTRDY
Not ready: This bit is set for 200µs after switching from
standby to active mode. It is cleared automatically. While
the bit is set, the output drivers are disabled.
Doc ID 022637 Rev 2
This bit is not clearable, it is cleared
automatically.
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SPI control and status registers
Table 49.
Bit name
L99MM70XP
Status register 4, bits (continued)
Comment
SPIWake
Indicates wake-up from VCC-standby mode via SPI
LINWake
Indicates wake-up from VCC-standby mode via LIN
INHWake
Indicates wake-up from VCC-standby mode via INH
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Doc ID 022637 Rev 2
These bits are latched until a “read and
clear” access on SR4.
L99MM70XP
Package and packaging information
10
Package and packaging information
10.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10.2
PowerSSO-36 package information
Figure 19. PowerSSO-36 package dimensions
AG00066V1
Doc ID 022637 Rev 2
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Package and packaging information
Table 50.
L99MM70XP
PowerSSO-36 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
2.15
-
2.45
A2
2.15
-
2.35
a1
0
-
0.10
b
0.18
-
0.36
c
0.23
-
0.32
1
10.10
-
10.50
1
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
-
2.3
-
G
-
-
0.1
G1
-
-
0.06
H
10.1
-
10.5
h
-
-
0.4
k
0°
-
8°
L
0.55
-
0.85
M
-
4.3
-
N
-
-
10°
O
-
1.2
-
Q
-
0.8
-
S
-
2.9
-
T
-
3.65
-
U
-
1
-
X
4.3
-
5.2
Y
6.9
-
7.5
D
Note:
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“D” and “E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not
exceed 0.15 mm per side.
Doc ID 022637 Rev 2
L99MM70XP
11
Revision history
Revision history
Table 51.
Document revision history
Date
Revision
Changes
04-Jan-2012
1
Initial release.
19-Sep-2013
2
Updated Disclaimer.
Doc ID 022637 Rev 2
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L99MM70XP
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