LNBH25PQR

LNBH25 LNB supply and control IC with step-up and I²C interface Features ■ Complete interface between LNB and I²C bus ■ Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93 % @ 0.5 A) ■ Selectable output current limit by external resistor ■ Compliant with main satellite receivers output voltage specification (15 programmable levels) ■ Accurate built-in 22 kHz tone generator suits widely accepted standards ■ 22 kHz tone waveform integrity guaranteed also at no load condition ■ Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allowing low power losses ■ LPM function (low power mode) to reduce dissipation ■ Overload and overtemperature internal protections with I²C diagnostic bits ■ LNB short-circuit dynamic protection ■ +/- 4 kV ESD tolerant on output power pins Applications ■ STB satellite receivers ■ TV satellite receivers ■ PC card satellite receivers Table 1. QFN24 (4 x 4 mm) Description Intended for analog and digital satellite receivers/Sat-TV and Sat-PC cards, the LNBH25 is a monolithic voltage regulator and interface IC, assembled in QFN24 4x4 specifically designed to provide the 13/18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count and low power dissipation together with a simple design and I²C standard interfacing. Device summary Order code Package Packaging LNBH25PQR QFN24 (4 x 4) Tape and reel February 2012 Doc ID 022433 Rev 4 1/34 www.st.com 34 Contents LNBH25 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 LPM (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 DiSEqC 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 Surge protections and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.10 FLT: fault flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.11 VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.12 TMON: 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.13 TDET: 22 kHz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.14 IMON: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.15 PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8 2.16 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8 2.17 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.18 ISW: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.19 COMP: boost capacitor ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.20 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9 2.21 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/34 Doc ID 022433 Rev 4 LNBH25 7 Contents 6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Doc ID 022433 Rev 4 3/34 Block diagram 1 LNBH25 Block diagram Figure 1. Block diagram ADDR SCL SDA LX PWM CTRL I2C Digital core DETIN DSQOUT Tone detector DAC Drop control Tone ctrl Diagnostics Protections FLT Isense DSQIN PGND VUP Current Limit selection Linear Regulator Gate ctrl BPSW VOUT Voltage reference GND 4/34 BYP VCC ISEL Doc ID 022433 Rev 4 AM10400v1 LNBH25 2 Application information Application information This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (Vup) that let the integrated LDO post-regulator (generating the 13 V /18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at Vup-VOUT = 1 V typ.). The LDO power dissipation can be further reduced when the 22 kHz tone output is disabled by setting the LPM bit to “1” (see 2.4: LPM (low power mode)). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start function reduces the inrush current during start-up. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. switch from 0 to 18 V. 2.1 DiSEqC data encoding (DSQIN pin) The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards, and can be activated in 3 different ways: 1. by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL compatible). In this case the I²C Tone control bits must be set: EXTM = TEN = 1. 2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this case the I²C Tone control bits must be set: EXTM = 0 and TEN = 1. 3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”. Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC data transmission, the LPM bit must be set to “0” (see 2.4: LPM (low power mode)). 2.2 Data encoding by external 22 kHz tone TTL signal In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”. The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the LNBH25 integrated tone generator. The output tone waveforms are internally controlled by the LNBH25 tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH25 activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired (refer to Figure 2). Doc ID 022433 Rev 4 5/34 Application information Figure 2. LNBH25 Tone enable and disable timing (using external waveform) DSQIN ~ 1 µs ~ 60 µs Tone Output AM10426v1 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C Tone control bits must be set: EXTM = 0 and TEN = 1. In this way, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH, the internal control circuit activates the 22 kHz tone output. The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired (refer to Figure 3). Figure 3. Tone enable and disable timing (using envelope signal) DSQIN 15 µs ~ 60 µs ~ 6 µs Tone Output AM10427v1 2.4 LPM (low power mode) In order to reduce total power loss, the LNBH25 is provided with the LPM I²C bit that can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time periods. The LPM bit can be set to “1” when the DiSEqC data transmission is not requested (no 22 kHz tone output is present); at this condition the drop voltage across the integrated LDO regulator (VUP-VOUT) is reduced to 0.6 V typ. and, consequently, the power loss inside the LNBH25 linear regulator is reduced too. For example: at 500 mA load, LPM=1 allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0” before starting the 22 kHz DiSEqC data transmission; at this condition the drop voltage across the LDO is kept to 1 V typ. Keep LPM=0 at all times in case the LPM function is not used. 2.5 DiSEqC 2.0 implementation The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing. The input pin (DETIN) must be AC coupled to the DiSEqC BUS, and extracted PWK data is available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus hardware 6/34 Doc ID 022433 Rev 4 LNBH25 Application information requirements an output RL filter is needed. In order to avoid 22 kHz waveform distortion during tone transmission, LNBH25 is provided with the BPSW pin to be connected to an external transistor, which allows to bypass the output RL filter in DiSEqC 2.x applications while in transmission mode. Before starting tone transmission by means of the DSQIN pin, make sure that the TEN bit is preventively set to “1” and after ending tone transmission, make sure that the TEN bit is set to “0”. 2.6 Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation: Equation 1 IMAX ( typ.) = 13915 RSEL1.111 with ISET=0 Equation 2 IMAX (typ.) = 6808 RSEL1.068 with ISET=1 (Refer also to the ISET bit description in Table 9). where RSEL is the resistor connected between ISEL and GND expressed in kΩ and IMAX(typ.) is the typical current limit threshold expressed in mA. IMAX can be set up to 1 A. 2.7 Output voltage selection The linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal DATA 1 register (see 7.3: Data registers and Table 14 for exact programmable values). Register writing is accessible via the I²C bus. 2.8 Diagnostic and protection functions LNBH25 has 8 diagnostic internal functions provided via the I²C bus, by reading 8 bits on two STATUS registers (in read mode). All the diagnostic bits are, in normal operation (that is no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature and overload protection status (OTF and OLF) while the remaining 6 bits are dedicated to the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum load current (IMON), to external voltage source presence on the VOUT pin (PDO), to the input voltage Power Not Good function (PNG) and to the 22 kHz tone presence on the DETIN pin (TDET). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is latched to “1” until relevant cause is removed and a new register reading operation is done. Doc ID 022433 Rev 4 7/34 Application information 2.9 LNBH25 Surge protections and TVS diodes The LNBH25 device is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect the STB output circuits where the LNBH25 and other devices are electrically connected to the antenna cable. Figure 4. Surge protection circuit For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically designed by ST. The selection of LNBTVS diodes should be made based on the maximum peak power dissipation that the diode is capable of supporting (see Ppp (W) parameter in the LNBTVS datasheet for further details). 2.10 FLT: fault flag In order to get an immediate feedback on diagnostic status, LNBH25 is equipped with a dedicated fault flag pin (FLT). In the case of overload (OLF bit=1) or overheating (OTF bit=1) or if Power No Good (PNG bit=1) condition is detected, the FLT pin (open drain output) is set to low and is kept low until the relevant activating diagnostic bit is cleared. Be aware that diagnostic bits OLF, OTF and PNG, once activated, are kept latched to “1” until the cause origin is removed and a new register reading operation is performed by the microprocessor. The FLT pin must be connected to a positive voltage (5 V max.) by means of a pull-up resistor. 2.11 VMON: output voltage diagnostic When device output voltage is activated (VOUT pin), its value is internally monitored and, as long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to “1”. See Table 17 for more details. 2.12 TMON: 22 kHz tone diagnostic The 22 kHz tone can be internally detected and monitored if the DETIN pin is connected to the LNB output bus (see typical application circuit in Figure 7) through a decoupling capacitor. The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz tone amplitude and/or the tone frequency is out of the guaranteed limits (see Table 19), the TMON I²C bit is set to “1”. 8/34 Doc ID 022433 Rev 4 LNBH25 2.13 Application information TDET: 22 kHz tone detection When a 22 kHz tone presence is detected on the DETIN pin, the TDET I²C bit is set to “1”. 2.14 IMON: minimum output current diagnostic In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) the LNBH25 is provided with a minimum output current flag by the IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than 12 mA (typ.). It is recommended to use IMON function only with the 22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the output current is below the minimum current threshold. To activate IMON diagnostic function, set to “1” the EN_IMON I²C bit in the DATA 4 register. Be aware that as soon as the IMON function is activated by means of EN_IMON=1, the VOUT is immediately increased to 21 V (typ.) independently on the VSEL bit setting. This operation is applied in order to be sure that the LNBH25 output has the higher voltage present in the LNB bus. Do not use this function in an application environment where 21 V voltage level is not supported by other peripherals connected to the LNB bus. 2.15 PDO: overcurrent detection on output pull-down stage When an overcurrent occurs on the pull-down output stage due to an external voltage source greater than LNBH25 nominal VOUT and for a time longer than ISINK_TIME-OUT (10 ms typ.), the PDO I²C bit is set to “1”. This may happen due to an external voltage source present on the LNB output (VOUT pin). For current threshold and deglitch time details, see Table 13. 2.16 Power-on I²C interface reset and undervoltage lockout The I²C interface built into LNBH25 is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ. the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor. 2.17 PNG: input voltage minimum detection When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to Table 13 for threshold details. 2.18 ISW: inductor switching current limit In order to allow low saturation current inductors to be used, the maximum DC-DC inductor switching current limit threshold can be set by means of one I²C bit (ISW). Two values are available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0). Doc ID 022433 Rev 4 9/34 Application information 2.19 LNBH25 COMP: boost capacitor ESR DC-DC converter compensation loop can be optimized in order to work well with high or low ESR capacitors (on the VUP pin). For this purpose, one I²C bit in the DATA 4 register (COMP) can be set to “1” or “0”. It is recommended to reset this bit to “0” unless using high ESR capacitors. 2.20 OLF: overcurrent and short-circuit protection and diagnostic In order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C DATA 3 register. When the PCL (pulsed current limiting) bit is set Io LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for TON time (90 ms or 180 ms typ., according to the TIMER bit programmed in the DATA 3 register) and after that, the output is set in shutdown for TOFF time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register is set to “1” and the FLT pin is set to low level. After this time has elapsed, the output is resumed for a time TON. At the end of TON, if the overload is still detected, the protection circuit cycles again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical TON +TOFF time is 990 ms (if TIMER=0) or 1080 ms (if TIMER=1) and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on startup in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns LOW when the overload condition is cleared and register reading is done. After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA 4 register. If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To reenable output stage, the VSEL bits must be set again by the microprocessor, and the OLF bit is reset to “0” after a register reading operation. If OLR=0, output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation. 2.21 OTF: thermal protection and diagnostic The LNBH25 is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1” and the FLT pin is set to low level. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA 4 register. If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To reenable output stage, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation. If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation. 10/34 Doc ID 022433 Rev 4 LNBH25 3 Pin configuration Pin configuration Figure 5. Pin connections (top view) 24 NC Table 2. 23 22 DSQOUT DSQIN/ DSQIN EXTM 21 20 19 VUP VOUT DETIN 1 NC BPSW 18 2 FLT VCC 17 3 LX-A LX VBYP 16 4 PGND GND 15 5 NC NC 14 6 ADDR NC 13 SCL SDA ISEL NC NC NC 7 8 9 10 11 12 AM09909v1 Pin description Pin n° Symbol Name Pin function 2 FLT FLT Open drain output for IC fault conditions. It is set low in case of overload (OLF bit) or overheating status (OTF bit) or power not good (PNG) is detected. To be connected to pull-up resistor (5 V max.). 3 LX N-MOS drain Integrated N-channel Power MOSFET drain. 4 P-GND Power ground DC-DC converter power ground. To be connected directly to the Epad. 6 ADDR Address setting Two I²C bus addresses available by setting the address pin level voltage. See Table 16. 7 SCL Serial clock Clock from I²C BUS. 8 SDA Serial data Bi-directional data from/to I²C BUS. 9 ISEL 15 GND 16 BYP 17 VCC The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold. Refer to Section 2.6 in the Current selection Application Information section. Also see the ISET bit description in Table 9. Analog ground Analog circuits ground. To be connected directly to the Epad. Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of Bypass capacitor this pin to external current or voltage sources may cause permanent damage to the device. Supply input 8 to 16 V IC DC-DC power supply. Doc ID 022433 Rev 4 11/34 Pin configuration Table 2. LNBH25 Pin description (continued) Pin n° Symbol Name Pin function 18 BPSW Switch control To be connected to an external transistor to be used to bypass the output RL filter needed in DiSEqC 2.x applications during the DiSEqC transmitting mode (see Section 5). Set to ground if not used. Open drain pin. 19 DETIN Tone detector input 22 kHz tone decoder input open drain pin, must be AC coupled to the DiSEqC 2.0 bus. Set to ground if not used. 20 VOUT LNB output port Output of the integrated very low drop linear regulator. See Table 14 for voltage selections and description. 21 VUP Step-up voltage Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. 22 DSQIN DSQIN for DiSEqC envelope input or External 22 kHz TTL input It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM I²C bit setting as follows: EXTM=0, TEN=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH25 uses this code to modulate the internally generated 22 kHz carrier. If EXTM=TEN=1: it accepts external 22 kHz logic signals which activate the 22 kHz tone output (refer to Section 2.3). Pull-up high if the tone output is activated only by the TEN I²C bit. 23 DSQOUT DiSEqC output Open drain output of the tone detector to the main microcontroller for DiSEqC 2.0 data decoding. It is low when tone is detected to the DETIN input pin. Set to ground if not used. Epad Epad Exposed pad To be connected with power grounds and to the ground layer through vias to dissipate the heat. 1, 5, 10, 11, 12, 13, 14, 24 N.C. Not internally connected Not internally connected pins. These pins can be connected to GND to improve thermal performances. 12/34 Doc ID 022433 Rev 4 LNBH25 Maximum ratings 4 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC power supply input voltage pins -0.3 to 20 V VUP DC input voltage -0.3 to 40 V IOUT Output current Internally limited mA VOUT DC output pin voltage -0.3 to 40 V VI Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V VO Logic output pins voltage (FLT, DSQOUT) -0.3 to 7 V VBPSW BPSW pin voltage -0.3 to 40 V VDETIN Detector input signal amplitude -0.6 to 2 V 10 mA IO Logic output pins current (FLT, DSQOUT, BPSW) LX LX input voltage -0.3 to 30 V VBYP Internal reference pin voltage -0.3 to 4.6 V ISEL Current selection pin voltage -0.3 to 3.5 V TSTG Storage temperature range -50 to 150 °C Operating junction temperature range -25 to 125 °C TJ ESD Table 4. Symbol ESD rating with human body model (HBM) all pins, unless power output pins 2 ESD rating with human body model (HBM) for power output pins 4 kV Thermal data Parameter Value Unit RthJC Thermal resistance junction-case 2 °C/W RthJA Thermal resistance junction-ambient with device soldered on 2s2p 4layer PCB provided with thermal vias below exposed pad. 40 °C/W Note: Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Doc ID 022433 Rev 4 13/34 Typical application circuits 5 LNBH25 Typical application circuits Figure 6. DiSEqC 1.x application circuit D2 to LNB 21 D1 C2 Vup Vout 20 C3 C5 3 LX D3 LNBH25 L1 Vin 12V 17 Vcc 22 DSQIN C4 C1 DiSEqC 22KHz TTL or DiSEqC Envelope TTL I 2C Bus { 6 ADDR 8 SDA 7 SCL 9 ISEL FLT 2 Byp 16 R1 (RSEL) P-GND A -GND 4 15 C7 AM10431v1 Table 5. DiSEqC 1.X bill of material Component R1 (RSEL) C1, C2 SMD resistor. Refer to Table 13 and ISEL pin description in Table 2 > 25 V electrolytic capacitor, 100 µF is suitable. C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise. C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise. C4, C7 14/34 Notes 220 nF ceramic capacitors. D1 STPS130A or similar schottky diode. D3 BAT54, BAT43, 1N5818, or any low power schottky diode with IF (AV) > 0.2 A, VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin. D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier. L1 10 µH inductor with Isat > Ipeak where Ipeak is the boost converter peak current. Doc ID 022433 Rev 4 LNBH25 Typical application circuits Figure 7. DiSEqC 2.x application circuit D2 to LNB L2 21 D1 C2 Vup Vout 20 15 Ω C3 C5 3 LX D3 LNBH25 4.7k L1 BPSW 4.7k Vin 12V Vcc 22 DSQIN 6 ADDR C6 19 10k C4 C1 DiSEqC 22KHz 17 DETIN TR1 18 TTL or DiSEqC Envelope TTL { 8 SDA 7 SCL 9 ISEL I2C Bus DSQOUT 23 FLT 2 Byp 16 Open drains to µController R1 (RSEL) P-GND 4 A -GND 15 C7 AM10432v1 Table 6. DiSEqC 2.x bill of material Component R1 (RSEL) C1, C2 Notes SMD resistors. Refer to Table 13 and ISEL pin description in Table 2 > 25 V electrolytic capacitor, 100 µF is suitable. C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise. C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise. C4, C7 220 nF ceramic capacitors. C6 10 nF ceramic capacitors. D1 STPS130A or similar schottky diode. D3 BAT54, BAT43, 1N5818, or any low power schottky diode with IF (AV) > 0.2 A, VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin. D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier. L1 10 µH inductor with Isat > Ipeak where Ipeak is the boost converter peak current. L2 220 µH inductor. TR1 2STR2160 or 2STF2340 or any small power PNP with, IC > 250 mA, VCE > 30 V can be used. Also any small power PMOS with ID > 250 mA, RDSON < 0.5Ω, VDS > 20 V, can be used. Doc ID 022433 Rev 4 15/34 I²C bus interface 6 LNBH25 I²C bus interface Data transmission from the main microprocessor to the LNBH25 and vice versa takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 6.1 Data validity As shown in Figure 8, the data on the SDA line must be stable during the high semi-period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 6.2 Start and stop condition As shown in Figure 9, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition. 6.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 6.4 Acknowledge The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 10). The peripheral (LNBH25) which acknowledges must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH25 won't generate acknowledge if the VCC supply is below the undervoltage lockout threshold (4.7 V typ.). 6.5 Transmission without acknowledge Avoiding to detect the acknowledges of the LNBH25, the microprocessor can use a simpler transmission: it simply waits one clock without checking the slave acknowledging, and sends the new data. This approach is of course less protected from misworking and decreases noise immunity. 16/34 Doc ID 022433 Rev 4 LNBH25 I²C bus interface Figure 8. Data validity on the I²C bus Figure 9. Timing diagram of I²C bus Figure 10. Acknowledge on the I²C bus Doc ID 022433 Rev 4 17/34 I²C interface protocol LNBH25 7 I²C interface protocol 7.1 Write mode transmission The LNBH25 interface protocol comprises: ● a start condition (S) ● a chip address byte with the LSB bit R/W = 0 ● a register address (internal address of the first register to be accessed) ● a sequence of data (byte to write in the addressed internal register + acknowledge) ● the following bytes, if any, to be written in successive internal registers ● a stop condition (P). The transfer lasts until a stop bit is encountered ● the LNBH25, as slave, acknowledges every byte transfer. Figure 11. Example of writing procedure starting with first data address 0x2 (a) CHIP ADDRESS LSB MSB 0 1 0 0 X LSB 0 0 0 0 DATA 1 Add=0x2 MSB 0 X X X ACK 0 MSB ACK 0 R/W = 0 S REGISTER ADDRESS DATA 3 Add=0x4 DATA 2 Add=0x3 LSB MSB MSB LSB DATA 4 Add=0x5 LSB MSB LSB ACK N/A EN_IMON N/A N/A OLR N/A ACK THERM COMP N/A ISET ISW PCL TIMER N/A N/A N/A TEN ACK N/A LPM EXTM N/A N/A N/A N/A ACK N/A VSEL1 VSEL2 VSEL3 VSEL4 N/A N/A N/A P AM09913v2 ACK = Acknowledge S = Start P = Stop R/W = 1/0, Read/Write bit X = 0/1, set the values to select the CHIP ADDRESS (see Chip Address in Table 16 for pin selection) and to select the REGISTER Address (see Table 7). a. The writing procedure can start from any Register Address by simply setting the X values in the Register Address byte (after the Chip Address). It can be also stopped from the master by sending a stop condition after any acknowledge bit. 18/34 Doc ID 022433 Rev 4 LNBH25 I²C interface protocol 7.2 Read mode transmission In Read mode the bytes sequence must be as follows: ● a start condition (S) ● a chip address byte with the LSB bit R/W=0 ● the register address byte of the internal first register to be accessed ● a stop condition (P) ● a new master transmission with the chip address byte and the LSB bit R/W=1 ● after the acknowledge the LNBH25 starts to send the addressed register content. As long as the master keeps the acknowledge LOW, the LNBH25 transmits the next address register byte content. ● the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit. Figure 12. Example of reading procedure starting with first status address 0X0 (b) REGISTER ADDRESS CHIP ADDRESS MSB 0 0 X 0 0 0 0 0 X X X P MSB 1 0 X 0 ACK TDET N/A TMON N/A IMON N/A N/A N/A OLF ACK N/A VMON N/A N/A PDO MSB 0 LSB DATA 3 Add=0x4 DATA 2 Add=0x3 LSB 0 MSB LSB OTF PNG MSB 0 STATUS 2 Add=0x1 STATUS 1 Add=0x0 DATA 1 Add=0x2 S ACK 1 LSB R/W = 1 0 MSB ACK 0 CHIP ADDRESS LSB MSB ACK 0 R/W = 0 S LSB MSB LSB DATA 4 Add=0x5 LSB MSB LSB ACK N/A EN_IMON N/A N/A OLR N/A ACK THERM COMP N/A ISET ISW PCL TIMER N/A N/A N/A ACK N/A TEN LPM EXTM N/A N/A N/A N/A ACK N/A VSEL1 VSEL2 VSEL3 VSEL4 N/A N/A N/A P AM09914v2 ACK = Acknowledge S = Start P = Stop R/W = 1/0, Read/Write bit X = 0/1, set the values to select the CHIP ADDRESS (see Chip Address in Table 16 for pin selection) and to select the REGISTER Address (see Table 7). b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X values in the register address byte (after the first Chip Address in the above figure). It can be also stopped from the master by sending a stop condition after any acknowledge bit. Doc ID 022433 Rev 4 19/34 I²C interface protocol 7.3 LNBH25 Data registers The DATA 1..4 registers can be addressed both in write and read mode. In read mode they return the last writing byte status received in the previous write transmission. The following tables provide the Register Address values of Data 1..4 and a function description of each bit. Table 7. DATA 1 (Read/Write register. Register address = 0X2) BIT Name Value Description Bit 0 (LSB) VSEL1 0/1 Bit 1 VSEL2 0/1 Bit 2 VSEL3 0/1 Bit 3 VSEL4 0/1 Bit 4 N/A 0 Reserved. Keep to "0" Bit 5 N/A 0 Reserved. Keep to "0" Bit 6 N/A 0 Reserved. Keep to "0" Bit 7 (MSB) N/A 0 Reserved. Keep to "0" Output voltage selection bits. (Refer to Table 14) N/A = Reserved bit. All bits reset to “0” at power-on. Table 8. DATA 2 (Read/Write register. Register address = 0X3) BIT Name Bit 0 (LSB) TEN Bit 1 LPM Bit 2 Value Description 1 22 kHz tone enabled. Tone output controlled by DSQIN pin 0 22 kHz tone output disabled 1 Low power mode activated (used only with 22 kHz tone output disabled) 0 Low power mode deactivated (keep always LPM = 0 during 22 kHz tone transmission) 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal EXTM Bit 3 N/A 0 Reserved. Keep to “0” Bit 4 N/A 0 Reserved. Keep to "0" Bit 5 N/A 0 Reserved. Keep to "0" Bit 6 N/A 0 Reserved. Keep to "0" Bit 7 (MSB) N/A 0 Reserved. Keep to "0" N/A = Reserved bit. All bits reset to 0 at power-on. 20/34 Doc ID 022433 Rev 4 LNBH25 Table 9. BIT Bit 0 (LSB) Bit 1 Bit 2 Bit 3 I²C interface protocol DATA 3 (Read/Write register. Register address = 0X4) Name Value Description 1 Current limit of LNB output (VOUT pin) set to lower current range. Refer to Section 2.6 in Application Information section. 0 Current Limit of LNB output (VOUT pin) set to default range. Refer to Section 2.6 in Application Information section. 1 DC-DC, inductor switching current limit set to 2.5 A typ. 0 DC-DC, inductor switching current limit set to 4 A typ. 1 Pulsed (Dynamic) LNB output current limiting is deactivated 0 Pulsed (Dynamic) LNB output current limiting is activated 1 Pulsed (Dynamic) LNB output current TON time set to 180 ms typ. 0 Pulsed (Dynamic) LNB output current TON time set to 90 ms typ. ISET ISW PCL TIMER Bit 4 N/A 0 Reserved. Keep to "0" Bit 5 N/A 0 Reserved. Keep to "0" Bit 6 N/A 0 Reserved. Keep to "0" Bit 7 (MSB) N/A 0 Reserved. Keep to "0" N/A = Reserved bit. All bits reset to 0 at power-on. Table 10. DATA 4 (Read/Write register. Register address = 0X5) BIT Name Bit 0 (LSB) EN_IMON Bit 1 Bit 2 Bit 3 Value Description 1 IMON Diagnostic function is enabled. (VOUT is set to 21 V typ.) 0 IMON Diagnostic function is disabled, keep always at “0” if IMON is not used N/A - Reserved N/A - Reserved 1 In case overload protection activation (OLF=1), all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0). 0 In case of overload protection activation (OLF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overload conditions is removed (OLF=0) with the previous VSEL bits setting. OLR Bit 4 N/A - Reserved Bit 5 N/A - Reserved Doc ID 022433 Rev 4 21/34 I²C interface protocol Table 10. BIT Bit 6 Bit 7 (MSB) LNBH25 DATA 4 (Read/Write register. Register address = 0X5) (continued) Name Value Description 1 If Thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=0). 0 In case of Thermal protection activation (OTF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=0) with the previous VSEL bits setting. 1 DC-DC converter compensation set to use HIGH ESR capacitors (VUP pin) 0 DC-DC converter compensation set to use LOW ESR capacitors (VUP pin) THERM COMP N/A = Reserved bit. All bits reset to 0 at power-on. 7.4 Status registers The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables. Table 11. STATUS 1 (Read register. Register address = 0X0) BIT Name Bit 0 (LSB) OLF Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB) N/A Value Description 1 VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 9 for the overload operation settings (ISET, PCL, TIMER bits). 0 No overload protection has been triggered to the VOUT pin (IOUT < IMAX). - Reserved 1 Output voltage (VOUT pin) lower than VMON specification thresholds. Refer to Table 17. 0 Output voltage (VOUT pin) is within the VMON specifications. - Reserved 1 Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (VOUT pin). 0 No overcurrent detected on output pull-down stage. - Reserved 1 Junction overtemperature is detected, TJ > 150 °C. See also THERM bit setting in Table 10. 0 Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal protection threshold. 1 Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 13. 0 Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 13. VMON N/A PDO N/A OTF PNG N/A = Reserved bit. All bits reset to 0 at power-on. 22/34 Doc ID 022433 Rev 4 LNBH25 Table 12. I²C interface protocol STATUS 2 (Read register. Register address = 0X1) BIT Name Bit 0 (LSB) TDET Bit 1 N/A Bit 2 Bit 3 Bit 4 Value 1 22 kHz tone presence is detected on the DETIN pin 0 No 22 kHz tone is detected on the DETIN pin - Reserved 1 22 kHz tone present on the DETIN pin is out of TMON specification thresholds. That is: the tone frequency or the ATONE (tone Amplitude) are out of the thresholds guaranteed in the TMON electrical characteristics table. 0 22 kHz tone present on the DETIN pin is within TMON specification thresholds. Refer to Table 19. - Reserved 1 Output current (from VOUT pin) is lower than IMON specification thresholds. Refer to Table 18. 0 Output current (from VOUT pin) is higher than IMON specifications. Refer toTable 18. TMON N/A Description IMON Bit 5 N/A - Reserved Bit 6 N/A - Reserved Bit 7 (MSB) N/A - Reserved N/A = Reserved bit. All bits reset to 0 at power-on. Doc ID 022433 Rev 4 23/34 Electrical characteristics 8 LNBH25 Electrical characteristics Refer to Section 5, TJ from 0 to 85 °C, all DATA 1..4 register bits set to 0 unless VSEL1 = 1, RSEL = 11.5 kΩ, DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section for I²C access to the system register (Section 6 and Section 7). Table 13. Symbol VIN IIN Electrical characteristics Parameter Test conditions Supply voltage (1) Supply current Max. Unit 8 12 16 V 6 mA 22 kHz Tone enabled (TEN=1), DSQIN = High, IOUT= 0 mA 10 mA VSEL1=VSEL2=VSEL3=VSEL4=0 1 mA Output voltage total accuracy Valid at any VOUT selected level VOUT Line regulation VIN = 8 to 16 V VOUT Load regulation IOUT from 50 to 750 mA IMAX Output current limiting thresholds IMAX Typ. IOUT = 0 mA VOUT Output current limiting thresholds Min. -3.5 +3.5 % 40 mV 100 RSEL = 11.5 kΩ, ISET = 0 750 1100 RSEL = 16.2 kΩ, ISET = 0 500 750 RSEL = 22 kΩ, ISET = 0 350 550 mA RSEL = 11.5 kΩ, ISET = 1 500 RSEL = 16.2 kΩ, ISET = 1 350 RSEL = 22 kΩ, ISET = 1 250 500 mA mA ISC Output short-circuit current RSEL = 11.5 kΩ, ISET= 0 SS Soft-start time VOUT from 0 to 13 V 4 ms SS Soft-start time VOUT from 0 to 18 V 6 ms T13-18 Soft transition rise time VOUT from 13 to 18 V 1.5 ms T18-13 Soft transition fall time VOUT from 18 to 13 V 1.5 ms TOFF Dynamic overload protection PCL=0, Output Shorted OFF Time TON Dynamic overload protection PCL = TIMER = 0, Output Shorted ON Time PCL = 0, TIMER = 1, Output Shorted ATONE Tone amplitude FTONE Tone frequency DTONE Tone duty cycle tr, tf Tone rise or fall time DSQIN=High, EXTM=0, TEN=1 IOUT from 0 to 750 mA CBUS from 0 to 750 nF DSQIN=High, EXTM=0, TEN=1 (2) EffDC/DC DC-DC converter efficiency 24/34 IOUT = 500 mA Doc ID 022433 Rev 4 900 ms TOFF/10 TOFF/5 0.55 0.675 0.8 VPP 20 22 24 kHz 43 50 57 % 5 8 15 µs 93 % LNBH25 Table 13. Symbol FSW Electrical characteristics Electrical characteristics (continued) Parameter Test conditions Min. DC-DC converter switching frequency Typ. UVLO Threshold Rising 4.8 UVLO Threshold Falling 4.7 Low power diagnostic (LPD) thresholds VLP Threshold Rising 7.2 VLP VLP Threshold Falling 6.7 VIL DSQIN, pin logic low VIH DSQIN, pin logic high IIH DSQIN, pin input current VIH = 5 V FDETIN Tone detector frequency capture range (3) 0.4VPP sine wave 19 VDETIN Tone detector input amplitude (3) Sine wave signal, 22 kHz 0.3 ZDETIN Tone detector input impedance VOL_BPS Unit 440 Undervoltage lockout thresholds UVLO Max. kHz V V 0.8 2 V V 15 22 µA 25 kHz 1.5 VPP 150 kΩ V BPSW pin low voltage IOL_BPSW = 5 mA, DSQIN = high, EXTM=0, TEN=1 0.7 VOL DSQOUT, FLT pins logic LOW DETIN Tone present, IOL= 2 mA 0.3 IOZ DSQOUT, FLT pins leakage current DETIN Tone absent, VOH = 6 V IOBK Output backward current All VSELx=0, VOBK = 30 V -3 ISINK Output low-side sink current VOUT forced at VOUT_NOM + 0.1 V 70 mA VOUT forced at VOUT_NOM + 0.1 V PDO I²C bit is set to 1 after this time is elapsed 10 ms VOUT forced at VOUT_NOM + 0.1 V after PDO bit is set to 1 (ISINK_TIME-OUT elapsed) 2 mA W ISINK_ Low-side sink current timeTIME-OUT out 0.5 V 10 µA -6 mA IREV Max. reverse current TSHDN Thermal shut-down threshold 150 °C ΔTSHDN Thermal shut-down hysteresis 15 °C 1. In applications where (VCC -VOUT) > 1.3 V the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design. 2. Guaranteed by design. 3. Frequency range in which the DETIN function is guaranteed. The VPP level is intended on the LNB bus (before the C6 capacitor. See typical application circuit for DiSEqC 2.x). IOUT from 0 to 750 mA, CBUS from 0 to 750 nF. Doc ID 022433 Rev 4 25/34 Electrical characteristics Table 14. LNBH25 Output voltage selection table (Data1 register, write mode) (1) VOUT min. VOUT pin voltage VOUT max. VSEL4 VSEL3 VSEL2 VSEL1 0 0 0 0 0 0 0 1 12.545 13.000 13.455 0 0 1 0 12.867 13.333 13.800 0 0 1 1 13.188 13.667 14.145 0 1 0 0 13.51 14.000 14.490 0 1 0 1 13.832 14.333 14.835 0 1 1 0 14.153 14.667 15.180 0 1 1 1 14.475 15.000 15.525 1 0 0 0 17.515 18.150 18.785 1 0 0 1 17.836 18.483 19.130 1 0 1 0 18.158 18.817 19.475 1 0 1 1 18.48 19.150 19.820 1 1 0 0 18.801 19.483 20.165 1 1 0 1 19.123 19.817 20.510 1 1 1 0 19.445 20.150 20.855 1 1 1 1 19.766 20.483 21.200 Function VOUT disabled. LNBH25 set in standby mode 0.000 1. TJ from 0 to 85 °C, VI = 12 V. TJ from 0 to 85 °C, VI = 12 V. Table 15. Symbol I²C electrical characteristics Parameter Test conditions VIL LOW level input voltage SDA, SCL VIH HIGH level input voltage SDA, SCL IIN Input current VOL FMAX Low level output voltage SDA, SCL, VIN = 0.4 to 4.5 V (1) Maximum clock frequency SCL -10 400 Doc ID 022433 Rev 4 Typ. Max. Unit 0.8 V 2 SDA (open drain), IOL = 6 mA 1. Guaranteed by design. 26/34 Min. V 10 µA 0.6 V kHz LNBH25 Electrical characteristics TJ from 0 to 85 °C, VI = 12 V. Table 16. Symbol Address pin characteristics Parameter Test condition Min. Typ. Max. Unit VADDR-1 “0001000(R/W)” Address pin R/W bit determines the transmission voltage range mode: read (R/W=1) write (R/W=0) 0 0.8 V VADDR-2 “0001001(R/W)” Address pin R/W bit determines the transmission voltage range mode: read (R/W=1) write (R/W=0) 2 5 V Refer to Section 5, TJ from 0 to 85°C, All DATA 1..4 register bits set to “0”, RSEL = 11.5 kΩ, DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section for I²C access to the system register. Table 17. Symbol Output voltage diagnostic (VMON bit, STATUS 1 register) characteristics Parameter Test condition Min. Typ. Max. Unit VTH-L Diagnostic low threshold at VOUT = 13.0 V VSEL1=1, VSEL2 = VSEL3 = VSEL4 = 0 80 90 95 % VTH-L Diagnostic low threshold at VOUT = 18.15 V VSEL4=1, VSEL1 = VSEL2 = VSEL3 = 0 80 90 95 % Note: If the output voltage is lower than the min. value the VMON I²C bit is set to 1. If VMON=0 then VOUT > 80 % of VOUT typical If VMON=1 then VOUT < 95 % of VOUT typical Refer to Section 5, TJ from 0 to 85 °C, RSEL = 11.5 kΩ, DSQIN = LOW, VIN = 12 V, unless otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section for I²C access to the system register. Table 18. Symbol ITH Note: Output current diagnostic (IMON bit, STATUS 2 register) characteristics Parameter Minimum current diagnostic threshold Test condition Min. Typ. Max. Unit EN_IMON = 1 (VOUT is set to 21 V typ.) 5 12 20 mA If the output current is lower than the min. threshold limit, the IMON I²C bit is set to 1. If the output current is higher than the max. threshold limit, the IMON I²C bit is set to 0. Doc ID 022433 Rev 4 27/34 Electrical characteristics LNBH25 Refer to Section 5, TJ from 0 to 85 °C, All DATA 1..4 register bits set to “0” unless VSEL1 = 1, TEN=1, RSEL = 11.5 kΩ, DSQIN = HIGH, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section for I²C access to the system register. Table 19. Symbol 22 kHz tone diagnostic (TMON bit, STATUS 2 register) characteristics Parameter Test condition Min. Typ. Max. Unit ATH-L Amplitude diagnostic low threshold DETIN pin AC coupled 200 300 400 mV ATH-H Amplitude diagnostic high threshold DETIN pin AC coupled 900 1100 1200 mV FTH-L Frequency diagnostic low thresholds DETIN pin AC coupled 13 16.5 20 kHz FTH-H Frequency diagnostic high thresholds DETIN pin AC coupled 24 29.5 38 kHz Note: 28/34 If the 22 kHz Tone parameters are lower or higher than the above limits, the TMON I²C bit is set to “1”. Doc ID 022433 Rev 4 LNBH25 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 20. QFN24L (4 x 4 mm) mechanical data (mm) Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 3.90 4.00 4.10 D2 2.55 2.70 2.80 E 3.90 4.00 4.10 E2 2.55 2.70 2.80 e 0.45 0.50 0.55 L 0.25 0.35 0.45 Doc ID 022433 Rev 4 29/34 Package mechanical data LNBH25 Figure 13. QFN24L (4 x 4 mm) package dimensions 7596209_D 30/34 Doc ID 022433 Rev 4 LNBH25 Package mechanical data Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 330 C 12.8 D 20.2 N 99 13.2 Max. 12.992 0.504 0.519 0.795 101 T 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 022433 Rev 4 31/34 Package mechanical data LNBH25 Figure 14. QFN24L (4 x 4) footprint recommended data (mm.) 32/34 Doc ID 022433 Rev 4 LNBH25 Revision history 10 Revision history Table 21. Document revision history Date Revision Changes 09-Nov-2011 1 Initial release. 01-Dec-2011 2 Updated mechanical data Table 20 on page 29 and Table 13 on page 30. Added Section 2.9 and Figure 4 on page 8. 13-Jan-2012 3 Modified: header Table 14 on page 26 and test condition Table 17 on page 27. 15-Feb-2012 4 Modified: D1, D3 Table 5 on page 14 and Table 6 on page 15. Doc ID 022433 Rev 4 33/34 LNBH25 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 34/34 Doc ID 022433 Rev 4