STB26N60M2

STB26N60M2 N-channel 600 V, 0.14 Ω typ., 20 A MDmesh™ M2 Power MOSFET in a D²PAK package Datasheet - production data Features TAB Order code VDS @ TJmax RDS(on) max. ID PTOT STB26N60M2 650 V 0.165 Ω 20 A 169 W 2 3 1     D²PAK Figure 1: Internal schematic diagram Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications  Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packing STB26N60M2 26N60M2 D²PAK Tape and reel March 2017 DocID030419 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STB26N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 D²PAK package information .............................................................. 9 4.2 D²PAK packing information ............................................................. 12 Revision history ............................................................................ 14 DocID030419 Rev 1 STB26N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 20 Drain current (continuous) at Tcase = 100 °C 13 IDM(1) Drain current (pulsed) 80 A PTOT W VGS ID Parameter Total dissipation at Tcase = 25 °C 169 dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range -55 to 150 A V/ns °C Notes: (1) Pulse width is limited by safe operating area. (2) ISD ≤ 20 A, di/dt=400 A/μs; VDS(peak) < V(BR)DSS, VDD = 80% V(BR)DSS. (3) VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.74 Thermal resistance junction-pcb 30 Rthj-pcb (1) Value Unit °C/W Notes: (1)When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR(1) Avalanche current, repetitive or not repetitive 3.8 A EAS(2) Single pulse avalanche energy 250 mJ Notes: (1) Pulse width limited by Tjmax. (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID030419 Rev 1 3/15 Electrical characteristics 2 STB26N60M2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C(1) 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 10 A 0.14 0.165 Ω Min. Typ. Max. Unit - 1360 - - 88 - - 2 - IDSS Zero gate voltage drain current IGSS 2 µA Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 124 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4 - Ω Qg Total gate charge - 34 - Qgs Gate-source charge - 5.6 - Qgd Gate-drain charge VDD = 480 V, ID = 20 A, VGS = 0 to 10 V (see Figure 15: "Test circuit for gate charge behavior") - 16.3 - VDS = 100 V, f = 1 MHz, VGS = 0 V Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 4/15 DocID030419 Rev 1 pF nC STB26N60M2 Electrical characteristics Table 7: Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 10 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") Min. Typ. Max. Unit - 20.2 - - 8 - - 66 - - 10 - Min. Typ. Max. Unit ns Table 8: Source-drain diode Symbol Parameter ISD Source-drain current - 20 A ISDM(1) Source-drain current (pulsed) - 80 A VSD(2) Forward on voltage - 1.6 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions VGS = 0 V, ISD = 20 A ISD = 20 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 20 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 360 ns - 5 µC - 27 A - 556 ns - 8 µC - 29 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID030419 Rev 1 5/15 Electrical characteristics 2.1 STB26N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID030419 Rev 1 STB26N60M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID030419 Rev 1 7/15 Test circuits 3 STB26N60M2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/15 DocID030419 Rev 1 Figure 19: Switching time waveform STB26N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 D²PAK package information Figure 20: D²PAK (TO-263) type A package outline DocID030419 Rev 1 9/15 Package information STB26N60M2 Table 9: D²PAK (TO-263) type A package mechanical data mm Dim. Min. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.50 8.70 8.90 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 10/15 Typ. 0.40 0° DocID030419 Rev 1 8° STB26N60M2 Package information Figure 21: D²PAK (TO-263) type A recommended footprint (dimensions are in mm) DocID030419 Rev 1 11/15 Package information 4.2 STB26N60M2 D²PAK packing information Figure 22: D2PAK type A tape outline 12/15 DocID030419 Rev 1 STB26N60M2 Package information Figure 23: D2PAK type A reel outline Table 10: D²PAK type A tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID030419 Rev 1 Min. Max. 330 13.2 26.4 30.4 13/15 Revision history 5 STB26N60M2 Revision history Table 11: Document revision history 14/15 Date Revision 10-Mar-2017 1 DocID030419 Rev 1 Changes First release. STB26N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID030419 Rev 1 15/15