STD95N4LF3
N-channel 40 V, 5.0 mΩ typ., 80 A STripFET™ III Power MOSFET
in a DPAK package
Datasheet — production data
Features
Type
VDSS
STD95N4LF3
40 V
RDS(on)
max
ID
PD
TAB
< 6.0 mΩ 80 A(1) 110 W
3
1. Value limited by wire bonding
■
100% avalanche tested
■
Logic level drive
1
DPAK
Applications
■
Switching application
– Automotive
Description
Figure 1.
Internal schematic diagram
This device is an N-channel enhancement mode
Power MOSFET produced using
STMicroelectronics’ STripFET™ III technology,
which is specifically designed to minimize onresistance and gate charge to provide superior
switching performance.
D (TAB or 2)
G(1)
S(3)
AM01474v1
Table 1.
Device summary
Order codes
Marking
Package
Packaging
STD95N4LF3
95N4LF3
DPAK
Tape and reel
July 2012
This is information on a product in full production.
Doc ID 15372 Rev 3
1/15
www.st.com
15
Contents
STD95N4LF3
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
.............................................. 8
Doc ID 15372 Rev 3
STD95N4LF3
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
40
V
VGS
Gate-source voltage
± 16
V
Drain current (continuous) at TC = 25 °C
80
A
Drain current (continuous) at TC = 100 °C
65
A
Drain current (pulsed)
320
A
Total dissipation at TC = 25 °C
110
W
Derating factor
0.73
W/°C
8
V/ns
Single pulse avalanche energy
400
mJ
Operating junction temperature
Storage temperature
-55 to 175
°C
Value
Unit
ID
(1)
ID
IDM
(2)
PTOT
dv/dt (3)
EAS
(4)
Tj
Tstg
Peak diode recovery voltage slope
1. Value limited by wire bonding
2. Pulse width limited by safe operating area
3. ISD ≤ 80 A, di/dt ≤ 40 A/µs, VDS ≤ V(BR)DSS, TJ ≤ TJMAX
4. Starting TJ = 25 °C, ID = 40 A, VDD = 35 V Figure 16 and Figure 17
Table 3.
Symbol
Thermal data
Parameter
Rthj-case
Thermal resistance junction-case max
1.36
°C/W
Rthj-pcb (1)
Thermal resistance junction-pcb max
50
°C/W
1. When mounted on 1inch² FR-4 2Oz Cu board
Doc ID 15372 Rev 3
3/15
Electrical characteristics
2
STD95N4LF3
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Drain-source
breakdown voltage
ID = 250 μA, VGS =0
IDSS
Zero gate voltage
drain current (VGS = 0)
VDS = 40 V
VDS = 40 V, TC= 125 °C
10
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ± 16 V
±200
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
2.5
V
RDS(on)
Static drain-source onresistance
VGS = 10 V, ID = 40 A
VGS = 5 V, ID = 40 A
5.0
6.0
9.0
mΩ
mΩ
Min.
Typ.
Max.
Unit
-
2500
560
50
pF
pF
pF
ns
ns
ns
ns
V(BR)DSS
Table 5.
Symbol
4/15
On/off states
40
V
1
Dynamic
Parameter
Test conditions
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f = 1 MHz,
VGS = 0
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 20 V, ID = 40 A
RG = 4.7 Ω VGS = 10 V
(see Figure 13 and
Figure 18)
-
7.5
45
45
11
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 20 V, ID = 80 A,
VGS = 10 V (see Figure 14)
-
50
7
9.5
Doc ID 15372 Rev 3
70
nC
nC
nC
STD95N4LF3
Electrical characteristics
Table 6.
Symbol
Source drain diode
Parameter
Test conditions
ISDM (1)
Source-drain current
Source-drain current
(pulsed)
VSD (2)
Forward on voltage
ISD
trr
Qrr
IRRM
ISD = 80 A, VGS = 0
ISD = 80 A, di/dt = 100 A/µs,
Reverse recovery time
VDD = 20 V, Tj = 150 °C
Reverse recovery charge
(see Figure 15 and
Reverse recovery current
Figure 19)
Min.
Max.
Unit
-
80
320
A
A
-
1.5
V
-
Typ.
40
55
3
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Doc ID 15372 Rev 3
5/15
Electrical characteristics
STD95N4LF3
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM01528v1
ID
(A)
is
ea
ar (on)
s
i
S
D
th
in ax R
on
ati by m
r
e
d
Op ite
Lim
100
100µs
1ms
10
10ms
1
TJ=175°C
TC=25°C
Single
pulse
0.1
0.1
Figure 4.
10
1
VDS(V)
Output characteristics
AM01529v1
ID
(A)
VGS=10V
300
AM01530v1
ID
(A)
300
250
250
VDS=10V
4V
200
200
150
150
100
100
3V
50
0
0
Figure 6.
50
1
2
3
4
5
6
7
8
0
0
VDS(V)
Static drain-source on-resistance
AM01532v1
RDS(on)
(mΩ)
6.6
9
Figure 7.
2
4
8
6
VGS(V)
Normalized BVDSS vs temperature
AM01531v1
BVDSS
(norm)
VGS=5V
1.1
6.4
6.2
6.0
1.0
5.8
0.9
5.6
5.4
0.8
5.2
5.0
0
6/15
10 20 30 40 50 60 70 80
ID(A)
Doc ID 15372 Rev 3
-50
0
50
100
150 TJ(°C)
STD95N4LF3
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM01533v1
VGS
(V)
VDD=20V
VGS=10V
ID=80A
12
10
Capacitance variations
AM01534v1
C
(pF)
f=1MHz
VDS=25V
VGS=0
5000
4500
4000
8
3500
6
2500
3000
Ciss
2000
4
1500
1000
2
0
0
10
20
30
40
50 Qg(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
AM01535v1
VGS(th)
(norm)
500
0
0
Coss
Crss
5
15
10
20
25
30
35 VDS(V)
Figure 11. Normalized on resistance vs
temperature
AM01536v1
RDS(on)
(norm)
1.6
1.6
1.4
1.4
1.2
1.2
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-50
0
50
100
150
TJ(°C)
-50
0
50
100
150
TJ(°C)
Figure 12. Source-drain diode forward
characteristics
Doc ID 15372 Rev 3
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Test circuits
3
STD95N4LF3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/15
0
Doc ID 15372 Rev 3
10%
AM01473v1
STD95N4LF3
Test circuits
Figure 19. Diode reverse recovery waveform
Doc ID 15372 Rev 3
9/15
Package mechanical data
4
STD95N4LF3
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 7.
DPAK (TO-252) mechanical data
mm
Dim.
Min.
Typ.
A
2.20
2.40
A1
0.90
1.10
A2
0.03
0.23
b
0.64
0.90
b4
5.20
5.40
c
0.45
0.60
c2
0.48
0.60
D
6.00
6.20
D1
E
5.10
6.40
6.60
E1
4.70
e
2.28
e1
4.40
4.60
H
9.35
10.10
L
1
L1
2.80
L2
0.80
L4
0.60
1
R
V2
10/15
Max.
0.20
0°
8°
Doc ID 15372 Rev 3
STD95N4LF3
Package mechanical data
Figure 20. DPAK (TO-252) drawing
0068772_I
Figure 21. DPAK footprint(a)
6.7
1.8
3
1.6
2.3
6.7
2.3
1.6
AM08850v1
a. All dimensions are in millimeters
Doc ID 15372 Rev 3
11/15
Packing mechanical data
5
STD95N4LF3
Packing mechanical data
Table 8.
DPAK (TO-252) tape and reel mechanical data
Tape
Reel
mm
mm
Dim.
Dim.
Min.
Max.
A0
6.8
7
A
B0
10.4
10.6
B
1.5
12.1
C
12.8
1.6
D
20.2
G
16.4
50
B1
12/15
Min.
Max.
330
13.2
D
1.5
D1
1.5
E
1.65
1.85
N
F
7.4
7.6
T
K0
2.55
2.75
P0
3.9
4.1
Base qty.
2500
P1
7.9
8.1
Bulk qty.
2500
P2
1.9
2.1
R
40
T
0.25
0.35
W
15.7
16.3
Doc ID 15372 Rev 3
18.4
22.4
STD95N4LF3
Packing mechanical data
Figure 22. Tape for DPAK (TO-252)
10 pitches cumulative
tolerance on tape +/- 0.2 mm
T
P0
Top cover
tape
P2
D
E
F
B1
W
K0
B0
For machine ref. only
including draft and
radii concentric around B0
A0
P1
D1
User direction of feed
R
Bending radius
User direction of feed
AM08852v1
Figure 23. Reel for DPAK (TO-252)
T
REEL DIMENSIONS
40mm min.
Access hole
At sl ot location
B
D
C
N
A
Full radius
Tape slot
in core for
tape start 25 mm min.
width
G measured at hub
AM08851v2
Doc ID 15372 Rev 3
13/15
Revision history
6
STD95N4LF3
Revision history
Table 9.
Document revision history
Date
Revision
11-Feb-2009
1
First release
23-Jul-2009
2
Marking on device summary has been corrected.
3
Updated title on the cover page.
Minor text changes.
Updated Section 4: Package mechanical data and Section 5:
Packing mechanical data.
13-Jul-2012
14/15
Changes
Doc ID 15372 Rev 3
STD95N4LF3
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Doc ID 15372 Rev 3
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