STFI7N80K5

STF7N80K5, STFI7N80K5 N-channel 800 V, 0.95 Ω typ., 6 A MDmesh™ K5 Power MOSFETs in TO-220FP and I²PAKFP packages Datasheet - production data Features VDS RDS(on) max. ID PTOT 800 V 1.2 Ω 6A 25 W Order code STF7N80K5 STFI7N80K5 TO-220FP I2PAKFP (TO-281) Figure 1: Internal schematic diagram D(2)      Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications  Switching applications Description G(1) S(3) AM01476v1_No_tab These very high voltage N-channel Power MOSFETs are designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code STF7N80K5 STFI7N80K5 July 2017 Marking Package TO-220FP 7N80K5 I²PAKFP (TO-281) DocID025377 Rev 2 This is information on a product in full production. Packing Tube 1/16 www.st.com Contents STF7N80K5, STFI7N80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/16 4.1 TO-220FP package information ...................................................... 11 4.2 I²PAKFP (TO-281) package information ......................................... 13 Revision history ............................................................................ 15 DocID025377 Rev 2 STF7N80K5, STFI7N80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ±30 V ID(1) Drain current (continuous) at TC = 25 °C 6 A ID(1) Drain current (continuous) at TC = 100 °C 3.8 A IDM(2) Drain current (pulsed) 24 A PTOT W Total dissipation at TC = 25 °C 25 dv/dt (3) Peak diode recovery voltage slope 4.5 dv/dt (4) MOSFET dv/dt ruggedness 50 Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC= 25 °C) VISO Tj Operating junction temperature range Tstg Storage temperature range V/ns 2500 V - 55 to 150 °C Value Unit 5 °C/W 62.5 °C/W Notes: (1)Limited (2)Pulse (3)I SD (4)V by package. width limited by safe operating area ≤6 A, di/dt ≤100 A/μs, VDS(peak) ≤V(BR)DSS DS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 88 mJ DocID025377 Rev 2 3/16 Electrical characteristics 2 STF7N80K5, STFI7N80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 800 V VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V TC = 125 °C (1) 50 µA Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 3 A ±10 µA 4 5 V 0.95 1.2 Ω Min. Typ. Max. Unit - 360 - pF - 30 - pF - 1 - pF - 47 - pf - 20 - pf 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V Co(er)(2) Equivalent capacitance energy related Rg Intrinsic gate resistance f = 1 MHz, ID=0 A - 6 - Ω Qg Total gate charge - 13.4 - nC Qgs Gate-source charge - 3.7 - nC Qgd Gate-drain charge VDD = 640 V, ID = 6 A VGS= 0 to 10 V (see Figure 16: "Test circuit for gate charge behavior") - 7.5 - nC Notes: (1)C o(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. (2)C o(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 4/16 DocID025377 Rev 2 STF7N80K5, STFI7N80K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Test conditions Turn-on delay time tr VDD= 400 V, ID = 3 A, RG = 4.7 Ω VGS = 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") Rise time td(off) Turn-off delay time tf Fall time Min. Typ. Max. Unit - 11.3 - ns - 8.3 - ns - 23.7 - ns - 20.2 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 6 A ISDM(1) Source-drain current (pulsed) - 24 A VSD(2) Forward on voltage ISD = 6 A, VGS = 0 V - 1.5 V trr Reverse recovery time - 315 ns Qrr Reverrse recovery charge - 2.8 µC IRRM Reverse recovery current ISD = 6 A, di/dt = 100 A/µs,VDD = 60 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 17.5 A ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 480 ns - 3.8 µC - 16 A Min. Typ. Max. Unit ±30 - - V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Test conditions Gate-source breakdown voltage IGS= ±1 mA, ID= 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID025377 Rev 2 5/16 Electrical characteristics 2.1 STF7N80K5, STFI7N80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/16 DocID025377 Rev 2 STF7N80K5, STFI7N80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Maximum avalanche energy vs starting TJ DocID025377 Rev 2 7/16 Electrical characteristics STF7N80K5, STFI7N80K5 Figure 14: Source-drain diode forward characteristics 8/16 DocID025377 Rev 2 STF7N80K5, STFI7N80K5 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID025377 Rev 2 9/16 Package information 4 STF7N80K5, STFI7N80K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID025377 Rev 2 STF7N80K5, STFI7N80K5 4.1 Package information TO-220FP package information Figure 21: TO-220FP package outline 7012510_Rev_12_B DocID025377 Rev 2 11/16 Package information STF7N80K5, STFI7N80K5 Table 10: TO-220FP package mechanical data mm Dim. Min. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 12/16 Typ. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID025377 Rev 2 STF7N80K5, STFI7N80K5 4.2 Package information I²PAKFP (TO-281) package information Figure 22: I²PAKFP (TO-281) package outline 8291506 Re v. C DocID025377 Rev 2 13/16 Package information STF7N80K5, STFI7N80K5 Table 11: I²PAKFP (TO-281) mechanical data mm Dim. Min. Typ. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 14/16 Max. 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 L6 7.50 DocID025377 Rev 2 1.25 7.60 7.70 STF7N80K5, STFI7N80K5 5 Revision history Revision history Table 12: Document revision history Date Revision 11-Oct-2013 1 First release. Part numbers previously included in datasheet DocID023448 2 Modified features on cover page. Modified Table 2: "Absolute maximum ratings", Table 7: "Switching times" and Table 9: "Gate-source Zener diode". Minor text changes. 05-Jul-2017 Changes DocID025377 Rev 2 15/16 STF7N80K5, STFI7N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 16/16 DocID025377 Rev 2