STH185N10F3-2

STH185N10F3-2 Automotive-grade N-channel 100 V, 180 A, 3.9 mΩ typ., STripFET™ F3 Power MOSFET in an H²PAK-2 package Datasheet - production data Features Order code VDS RDS(on) max. ID STH185N10F3-2 100 V 4.5 mΩ 180 A    AEC-Q101 qualified Ultra low on-resistance 100% avalanche tested Applications  Switching applications Figure 1: Internal schematic diagram Description This device is an N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. D(TAB) G(1) S(2, 3) AM01475v5 Table 1: Device summary Order code Marking Packages Packing STH185N10F3-2 185N10F3 H2PAK-2 Tape and reel October 2016 DocID026910 Rev 3 This is information on a product in full production. 1/15 www.st.com Contents STH185N10F3-2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 H²PAK-2 package information ......................................................... 10 4.2 H²PAK packing information ............................................................. 12 Revision history ............................................................................ 14 DocID026910 Rev 3 STH185N10F3-2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ± 20 V ID (1) Drain current (continuous) at TC = 25°C 180 A ID (1) Drain current (continuous) at TC=100°C 120 A IDM (2) Drain current (pulsed) 720 A PTOT Total dissipation at TC = 25°C 315 W dv/dt Peak diode recovery voltage slope 20 V/ns Single pulse avalanche energy 350 mJ - 55 to 175 °C Value Unit Thermal resistance junction-case 0.48 °C/W Thermal resistance junction-pcb 35 °C/W EAS (3) Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)Current (2)Pulse limited by package. width limited by safe operating area. (3)Starting Tj = 25 °C, ID = 80 A, VDD = 50 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Notes: (1)When mounted on FR-4 board, on 1inch², 2oz Cu. DocID026910 Rev 3 3/15 Electrical characteristics 2 STH185N10F3-2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS VGS = 0, ID = 250 µA Min. Typ. Max. 100 Unit V VGS = 0, VDS= 100 V, 10 µA VGS = 0, VDS = 100 V, (1) TC =125°C 100 µA ±200 nA 4 V 3.9 4.5 mΩ Min. Typ. Max. Unit - 6665 - pF - 786 - pF - 49 - pF - 114.6 - nC - 38.8 - nC - 31.9 - nC Min. Typ. Max. Unit - 25.6 - ns - 97.1 - ns - 99.9 - ns - 6.9 - ns Gate body leakage current VDS = 0, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID= 60 A 2 Notes: (1)Defined by design, not subject to production test Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VGS = 0, VDS = 25 V, f = 1 MHz VDD = 50 V, ID = 120 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 50 V, ID = 60 A RG = 4.7 Ω VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") DocID026910 Rev 3 STH185N10F3-2 Electrical characteristics Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 180 A ISDM(1) Source-drain current (pulsed) - 720 A VSD(2) Forward on voltage VGS = 0, ISD =120 A - 1.5 V trr Reverse recovery time - 83.4 ns Qrr Reverse recovery charge - 295.7 nC IRRM Reverse recovery current ISD=120 A, di/dt = 100 A/µs, VDD = 80 V, Tj=150°C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 7.1 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300µs, duty cycle 1.5% DocID026910 Rev 3 5/15 Electrical characteristics 2.1 STH185N10F3-2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area GIPG110620141143SA ID (A) 280tok K ᵟ =0.5 100 0.2 is ) ea ar S(on is th R D in ax ion y m at er d b Op ite Lim 10 0.1 100µs 10 0.05 -1 0.02 Zth=k Rthj-c ᵟ =tp/ t 0.01 1 1ms Tj=175°C Tc=25°C Single pulse 0.1 0.1 1 Single pulse tp t 10ms VDS(V) 10 -2 10 -5 10 Figure 4: Output characteristics 10 -4 10 -3 10 -2 10 -1 tp (s) Figure 5: Transfer characteristics AM08616v1 ID(A) AM08617v1 ID (A) V GS=10V 350 350 V DS=2V 7V 300 300 250 250 200 200 150 6V 100 150 100 50 50 5V 0 0 1 0 2 4 3 5 6 7 8 V DS(V) Figure 6: Normalized V(BR)DSS vs temperature AM08618v1 V (BR)DSS (norm) RDS(on) (mΩ) 4.3 1.05 4.1 1.00 3.9 0.95 3.7 -25 25 75 125 175 T J(°C) 1 2 3 4 5 6 7 8 9 V GS(V) Figure 7: Static drain-source on-resistance 1.10 0.90 -75 6/15 ID=1m A 0 3.5 0 DocID026910 Rev 3 AM08626v1 VGS=10V 20 40 60 80 100 120 140 160 180 ID(A) STH185N10F3-2 Electrical characteristics Figure 8: Gate charge vs gate-source voltage Figure 9: Capacitance variations AM08620v1 V GS (V) V DD=50V ID=120 A 12 AM08621v1 C (pF) 20000 10 15000 8 6 10000 4 Ciss 5000 2 Crss Coss 0 0 20 40 60 80 0 0 Q g(nC) 100 120 140 Figure 10: Normalized gate threshold voltage vs temperature 40 60 80 100 V DS(V) Figure 11: Normalized on-resistance vs temperature AM08623v1 R DS(on) AM08622v1 V GS(th) (norm) 20 (norm) ID=250µ A ID=60 A V GS=10V 2.1 1.3 1.9 1.7 1.1 1.5 0.9 1.3 1.1 0.7 0.9 0.5 0.3 -75 0.7 -25 25 75 0.5 -75 175 T J(°C) 125 -25 25 75 125 175 T J(°C) Figure 12: Source-drain diode forward characteristics AM08624v1 V SD (V) 1.0 T J=-55°C 0.9 0.8 T J=25°C 0.7 0.6 0.5 T J=175°C 0.4 0 20 40 60 80 100 DocID026910 Rev 3 120 ISD(A) 7/15 Test circuits 3 STH185N10F3-2 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform 8/15 DocID026910 Rev 3 Figure 18: Switching time waveform STH185N10F3-2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026910 Rev 3 9/15 Package information 4.1 STH185N10F3-2 H²PAK-2 package information Figure 19: H²PAK-2 package outline 10/15 DocID026910 Rev 3 STH185N10F3-2 Package information Table 8: H²PAK-2 package mechanical data mm Dim. Min. Typ. Max. A 4.30 4.70 A1 0.03 0.20 C 1.17 1.37 e 4.98 5.18 E 0.50 0.90 F 0.78 0.85 H 10.00 10.40 H1 7.40 L 15.30 L1 1.27 1.40 L2 4.93 5.23 L3 6.85 7.25 L4 1.5 1.7 - 7.80 15.80 M 2.6 2.9 R 0.20 0.60 V 0° 8° Figure 20: H²PAK-2 recommended footprint DocID026910 Rev 3 11/15 Package information 4.2 STH185N10F3-2 H²PAK packing information Figure 21: Tape outline Figure 22: Reel outline T REE L DIMENS IONS 40 mm min. Acc ess hole At slot location B D C N A Tape slot In core for Full radius At hub Tape start 12/15 G measured DocID026910 Rev 3 STH185N10F3-2 Package information Table 9: Tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID026910 Rev 3 Min. Max. 330 13.2 26.4 30.4 13/15 Revision history 5 STH185N10F3-2 Revision history Table 10: Document revision history Date Revision 23-Sep-2014 1 First version. 2 Updated Safe operating area. Updated H²PAK package information 02-Sep-2016 Changes Minor text changes. 06-Oct-2016 14/15 3 Updated Features. Updated Section 9.1: "H²PAK-2 package information". Minor text changes. DocID026910 Rev 3 STH185N10F3-2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID026910 Rev 3 15/15