STL24N60M2

STL24N60M2 N-channel 600 V, 0.186 Ω typ., 18 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2 Order code VDS@TJ max RDS(on) max. ID STL24N60M2 650 V 0.210 Ω 18 A     1 PowerFLAT™ 8x8 HV Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications  Switching applications Figure 1: Internal schematic diagram Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packing STL24N60M2 24N60M2 PowerFLAT™ 8x8 HV Tape and reel May 2016 DocID024777 Rev 3 This is information on a product in full production. 1/15 www.st.com Contents STL24N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT™ 8x8 HV package information .................................... 10 4.2 PowerFLAT™ 8x8 HV packing information ..................................... 12 Revision history ............................................................................ 14 DocID024777 Rev 3 STL24N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 25 V ID(1) Drain current (continuous) at TC = 25 °C 18 A ID(1) Drain current (continuous) at TC = 100 °C 12 A Drain current (pulsed) 72 A IDM(1)(2) PTOT (1) Total dissipation at TC = 25 °C 125 W dv/dt(3) Peak diode recovery voltage slope 15 V/ns dv/dt(4) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range -55 to 150 °C Tj Operating junction temperature range Notes: (1)the value is limited by package (2)Pulse (3)I SD (4)V width limited by safe operating area. ≤ 18 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. DS ≤ 480 V Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case max 1 °C/W Thermal resistance junction-pcb max 45 °C/W Notes: (1)When mounted on FR-4 board of inch², 2oz Cu. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 180 mJ DocID024777 Rev 3 3/15 Electrical characteristics 2 STL24N60M2 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V, TC = 125 °C(1) 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 9 A 0.186 0.210 Ω Min. Typ. Max. Unit 2 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance - 1060 - pF Coss Output capacitance - 55 - pF Crss Reverse transfer capacitance - 2.2 - pF Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 258 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 7 - Ω Qg Total gate charge - 29 - nC Qgs Gate-source charge - 6 - nC Qgd Gate-drain charge - 12 - nC VDS= 100 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 18 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 9 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load") and (Figure 19: "Switching time waveform") DocID024777 Rev 3 Min. Typ. Max. Unit - 14 - ns - 9 - ns - 60 - ns - 15 - ns STL24N60M2 Electrical characteristics Table 8: Source drain diode Symbol Parameter ISD(1) Source-drain current ISDM(1)(2) Source-drain current (pulsed) VSD (3) Forward on voltage Test conditions VGS = 0 V, ISD = 18 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Min. Typ. Max. Unit - 18 A - 72 A - 1.6 V - 332 ns - 4 µC - 24 A - 450 ns - 5.5 µC - 25 A Notes: (1)The value is limited by package. (2)Pulse width is limited by safe operating area (3)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID024777 Rev 3 5/15 Electrical characteristics 2.1 STL24N60M2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*RthJ-c δ= tp/Ƭ 0.01 Single pulse tp -2 10 -5 10 10 -4 10 -3 10 -2 Ƭ tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance R W VGS=10 A 0.194 0.192 0.190 0.188 0.186 0.184 0.182 0.180 0.178 0 6/15 DocID024777 Rev 3 2 4 6 8 10 12 14 16 ID(A) STL24N60M2 Electrical characteristics Figure 8: Capacitance variations AM15665v1 C (pF) Figure 9: Normalized gate threshold voltage vs temperature Ciss 1000 100 Coss 10 Crss 1 0.1 1 100 10 V DS(V) Figure 10: Normalized on-resistance vs temperature RDS(on) (norm) 2.5 Figure 11: Normalized V(BR)DSS vs temperature ID=9 A VGS=10 V 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -50 -25 0 25 50 75 100 125 TJ(°C) Figure 12: Output capacitance stored energy AM15669v1 Eoss(µJ) Figure 13: Source-drain diode forward characteristics 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 VDS(V) DocID024777 Rev 3 7/15 Test circuits 3 STL24N60M2 Test circuits Figure 15: Gate charge test circuit Figure 14: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G S L=100µH 3.3 µF B 25Ω L D + 1000 µF VD 2200 µF VDD VDD + G RG 3.3 µF ID S D.U.T. Vi GND1 D.U.T. GND2 Pw GND1 Figure 18: Unclamped inductive waveform 8/15 DocID024777 Rev 3 GND2 AM15858v1 Figure 19: Switching time waveform STL24N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID024777 Rev 3 9/15 Package information 4.1 STL24N60M2 PowerFLAT™ 8x8 HV package information Figure 20: PowerFLAT™ 8x8 HV package outline 8222871_Rev_3_ A 10/15 DocID024777 Rev 3 STL24N60M2 Package information Table 9: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 0.60 Figure 21: PowerFLAT™ 8x8 HV footprint All dimensions are in millimeters. DocID024777 Rev 3 11/15 Package information 4.2 STL24N60M2 PowerFLAT™ 8x8 HV packing information Figure 22: PowerFLAT™ 8x8 HV tape All dimensions are in millimeters. Figure 23: PowerFLAT™ 8x8 HV package orientation in carrier tape 12/15 DocID024777 Rev 3 STL24N60M2 Package information Figure 24: PowerFLAT™ 8x8 HV reel All dimensions are in millimeters. DocID024777 Rev 3 13/15 Revision history 5 STL24N60M2 Revision history Table 10: Document revision history Date Revision 11-Jun-2013 1 First release. 2 Modified: ID (at TC = 100 °C) value in Table 3. Modified: VSD max value, figures 3 and 11. Updated: Section 4: Package mechanical data – Minor text changes. 3 Updated features and description in cover page. Updated package silhouette and Figure 1: "Internal schematic diagram". Updated Section 4: "Test circuits" and Section 5.1: "PowerFLAT™ 8x8 HV package information". Minor text changes 28-Feb-2014 25-May-2016 14/15 Changes DocID024777 Rev 3 STL24N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID024777 Rev 3 15/15