STP60NS04ZB

STP60NS04ZB N-CHANNEL CLAMPED 10mΩ - 60A TO-220 FULLY PROTECTED MESH OVERLAY™ MOSFET TYPE STP60NS04ZB s s s s VDSS CLAMPED RDS(on) < 0.015 Ω ID 60 A TYPICAL RDS(on) = 0.010 Ω 100% AVALANCHE TESTED LOW CAPACITANCE AND GATE CHARGE 175°C MAXIMUM JUNCTION TEMPERATURE 1 3 2 DESCRIPTION This fully clamped MOSFET is produced by using the latest advanced Company’s Mesh Overlay process which is based on a novel strip layout. The inherent benefits of the new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions such as those encountered in the automotive environment .Any other application requiring extra ruggedness is also recommended. APPLICATIONS ABS,SOLENOID DRIVERS s MOTOR CONTROL s DC-DC CONVERTERS s TO-220 INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDS VDG VGS ID ID IDG IGS IDM ( ) PTOT VESD(G-S) VESD(G-D) VESD(D-S) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Gate Current (continuous) Gate Source Current (continuous) Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate-Source ESD(HBM-C=100 pF, R=1.5 KΩ) Gate-Drain ESD(HBM-C=100 pF, R=1.5 KΩ) Drain-Source ESD(HBM-C=100 pF, R=1.5 KΩ) Storage Temperature Max. Operating Junction Temperature Value CLAMPED CLAMPED CLAMPED 60 42 ± 50 ± 50 240 150 1 6 4 4 –65 to 175 Unit V V V A A mA mA A W W/°C kV kV kV °C (•)Pulse width limited by safe operating area November 2002 1/8 STP60NS04ZB THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1.0 62.5 300 °C/W °C/W °C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 30 V ) Max Value 60 400 Unit A mJ ELECTRICAL CHARACTERISTICS (TCASE = 25°C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS VGSS Parameter Clamped Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate-Source Breakdown Voltage Test Conditions ID = 1 mA, VGS = 0 -40 < Tj < 175 °C VDS = 16 V,Tj = 150 °C VDS = 16 V,Tj = 175 °C VGS = ±10 V,Tj = 175 °C VGS = ±16 V,Tj = 175 °C IGS = ±100 µA 18 Min. 33 50 100 50 150 Typ. Max. Unit V µA µA µA µA V ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 1 mA -40 < Tj < 150 °C VGS = 10 V, ID = 30 A VGS = 16 V, ID = 30 A Min. 1.7 Typ. 3 11 10 Max. 4.2 15 14 Unit V mΩ mΩ DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS =15 V ,ID = 30 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. 20 Typ. 40 1700 800 190 2100 1000 240 Max. Unit S pF pF pF 2/8 STP60NS04ZB ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Qg Qgs Qgd Parameter Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 18 V, ID = 60 A, VGS = 10 V Min. Typ. 48 13 16 Max. 62 Unit nC nC nC SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off Voltage Rise Time Fall Time Cross-over Time Test Conditions VCLAMP = 30 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V (see test circuit, Figure 3) Min. Typ. 60 45 100 Max. 75 60 130 Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60 A, VGS = 0 ISD = 60 A, di/dt = 100 A/µs VDD = 15 V, Tj = 150°C (see test circuit, Figure 5) 50 62 2.6 Test Conditions Min. Typ. Max. 60 240 1.5 Unit A A V ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STP60NS04ZB Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP60NS04ZB Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Zero Gate Voltage Drain Current vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STP60NS04ZB Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP60NS04ZB TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 D F1 G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/8 STP60NS04ZB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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