TS4872IJT

TS4872 RAIL TO RAIL INPUT/OUTPUT 1W AUDIO POWER AMPLIFIER WITH STANDBY MODE s OPERATING FROM VCC = 2.2V to 5.5V s RAIL TO RAIL INPUT/OUTPUT s 1W OUTPUT POWER @ Vcc=5V, THD=1%, f=1kHz, with 8Ω Load MODE (10nA) TS4872IJT - FLIP CHIP PIN CONNECTIONS (Top View) s ULTRA LOW CONSUMPTION IN STANDBY s 75dB PSRR @ 217Hz @ 5 & 2.6V s ULTRA LOW POP & CLICK s ULTRA LOW DISTORTION (0.05%) s UNITY GAIN STABLE s 8 X170µm BUMPS FLIP CHIP PACKAGE DESCRIPTION The TS4872 is an Audio Power Amplifier capable of delivering 1W of continuous RMS Ouput Power into 8Ω load @ 5V. This Audio Amplifier is exhibiting 0.1% distortion level (THD) from a 5V supply for a Pout = 250mW RMS. An external standby mode control reduces the supply current to less than 10nA. An internal shutdown protection is provided. The TS4872 has been designed for high quality audio applications such as mobile phones and to minimize the number of external components. The unity-gain stable amplifier can be configured by external gain setting resistors. APPLICATIONS TYPICAL APPLICATION SCHEMATIC 8 Vout1 7 Vin + 6 Vcc 5 STDBY Vout2 4 Vin GND BYPASS 1 2 3 Cfeed Rfeed Vcc 6 Audio Input Cin Vcc Cs s Mobile Phones (Cellular / Cordless) s PDAs s Laptop/Notebook computers s Portable Audio Devices ORDER CODE Part Number TS4872IJT Temperature Range -40, +85°C Package Marking J q YW4872 Rin 1 7 VinVin+ + Vout1 8 RL 8 Ohms Vcc 3 Rstb 5 Standby Bias GND TS4872 Bypass Av=-1 + Vout2 4 Cb 2 J = Flip Chip Package - only available in Tape & Reel (JT) October 2002 1/29 TS4872 ABSOLUTE MAXIMUM RATINGS Symbol VCC Vi Toper Tstg Tj Rthja Supply voltage Input Voltage 2) 1) Parameter Value 6 GND to VCC -40 to + 85 -65 to +150 150 200 Internally Limited 2 200 Class A 250 Unit V V °C °C °C °C/W kV V °C Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Flip Chip Thermal Resistance Junction to Ambient 3) Pd Power Dissipation ESD Human Body Model ESD Machine Model Latch-up Latch-up Immunity Lead Temperature (soldering, 10sec) 1. All voltages values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3V / G ND - 0.3V 3. Device is protected in case of over temperature by a thermal shutdown active @ 150°C OPERATING CONDITIONS Symbol VCC VICM Supply Voltage Common Mode Input Voltage Range VCC from 2.6V to 5V VCC < 2.6V Standby Voltage Input : Device ON Device OFF Load Resistor Flip Chip Thermal Resistance Junction to Ambient 1) Parameter Value 2.2 to 5.5 GND to VCC VCC / 2 GND ≤ VSTB ≤ 0.5V VCC - 0.5V ≤ VSTB ≤ VCC 4 - 32 95 Unit V VSTB RL Rthja V Ω °C/W 1. With Heat Sink Surface = 125mm 2 2/29 TS4872 ELECTRICAL CHARACTERISTICS VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio 2) f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, CL = 500pF Gain Bandwidth Product RL = 8Ω Parameter Min. Typ. 6 10 5 1 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV W % dB Degrees dB MHz 1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified) 3) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio 2) f = 217Hz, RL = 8Ω, RFeed = 22KΩs, Vripple = 100mV rms Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, CL = 500pF Gain Bandwidth Product RL = 8Ω Parameter Min. Typ. 5.5 10 5 450 0.1 68 70 20 2 Max. 8 1000 20 Unit mA nA mV mW % dB Degrees dB MHz 1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz 3 All electrical values are made by correlation between 2.6v and 5v measurements 3/29 TS4872 ELECTRICAL CHARACTERISTICS VCC = 2.6V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Parameter Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio 2) f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, CL = 500pF Gain Bandwidth Product RL = 8Ω Min. Typ. 5.5 10 5 260 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV mW % dB Degrees dB MHz 1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz VCC = 2.2V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Parameter Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio 2) f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 100mVpp Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, CL = 500pF Gain Bandwidth Product RL = 8Ω Min. Typ. 4.5 10 2 180 0.1 75 70 20 2 Max. Unit mA nA mV mW % dB Degrees dB MHz 1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz 4/29 TS4872 Components Rin Cin Rfeed Cs Cb Cfeed Rstb Gv Functional Description Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin)) Input coupling capacitor which blocks the DC voltage at the amplifier input terminal Feed back resistor which sets the closed loop gain in conjunction with Rin Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed)) Pull-up resistor which fixes the right supply level on the standby pin Closed loop gain in BTL configuration = 2 x (Rfeed / Rin) REMARKS 1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF. 2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way, the quiescent current remains the same. 3. The standby response time is about 1µs. 5/29 TS4872 Fig. 1 : Open Loop Frequency Response Fig. 2 : Open Loop Frequency Response 0 60 Gain Vcc = 5V RL = 8Ω Tamb = 25°C -20 -40 -60 Phase (Deg) 0 60 Gain Vcc = 5V ZL = 8Ω + 560pF Tamb = 25°C -20 -40 -60 Phase (Deg) 40 Gain (dB) 40 Phase Gain (dB) Phase 20 -80 -100 -120 -80 -100 -120 20 0 -140 -160 0 -140 -160 -20 -180 -200 -20 -180 -200 -40 0.3 1 10 100 Frequency (kHz) 1000 10000 -220 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 -220 Fig. 3 : Open Loop Frequency Response Fig. 4 : Open Loop Frequency Response 80 60 40 Gain Vcc = 3.3V RL = 8Ω Tamb = 25°C 0 -20 -40 -60 -80 80 60 40 Phase 20 0 -20 -40 0.3 Gain Vcc = 3.3V ZL = 8Ω + 560pF Tamb = 25°C 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 1 10 100 1000 Frequency (kHz) 10000 -240 Phase (Deg) Phase (Deg) Phase 20 0 -100 -120 -140 -160 -180 -200 -220 -240 -20 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 Fig. 5 : Open Loop Frequency Response Phase (Deg) Gain (dB) Fig. 6 : Open Loop Frequency Response Gain (dB) 80 60 40 Gain (dB) 0 Gain Vcc = 2.6V RL = 8Ω Tamb = 25°C -20 -40 -60 -80 Phase Phase (Deg) Gain (dB) 80 Gain 60 40 Phase 20 0 -20 -40 0.3 Vcc = 2.6V ZL = 8Ω + 560pF Tamb = 25°C 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 1 10 100 1000 Frequency (kHz) 10000 -240 -100 -120 -140 -160 -180 -200 -220 -240 20 0 -20 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 6/29 TS4872 Fig. 7 : Open Loop Frequency Response Fig. 8 : Open Loop Frequency Response 100 80 60 Gain Gain (dB) -80 Phase -100 -120 Phase (Deg) 100 80 60 Gain Gain (dB) -80 Phase -100 -120 -140 -160 Phase (Deg) 40 20 0 -20 -40 0.3 -140 -160 -180 Vcc = 5V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 -200 40 20 -180 0 -20 Vcc = 3.3V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -240 -220 -40 0.3 Fig. 9 : Open Loop Frequency Response 100 80 60 Gain Gain (dB) -80 Phase -100 -120 -140 -160 Phase (Deg) 40 20 -180 0 -20 -40 0.3 Vcc = 2.6V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -240 7/29 TS4872 Fig. 10 : Power Supply Rejection Ratio (PSRR) vs Power Supply -30 Rfeed = 22kΩ Cb = 1µF & 0.1µF Input = floating RL = 8Ω Tamb = 25°C Vcc=3.3V Ripple=100mVrms -60 Vcc=5V Ripple=200mVrms -70 Vcc=2.6V Ripple=200mVrms -80 10 100 1000 10000 Frequency (Hz) 100000 -70 -80 10 Cfeed=680pF Fig. 11 : Power Supply Rejection Ratio (PSRR) vs Feedback Capacitor -10 -20 -30 PSRR (dB) -40 PSRR (dB) -50 -40 -50 -60 Vcc = 5V Cb = 1µF & 0.1µF Rfeed = 22kΩ Rfeed = 22kΩ Vripple = 200mVms Input = floating RL = 8Ω Tamb = 25°C Cfeed=0 Cfeed=150pF Cfeed=330pF 100 1000 10000 Frequency (Hz) 100000 Fig. 12 : Power Supply Rejection Ratio (PSRR) vs Bypass Capacitor -10 -20 -30 PSRR (dB) Fig. 13 : Power Supply Rejection Ratio (PSRR) vs Input Capacitor -10 Cin=1µF Cin=330nF -20 Cin=220nF Cb=1µF Cb=10µF -40 Cb=47µF -50 -60 PSRR (dB) Vcc = 5 & 2.6V Rfeed = 22k Rin = 22k, Cin = 1µF Rg = 100Ω, RL = 8Ω Tamb = 25°C -30 Vcc = 5 & 2.6V Rfeed = 22k, Rin = 22k Cb = 1µF Rg = 100Ω, RL = 8Ω Tamb = 25°C -40 Cin=100nF -50 Cin=22nF -70 Cb=100µF -80 10 100 1000 Frequency (Hz) 10000 100000 -60 10 100 1000 Frequency (Hz) 10000 100000 Fig. 14 : Power Supply Rejection Ratio (PSRR) vs Feedback Resistor -10 -20 -30 PSRR (dB) -40 -50 -60 -70 Vcc = 5V Cb = 1µF & 0.1µF Vripple = 200mVrms Input = floating RL = 8Ω Tamb = 25°C Rfeed=110kΩ Rfeed=47kΩ Rfeed=22kΩ Rfeed=10kΩ -80 10 100 1000 10000 Frequency (Hz) 100000 8/29 TS4872 Fig. 15 : Pout @ THD + N = 1% vs Supply Voltage vs RL 1.4 Output power @ 10% THD + N (W) Output power @ 1% THD + N (W) Fig. 16 : Pout @ THD + N = 10% vs Supply Voltage vs RL 2.0 1.2 1.0 0.8 0.6 0.4 0.2 Gv = 2 & 10 Cb = 1µF F = 1kHz BW < 125kHz Tamb = 25°C 8Ω 6Ω 4Ω 16Ω 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 Gv = 2 & 10 Cb = 1µF F = 1kHz BW < 125kHz Tamb = 25°C 8Ω 4Ω 6Ω 16Ω 32Ω 0.0 2.5 3.0 3.5 Vcc (V) 32Ω 3.0 3.5 Vcc (V) 4.0 4.5 5.0 4.0 4.5 5.0 Fig. 17 : Power Dissipation vs Pout 1.4 Vcc=5V 1.2 F=1kHz THD+N 4.4ms). Increase Cin value increases the pop and click phenomena to an unpleasant sound at power supply ON and standby function ON/OFF. Why Cs is not important in pop and click consideration ? Hypothesis : • Cs = 100µF • Supply voltage = 5V • Supply voltage internal resistor = 0.1Ω • Supply current of the amplifier Icc = 6mA At power ON of the supply, the supply capacitor is charged through the internal power supply resistor. So, to reach 5V you need about five to ten times the charging time constant of Cs (τs = 0.1xCs (s)). Then, this time equal 50µs to 100µs 10kΩ. Let's take Rin = 10kΩ, then Rfeed = 28.25kΩ. We could use for Rfeed = 30kΩ in normalized value and the gain will be Gv = 6. In lower frequency we want 20 Hz (-3dB cut off frequency). Then 1 C IN = ----------------------------- = 795nF 2 π R inF C L So, we could use for Cin a 1µF capacitor value that gives 16Hz. In Higher frequency we want 20kHz (-3dB cut off frequency). The Gain Bandwidth Product of the TS4872 is 2MHz typical and doesn't change when the amplifier delivers power into the load. The first amplifier has a gain of Rfee d ----------------- = 3 R in and the theoretical value of the -3dB cut-off higher frequency is 2MHz/3 = 660kHz. We can keep this value or limit the bandwidth by adding a capacitor Cfeed, in parallel on Rfeed. 23/29 Now, we must consider the discharge time of Cb. At power OFF or standby ON, Cb is discharged by a 100kΩ resistor. So the discharge time is about τb Disch ≈ 3xCbx100kΩ (s). In the majority of application, Cb=1µF, then τbDisch≈300ms >> tdischCs. s Power amplifier design examples Given : • • • • • • Load impedance : 8Ω Output power @ 1% THD+N : 0.5W Input impedance : 10kΩ min. Input voltage peak to peak : 1Vpp Bandwidth frequency : 20Hz to 20kHz (0, -3dB) Ambient temperature max = 50°C TS4872 Then 1 C FE E D = -------------------------------------- = 265pF 2π R F EEDFC H So, we could use for Cfeed a 220pF capacitor value that gives 24kHz. Now, we can calculate the value of Cb with the formula τb = 50k ΩxCb >> τin = (Rin+Rfeed)xCin which permits to reduce the pop and click effects. Then Cb >> 0.8µF. We can choose for Cb a normalized value of 2.2µF that gives good results in THD+N and PSRR. In the following tables, you could find three another examples with values required for the demoboard. Remark : components with (*) marking are optional. Application n°1 : 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier. Components : Designator R1 R4 R6 R7 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 J1 U1 Part Type 22k / 0.125W 22k / 0.125W Short Cicuit 330k / 0.125W 470nF 100µF 100nF Short Circuit Short Circuit 1 µF 2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch SMB plug TS4872IJ R1 R2 R4 R6 R7 C2 C5 C6 C7 C9 J1 U1 Application n°2 : 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier. Components : Designator R1 R4 R6 R7 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 Part Type 110k / 0.125W 22k / 0.125W Short Cicuit 330k / 0.125W 470nF 100µF 100nF Short Circuit Short Circuit 1 µF 2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch SMB Plug TS4872IJ Application n°3 : 50Hz to 10kHz bandwidth and 10dB gain BTL power amplifier. Components : Designator Part Type 33k / 0.125W Short Circuit 22k / 0.125W Short Cicuit 330k / 0.125W 470pF 150nF 100µF 100nF Short Circuit 24/29 TS4872 Designator C10 C12 S1, S2, S6, S7 S8 J1 U1 Part Type Short Circuit 1 µF 2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch SMB Plug TS4872IJ S8 C6 C7 C9 C10 C12 Designator 100µF 100nF Part Type Short Circuit Short Circuit 1 µF 2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch SMB Plug TS4872IJ S1, S2, S6, S7 Application n°4 : Differential inputs BTL power amplifier. In this configuration, we need to place these components : R1, R4, R5, R6, R7, C4, C5, C12. We have also : R4 = R5, R1 = R6, C4 = C5. The gain of the amplifier is : G V D I FF R1 = 2 ------- (Pos. Input - Neg.Input) R4 J1, J3 U1 s Note on how to use the PSRR curves (page 8) We have finished a design and we have chosen the components : s Rin=Rfeed=22kΩ For a 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier you could follow the bill of material below. Components : Designator R1 R4 R5 R6 R7 C4 C5 Part Type 22k / 0.125W 22k / 0.125W 22k / 0.125W 22k / 0.125W 330k / 0.125W 470nF 470nF s Cin=100nF s Cb=1µF Now, on fig. 13, we can see the PSRR (input grounded) vs frequency curves. At 217Hz we have a PSRR value of -36dB. In reality we want a value about -70dB. So, we need a gain of 34dB ! Now, on fig. 12 we can see the effect of Cb on the PSRR (input grounded) vs. frequency. With Cb=100µF, we can reach the -70dB value. The process to obtain the final curve (Cb=100µF, Cin=100nF, Rin=Rfeed=22kΩ) is a simple transfer point by point on each frequency of the curve on fig. 13 to the curve on fig. 12. The measurement results is shown on figure 84. 25/29 TS4872 Fig. 84 : PSRR changes with Cb Fig. 85 : PSRR measurement schematic -30 Cin=100nF Cb=1µF -40 PSRR (dB) Vcc = 5 & 2.6V Rfeed = 22k, Rin = 22k Rg = 100Ω, RL = 8Ω Tamb = 25°C Rfeed Vripple Vcc 1 Rin Cin 7 VinVin+ + RL Av=-1 + Vout2 4 Vs+ 6 Vcc Vout1 8 Vs- -50 Cin=100nF Cb=100µF -60 3 Bypass Standby Bias GND -70 10 100 1000 Frequency (Hz) Rg 100 Ohms 5 10000 100000 Cb TS4872 2 s Note on PSRR measurement What is the PSRR ? The PSRR is the Power Supply Rejection Ratio. It’s a kind of SVR in a determined frequency range. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR ? For PSRR measurement schematic see figure 85 s Principle of operation • We fixed the DC voltage supply (Vcc) • We fixed the AC sinusoidal ripple voltage (Vripple) • No bypass capacitor Cs is used The PSRR value for each frequency is : PSRR ( d B ) = 20 x Log 10 R ms ( V r i p pl e ) -------------------------------------------Rms ( Vs + - Vs - ) Remark : The measure of the Rms voltage is not a Rms selective measure but a full range (2 Hz to 125 kHz) Rms measure. It means that we measure the effective Rms signal + the noise. 26/29 TS4872 TOP VIEW OF THE DAISY CHAIN MECHANICAL DATA ( all drawings dimensions are in millimeters ) 7 Vin + 6 Vcc 5 STDBY 8 Vout1 Vout2 4 1.52 Vin GND BYPASS 1 2 3.02 3 REMARKS Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested. ORDER CODE Part Number TSDC4872IJT Temperature Range -40, +85°C Package Marking J • DC01 27/29 TS4872 TAPE & REEL SPECIFICATION ( top view ) User direction of feed 7 6 5 8 XXX4872 4 1 2 3 7 6 5 8 XXX4872 4 1 2 3 28/29 TS4872 PIN OUT (top view) 7 Vin + MARKING (top view) 6 Vcc 5 STDBY 8 Vout1 Vout2 4 Vin GND BYPASS 1 2 3 s Balls are underneath PACKAGE MECHANICAL DATA FLIP CHIP - 8 BUMPS s Y : Year s W : Week with two digits s Example : 1254872 s s s s s Die size : (3.02mm±10%) x (1.52mm ±10%) Die height (including bumps) : 540µm ±50µm Bump height : 140µm ±15µm (i.e. bump diameter of 185µm ±15µm) Silicon thickness : 400µm±25µm Pitch: 500µm ±10µm and 750µm±10µm Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © http://www.st.com 29/29