TS4975EIJT

TS4975 Stereo Headphone Drive Amplifier with Digital Volume Control via I2C Bus ■ ■ ■ ■ ■ ■ ■ ■ ■ Operating from VCC = 2.5V to 5.5V I²C bus control interface 40mW output power @ VCC = 3.3V, THD = 1%, F = 1kHz, with 16Ω load Ultra-low consumption in stdby mode: 0.6µA Digital volume control range from 18dB to -34dB 14-step digital volume control 9 different output mode selections Pop & click noise reduction circuitry Flip-chip package, 12 x 300µm bumps (leadfree) Pin out (top view) TS4975EIJT - Flip Chip Description The TS4975 is a stereo audio headphone driver capable of delivering up to 102mW per channel of continuous average power into a 16Ω singleended load with 1% THD+N from a 5V power supply. The overall gain of these headphone drivers is controlled digitally by volume control registers programmed via the I2C interface, minimizing the number of external components needed. This device can also easily be driven by an MCU to select the output modes, through the I2C bus interface. A phantom ground configuration allows one to avoid using bulky capacitors on the outputs of the headphone amplifiers. The TS4975 is packaged in a 1.8mm X 2.3mm Flip Chip package, ideally suited for spaceconscious portable applications. It has also an internal protection mechanism. thermal shutdown OUT1 PHG1 PHG2 OUT2 IN1 VCC GND IN2 BYPASS SCL SDA ADD Applications ■ ■ ■ ■ Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices Order Codes Part Number TS4975EIJT Temperature Range -40, +85°C Package Flip-chip Packing Tape & Reel Marking A75 Rev 3 1/36 www.st.com 36 November 2005 Absolute Maximum Ratings TS4975 1 Absolute Maximum Ratings Table 1. Symbol VCC Vi Toper Tstg Tj R thja Pdiss ESD ESD Latch-up Key parameters and their absolute maximum ratings Parameter Supply voltage (1) Input Voltage (2) Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient (3) Power Dissipation Susceptibility - Human Body Model(5) Susceptibility - Machine Model (min. Value) Latch-up Immunity Lead Temperature (soldering, 10sec) Value 6 GND to VCC -40 to + 85 -65 to +150 150 200 Internally Limited(4) 2 200 200 260 kV V mA °C Unit V V °C °C °C °C/W 1. All voltages values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3. Device is protected in case of over temperature by a thermal shutdown active @ 150°C. 4. Exceeding the power derating curves during a long period, may involve abnormal operating condition. 5. Human body model, 100pF discharged through a 1.5kOhm resistor, into pin to VCC device. Table 2. Symbol VCC RL CL Toper R thja Operating conditions Parameter Supply Voltage Load Resistor Load Capacitor RL = 16 to 100Ω, RL > 100Ω, Operating Free Air Temperature Range Flip Chip Thermal Resistance Junction to Ambient Value 2.5 to 5.5v >16 Unit V Ω 400 100 -40 to +85 90 pF °C °C/W 2/36 TS4975 Typical Application Schematics 2 Typical Application Schematics Typical application schematics for the TS4975 are show in Figure 1, for a single-ended output configuration and in Figure 2, for a phantom ground output configuration. Figure 1. Single-ended configuration Vcc + Cb 1µF + Cs 1µF A1 Bias IN1 Pre-Amplifier OUT1 Amplifier Vcc Bypass B2 IN1 Cin1 A2 Cout1 RL = 16/32 Ohms IN1 OUT1 A3 + + 1k 330nF PHG1 Amplifier 220µF PHG1 Mode Select PHG2 Amplifier B3 PHG2 C3 IN2 Pre-Amplifier OUT2 Amplifier IN2 Cin2 D2 Cout2 RL = 16/32 Ohms IN2 OUT2 D3 + + 1k 330nF 220µF Volume control GND ADD I2C SCL SDA TS4975 D1 B1 C2 ADD SCL SDA C1 3/36 Typical Application Schematics Figure 2. Phantom ground output configuration Vcc TS4975 + Cb 1µF + Cs 1µF A1 Bypass Bias IN1 Pre-Amplifier OUT1 Amplifier Vcc B2 RL = 16/32 Ohms A3 IN1 Cin1 A2 IN1 OUT1 + 330nF PHG1 Amplifier PHG1 Mode Select PHG2 Amplifier B3 PHG2 C3 IN2 Pre-Amplifier OUT2 Amplifier RL = 16/32 Ohms D3 IN2 Cin2 D2 IN2 OUT2 330nF + Volume control GND ADD I2C SCL SDA TS4975 D1 B1 C2 ADD SCL SDA 4/36 C1 TS4975 Electrical Characteristics 3 Electrical Characteristics Table 3. Symbol VIL VIH FSCL Vol Ii Electrical characteristics for the I²C interface Parameter Maximum Low level Input Voltage on pins SDA, SCL, VADD Minimum High Level Input Voltage on pins SDA, SCL, VADD SCL Maximum clock Frequency Max Low Level Output Voltage, SDA pin, Isink = 3mA Max Input current on SDA, SCL(1) from 0.1 VCC to 0.9 VCC Value 0.3 VCC 0.7 VCC 400 0.4 10 Unit V V kHz V µA 1. SCL and SDA are CMOS inputs. The nominal input current is about few pA and not 10uA. 10µA refer to the I2C bus specification. Table 4. Output noise (all inputs grounded) Unweighted Filter from VCC = 2.5V to 5V Weighted Filter (A) from VCC = 2.5V to 5V 23µVrms 45µVrms 23µVrms 45µVrms SE, G = +2dB SE, G = +18dB PHG, G = +2dB PHG, G = +18dB 34µVrms 67µVrms 34µVrms 67µVrms 5/36 Electrical Characteristics Table 5. Symbol TS4975 VCC = +2.5 V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Conditions No input signal, no load, Single-ended, Mode 1-4 No input signal, no load, Single-ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Min. Typ. 3 2 4.6 3.6 0.6 5 15 11 15 11 21 13 mW 21 13 0.3 0.3 % 0.3 0.3 Max. 4.2 2.8 mA 6.5 5.3 2 50 µA mV Unit ICC Supply Current ISTBY Voo Standby Current Output Offset Voltage SCL and SDA at VCC level, No input signal No input signal, RL = 32Ω, Phantom Ground Single-ended, THD+N = 1% Max, F = 1kHz, RL = 16Ω Single-ended, THD+N = 1% Max,F = 1kHz, RL = 32Ω Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 16Ω Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 32Ω Single-ended, AV = 2dB, RL = 32Ω, Pout = 10 mW, 20Hz < F < 20kHz, Single-ended, AV = 2dB, RL = 16Ω, Pout = 15 mW, 20Hz < F < 20kHz Phantom Ground, AV = 2dB, RL = 32Ω, Pout = 10 mW, 20Hz < F < 20kHz Phantom GroundAV = 2dB, RL = 16Ω, Pout = 15 mW, 20Hz < F < 20kHz Single-ended Output referenced to Phantom Ground F = 217Hz, RL = 16Ω, AV = 2dB Vripple = 200mV pp, Input Grounded, Cb = 1µF Single-ended Output referenced to Ground, F = 217Hz, RL = 16Ω, AV = 2dB Vripple = 200mV pp, Input Grounded, Cb = 1µF Pout Output Power (per channel) THD + N Total Harmonic Distortion + Noise 60 PSRR Power Supply Rejection Ratio(1) 60 dB 6/36 TS4975 Table 5. Symbol Electrical Characteristics VCC = +2.5 V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Conditions RL = 32Ω, AV = 2dB with Single-ended F = 1kHZ, Pout = 10mW RL = 32Ω, AV = 2dB with Single-ended F = 20Hz to 20kHz, Pout = 10mW RL = 32Ω, AV = 2dB with Phantom Ground, F = 1kHZ, Pout = 10mW RL = 32Ω, AV = 2dB with Phantom Ground, F = 20Hz to 20kHz, Pout = 10mW AV = 2dB, RL = 32Ω, Pout = 12mW Single-Ended AV = 2dB, RL = 32Ω, Pout = 12mW Phantom Ground Min. Typ. 103 Max. Unit 75 dB 69 69 88 dB 88 23 µVrms 23 -34 4 -1 +1 30 110 1 34.5 180 +18 dB dB dB kΩ ms µs Crosstalk Channel Separation SNR Signal to Noise Ratio A-Weighted ONoise G Output Noise Voltage, AV = 2dB, Single-ended A-Weighted AV = 2dB, Phantom Ground Digital Gain Range Digital Gain Stepsize Gain Error Tolerance In1 & In2 to Out1 & Out2 Zin twu tws In1 & In2 Input Impedance Wake up time Standby time All gain settings Cb = 1µF 25.5 1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217Hz 7/36 Electrical Characteristics Table 6. Symbol TS4975 VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Conditions No input signal, no load, Single-ended, Mode 1-4 No input signal, no load, Single-ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Min. Typ. 3 2 4.6 3.6 0.6 5 34 24 34 24 40 26 mW 40 26 0.3 0.3 % 0.3 0.3 Max. 4.2 2.8 mA 6.5 5.3 2 50 µA mV Unit ICC Supply Current ISTBY Voo Standby Current Output Offset Voltage SCL and SDA at VCC level, No input signal No input signal, RL = 32Ω, Phantom Ground Single-ended, THD+N = 1% Max, F = 1kHz, RL = 16Ω Pout Output Power (per channel) Single-ended, THD+N = 1% Max,F = 1kHz, RL = 32Ω Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 16Ω Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 32Ω Single-ended, AV = 2dB, RL = 32Ω, Pout = 20 mW, 20Hz < F < 20kHz, Single-ended, AV = 2dB, RL = 16Ω, Pout = 30 mW, 20Hz < F < 20kHz Phantom Ground, AV = 2dB, RL = 32Ω, Pout = 20 mW, 20Hz < F < 20kHz Phantom GroundAV = 2dB, R L = 16Ω, Pout = 30 mW, 20Hz < F < 20kHz Single-ended Output referenced to Phantom Ground F = 217Hz, RL = 16Ω, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1µF Single-ended Output referenced to Ground, F = 217Hz, RL = 16Ω, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1µF THD + N Total Harmonic Distortion + Noise 61 PSRR Power Supply Rejection Ratio(1) dB 61 8/36 TS4975 Table 6. Symbol Electrical Characteristics VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Conditions RL = 32Ω, AV = 2dB with Single-ended F = 1kHZ, Pout = 20mW RL = 32Ω, AV = 2dB with Single-ended F = 20Hz to 20kHz, Pout = 20mW RL = 32Ω, AV = 2dB with Phantom Ground, F = 1kHZ, Pout = 20mW RL = 32Ω, AV = 2dB with Phantom Ground, F = 20Hz to 20kHz, Pout = 20mW AV = 2dB, RL = 32Ω, Pout = 25mW Single-Ended AV = 2dB, RL = 32Ω, Pout = 25mW Phantom Ground Min. Typ. 103 75 dB 69 69 90 dB 90 23 23 -34 4 -1 All gain settings Cb=1µF 25.5 30 90 1 +1 34.5 156 +18 dB dB dB kΩ ms µs Max. Unit Crosstalk Channel Separation SNR Signal To Noise Ratio ONoise G Output Noise Voltage, AV = 2dB, Single-ended A-Weighted AV = 2dB, Phantom Ground Digital Gain Range Digital Gain Step size Gain Error Tolerance In1 & In2 Input Impedance Wake up time Standby time In1 & In2 to Out1 & Out2 µVrms Zin twu tws 1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217Hz 9/36 Electrical Characteristics Table 7. Symbol TS4975 VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Conditions No input signal, no load, Single-ended, Mode 1-4 No input signal, no load, Single-ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Min. Typ. 3 2 4.6 3.6 0.6 5 92 59 92 59 102 64 mW 98 63 0.3 0.3 % 0.3 Max. 4.2 2.8 mA 6.5 5.3 2 50 µA mV Unit ICC Supply Current ISTBY Voo Standby Current Output Offset Voltage SCL and SDA at VCC level, No input signal No input signal, RL = 32Ω, Phantom Ground Single-ended, THD+N = 1% Max, F = 1kHz, RL = 16Ω Single-ended, THD+N = 1% Max,F = 1kHz, RL = 32Ω Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 16Ω Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 32Ω Single-ended, AV = 2dB, RL = 32Ω, Pout = 50 mW, 20Hz < F < 20kHz, Single-ended, AV = 2dB, RL = 16Ω, Pout = 80 mW, 20Hz < F < 20kHz Phantom Ground, AV = 2dB, RL = 32Ω, Pout = 50 mW, 20Hz < F < 20kHz Phantom GroundAV = 2dB, RL = 16Ω, Pout = 80 mW, 20Hz < F < 20kHz Single-ended Output referenced to Phantom Ground F = 217Hz, RL = 16Ω, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1µF Single-ended Output referenced to Ground F = 217Hz, RL = 16Ω, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1µF Pout Output Power (per channel) Total Harmonic THD + N Distortion + Noise 0.3 63 PSRR Power Supply Rejection Ratio(1) dB 63 10/36 TS4975 Table 7. Symbol Electrical Characteristics VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Conditions RL = 32Ω, AV = 2dB with Single-ended F = 1kHZ, Pout = 50mW RL = 32Ω, AV = 2dB with Single-ended F = 20Hz to 20kHz, Pout = 50mW RL = 32Ω, AV = 2dB with Phantom Ground, F = 1kHZ, Pout = 50mW RL = 32Ω, AV = 2dB with Phantom Ground, F = 20Hz to 20kHz, Pout = 50mW AV = 2dB, RL = 32Ω, Pout = 62mW Single-Ended AV = 2dB, RL = 32Ω, Pout = 62mW Phantom Ground AV = 2dB, Single-ended AV = 2dB, Phantom Ground In1 & In2 to Out1 & Out2 -34 4 -1 All gain settings Cb=1µF 25.5 30 80 1 +1 34.5 144 Min. Typ. 103 Max. Unit 75 dB 69 Crosstalk Channel Separation 69 95 dB 95 23 µVrms 23 +18 dB dB dB kΩ ms µs SNR Signal To Noise Ratio, A-Weighted ONoise G Output Noise Voltage, A-Weighted Digital Gain Range Digital Gain Step size Gain Error Tolerance Zin twu tws In1 & In2 Input Impedance Wake up time Standby time 1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple )). Vripple is an added sinus signal to VCC @ F = 217Hz 11/36 Electrical Characteristics Figure 3. THD+N vs. output power Figure 4. THD+N vs. output power TS4975 10 1 THD + N (%) RL = 8 Ω Out. mode 1 - 8 SE, G = +2dB BW < 125kHz Tamb = 25 °C 10 Vcc=2.5V F=20kHz 1 THD + N (%) Vcc=2.5V F=1kHz RL = 8 Ω Out. mode 1 - 8 SE, G = +18dB BW < 125kHz Tamb = 25 °C Vcc=3.3V F=20kHz Vcc=2.5V F=20kHz 0.1 0.1 Vcc=3.3V F=1kHz Vcc=2.5V F=1kHz Vcc=5V F=20kHz 0.01 Output power (W) 0.01 Vcc=3.3V F=1kHz Vcc=3.3V F=20kHz Vcc=5V F=20kHz Vcc=5V F=1kHz 0.01 Vcc=5V F=1kHz 1E-3 1E-3 0.01 Output power (W) 0.1 1E-3 1E-3 0.1 Figure 5. THD+N vs. output power Figure 6. THD+N vs. output power 10 1 THD + N (%) RL = 16 Ω Out. mode 1 - 8 SE, G = +2dB BW < 125kHz Tamb = 25 °C 10 Vcc=2.5V F=20kHz 1 THD + N (%) Vcc=2.5V F=1kHz RL = 16 Ω Out. mode 1 - 8 SE, G = +18dB BW < 125kHz Tamb = 25 °C Vcc=3.3V F=20kHz Vcc=2.5V F=1kHz 0.1 0.1 0.01 Vcc=3.3V F=1kHz Vcc=3.3V F=20kHz Vcc=5V F=20kHz Vcc=5V F=1kHz 0.01 Vcc=2.5V F=20kHz Vcc=3.3V F=1kHz Vcc=5V F=20kHz Vcc=5V F=1kHz 1E-3 1E-3 0.01 Output power (W) 0.1 1E-3 1E-3 0.01 Output power (W) 0.1 Figure 7. THD+N vs. output power Figure 8. THD+N vs. output power 10 1 THD + N (%) RL = 32 Ω Out. mode 1 - 8 SE, G = +2dB BW < 125kHz Tamb = 25 °C 10 Vcc=2.5V F=20kHz 1 THD + N (%) RL = 32 Ω Out. mode 1 - 8 SE, G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V F=20kHz 0.1 Vcc=5V F=20kHz Vcc=3.3V F=20kHz Vcc=3.3V F=1kHz 0.01 Output power (W) 0.1 Vcc=5V F=20kHz Vcc=2.5V F=1kHz Vcc=3.3V F=20kHz 0.01 Output power (W) 0.01 Vcc=2.5V F=1kHz 0.01 Vcc=5V F=1kHz 0.1 1E-3 1E-3 Vcc=3.3V F=1kHz Vcc=5V F=1kHz 0.1 1E-3 1E-3 12/36 TS4975 Figure 9. THD+N vs. output power Electrical Characteristics Figure 10. THD+N vs. output power 10 1 THD + N (%) RL = 8 Ω Out. mode 1 - 8 PHG, G = +2dB BW < 125kHz Tamb = 25 °C 10 Vcc=2.5V F=20kHz Vcc=2.5V F=1kHz THD + N (%) Vcc=2.5V F=1kHz 1 Vcc=2.5V F=20kHz Vcc=3.3V F=20kHz 0.1 0.1 Vcc=3.3V F=1kHz Vcc=5V F=20kHz 0.01 Output power (W) 0.01 Vcc=3.3V F=1kHz Vcc=3.3V F=20kHz Vcc=5V F=20kHz Vcc=5V F=1kHz 0.01 RL = 8 Ω Out. mode 1 - 8 SE, G = +18dB BW < 125kHz Tamb = 25 °C Vcc=5V F=1kHz 1E-3 1E-3 0.01 Output power (W) 0.1 1E-3 1E-3 0.1 Figure 11. THD+N vs. output power Figure 12. THD+N vs. output power 10 RL = 16 Ω Out. mode 1 - 8 PHG, G = +2dB 1 BW < 125kHz Tamb = 25 °C 10 Vcc=2.5V F=20kHz 1 THD + N (%) Vcc=3.3V F=20kHz Vcc=2.5V F=1kHz Vcc=2.5V F=20kHz THD + N (%) Vcc=2.5V F=1kHz 0.1 0.1 Vcc=3.3V F=1kHz Vcc=5V F=20kHz 0.01 Output power (W) 0.01 Vcc=3.3V F=1kHz Vcc=3.3V F=20kHz Vcc=5V F=20kHz Vcc=5V F=1kHz 0.01 RL = 16 Ω Out. mode 1 - 8 PHG, G = +18dB BW < 125kHz Tamb = 25°C Vcc=5V F=1kHz 1E-3 1E-3 0.01 Output power (W) 0.1 1E-3 1E-3 0.1 Figure 13. THD+N vs. output power Figure 14. THD+N vs. output power 10 1 THD + N (%) RL = 32 Ω Out. mode 1 - 8 PHG, G = +2dB BW < 125kHz Tamb = 25 °C 10 Vcc=2.5V F=20kHz 1 THD + N (%) RL = 32 Ω Out. mode 1 - 8 PHG, G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V F=20kHz 0.1 Vcc=5V F=20kHz 0.01 Vcc=2.5V F=1kHz Vcc=3.3V F=20kHz 0.01 Output power (W) 0.1 Vcc=5V F=20kHz Vcc=3.3V F=20kHz Vcc=3.3V F=1kHz 0.01 Output power (W) 0.01 Vcc=3.3V F=1kHz Vcc=5V F=1kHz 0.1 Vcc=2.5V F=1kHz Vcc=5V F=1kHz 0.1 1E-3 1E-3 1E-3 1E-3 13/36 Electrical Characteristics Figure 15. THD+N vs. frequency Figure 16. THD+N vs. frequency TS4975 10 THD + N (%) Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW Vcc=5V P=110mW THD + N (%) RL = 8Ω Output mode 1 - 8 Single Ended G = +2dB 1 BW < 125kHz Tamb = 25 °C 10 1 RL = 8Ω Output mode 1 - 8 Single Ended G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=20mW Vcc=3.3V P=40mW Vcc=5V P=110mW 0.1 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 Figure 17. THD+N vs. frequency Figure 18. THD+N vs. frequency 10 RL = 16 Ω Output mode 1 - 8 Single Ended G = +2dB BW < 125kHz Tamb = 25°C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW Vcc=5V P=80mW 10 RL = 16 Ω Output mode 1 - 8 Single Ended G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW THD + N (%) THD + N (%) 1 1 Vcc=5V P=80mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 Figure 19. THD+N vs. frequency Figure 20. THD+N vs. frequency 10 RL = 32 Ω Output mode 1 - 8 Single Ended G = +2dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=10mW 0.1 Vcc=3.3V P=20mW Vcc=5V P=50mW 10 RL = 32 Ω Output mode 1 - 8 Single Ended G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=10mW 0.1 Vcc=3.3V P=20mW Vcc=5V P=50mW THD + N (%) 0.01 THD + N (%) 1 1 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 14/36 TS4975 Figure 21. THD+N vs. frequency Electrical Characteristics Figure 22. THD+N vs. frequency 10 THD + N (%) Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW Vcc=5V P=110mW THD + N (%) 1 RL = 8 Ω Output mode 1 - 8 Phantom Ground G = +2dB BW < 125kHz Tamb = 25°C 10 RL = 8 Ω Output mode 1 - 8 Phantom Ground G = +18dB BW < 125kHz Tamb = 25°C Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW 1 Vcc=5V P=110mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 Figure 23. THD+N vs. frequency Figure 24. THD+N vs. frequency 10 RL = 16 Ω Output mode 1 - 8 Phantom Ground G = +2dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW Vcc=5V P=80mW 10 RL = 16 Ω Output mode 1 - 8 Phantom Ground G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW THD + N (%) THD + N (%) 1 1 Vcc=5V P=80mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 Figure 25. THD+N vs. frequency Figure 26. THD+N vs. frequency 10 RL = 32 Ω Output mode 1 - 8 Phantom Ground G = +2dB BW < 125kHz Tamb = 25°C Vcc=2.5V P=10mW 0.1 Vcc=3.3V P=20mW Vcc=5V P=50mW 10 RL = 32 Ω Output mode 1 - 8 Phantom Ground G = +18dB BW < 125kHz Tamb = 25 °C Vcc=2.5V P=10mW Vcc=3.3V P=20mW Vcc=5V P=50mW THD + N (%) THD + N (%) 1 1 0.1 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 15/36 Electrical Characteristics Figure 27. Output power vs. power supply voltage (each channel) TS4975 Figure 28. Output power vs. power supply voltage (each channel) 180 Output power at 10% THD + N (mW) Output power at 1% THD + N (mW) 220 F = 1kHz Output mode 1 - 8 Single Ended BW < 125 kHz Tamb = 25 °C 32 Ω 200 180 160 140 120 100 80 60 40 20 0 2.5 3.0 3.5 4.0 V cc (V) 160 140 120 100 80 60 40 20 8Ω 16 Ω F = 1kHz Output mode 1 - 8 Single Ended BW < 125 kHz Tamb = 25 °C 32 Ω 8Ω 16 Ω 64 Ω 3.0 3.5 4.0 V cc (V) 64 Ω 4.5 5.0 5.5 0 2.5 4.5 5.0 5.5 Figure 29. Output power vs. power supply voltage (each channel) Figure 30. Output power vs. power supply voltage (each channel) 180 Output power at 1% THD + N (mW) Output power at 10% THD + N (mW) 160 140 120 100 80 60 40 20 F = 1kHz Output mode 1 - 8 Phantom Ground BW < 125 kHz Tamb = 25 °C 32Ω 220 8Ω 16 Ω 200 180 160 140 120 100 80 60 40 20 F = 1kHz Output mode 1 - 8 Phantom Ground BW < 125 kHz Tamb = 25 °C 32 Ω 8Ω 16 Ω 64 Ω 3.0 3.5 4.0 V cc (V) 64 Ω 3.0 3.5 4.0 V cc (V) 0 2.5 4.5 5.0 5.5 0 2.5 4.5 5.0 5.5 16/36 TS4975 Figure 31. PSSR vs. frequency Electrical Characteristics Figure 32. PSSR vs. frequency 0 -10 -20 -30 PSRR (dB) 0 Vcc = 2.5V RL ≥ 16 Ω Output mode 1 - 8 SE, Inp. grounded Vripple = 200mVpp G=+10dB -10 -20 G=+18dB PSRR (dB) -30 -40 -50 -60 -70 Vcc = 2.5V RL ≥ 1 6Ω Output mode 1 - 8 PHG, Inp. grounded Vripple = 200mVpp G=+10dB G=+18dB G=+2dB -40 -50 -60 -70 -80 -90 G=-2dB -100 20 100 1000 Frequency (Hz) G=+2dB G=-10dB G=-34dB -80 -90 G=-2dB 100 G=-10dB 1000 Frequency (Hz) G=-34dB 10000 10000 -100 20 Figure 33. PSSR vs. frequency Figure 34. PSSR vs. frequency 0 -10 -20 -30 PSRR (dB) 0 Vcc = 3.3V RL ≥ 16 Ω Output mode 1 - 8 SE, Inp. grounded Vripple = 200mVpp G=+10dB -10 -20 G=+18dB PSRR (dB) -30 -40 -50 -60 -70 -80 Vcc = 3.3V RL ≥ 1 6Ω Output mode 1 - 8 PHG, Inp. grounded Vripple = 200mVpp G=+10dB G=+18dB G=+2dB -40 -50 -60 -70 -80 G=-10dB -90 G=-2dB -100 20 100 1000 Frequency (Hz) G=+2dB G=-34dB 10000 -90 -100 20 100 G=-2dB G=-10dB 1000 G=-34dB 10000 Frequency (Hz) Figure 35. PSSR vs. frequency Figure 36. PSSR vs. frequency 0 -10 -20 -30 PSRR (dB) 0 Vcc = 5V RL ≥ 1 6 Ω Output mode 1 - 8 SE, Inp. grounded Vripple = 200mVpp G=+10dB -10 -20 G=+18dB PSRR (dB) -30 -40 -50 -60 -70 Vcc = 5V RL ≥ 16 Ω Output mode 1 - 8 PHG, Inp. grounded Vripple = 200mVpp G=+10dB G=+18dB G=+2dB -40 -50 -60 -70 -80 -90 G=-2dB -100 20 100 1000 Frequency (Hz) G=+2dB G=-10dB G=-34dB 10000 -80 -90 -100 20 100 G=-2dB G=-10dB 1000 Frequency (Hz) G=-34dB 10000 17/36 Electrical Characteristics Figure 37. Crosstalk vs. frequency Figure 38. Crosstalk vs. frequency TS4975 0 Vcc = 2.5V Output mode 1 -20 Single Ended G = +2dB -40 Tamb = 25 °C -60 -80 -100 -120 RL=32Ω Po=10mW RL=16 Ω Po=15mW 0 -10 Crosstalk Level (dB) Crosstalk Level (dB) -20 -30 -40 -50 -60 -70 Vcc = 2.5V Output mode 1 Phantom Ground G = +2dB Tamb = 25 °C RL=32 Ω Po=10mW RL=16 Ω Po=15mW 100 1000 Frequency (Hz) 10000 -80 100 1000 Frequency (Hz) 10000 Figure 39. Crosstalk vs. frequency Figure 40. Crosstalk vs. frequency 0 -20 Crosstalk Level (dB) 0 Vcc = 3.3V Output mode 1 Single Ended G = +2dB Tamb = 25 °C RL=16 Ω Po=30mW RL=32Ω Po=20mW -10 Crosstalk Level (dB) -20 -30 -40 -50 -60 -70 -40 -60 -80 -100 -120 Vcc = 3.3V Output mode 1 Phantom Ground G = +2dB Tamb = 25 °C RL=32 Ω Po=20mW RL=16 Ω Po=30mW 100 1000 Frequency (Hz) 10000 -80 100 1000 Frequency (Hz) 10000 Figure 41. Crosstalk vs. frequency Figure 42. Crosstalk vs. frequency 0 Vcc = 5V Output mode 1 -20 Single Ended G = +2dB -40 Tamb = 25 °C -60 -80 -100 -120 RL=32Ω Po=50mW RL=16 Ω Po=80mW 0 -10 Crosstalk Level (dB) Crosstalk Level (dB) -20 -30 -40 -50 -60 -70 Vcc = 5V Output mode 1 Phantom Ground G = +2dB Tamb = 25 °C RL=32 Ω Po=50mW RL=16 Ω Po=80mW 100 1000 Frequency (Hz) 10000 -80 100 1000 Frequency (Hz) 10000 18/36 TS4975 Figure 43. SNR vs. power supply voltage Electrical Characteristics Figure 44. SNR vs. power supply voltage 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 SNR (dB) 2.5 3.3 Vcc (V) 5 SNR (dB) R L = 32 Ω R L = 16 Ω Out. mode 1 - 8 SE, G = +2dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25 °C 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 R L = 32 Ω R L = 16 Ω Out. mode 1 - 8 SE, G = +2dB Weighted filter type A THD+N < 0.5% Tamb = 25 °C 2.5 3.3 Vcc (V) 5 Figure 45. SNR vs. power supply voltage Figure 46. SNR vs. power supply voltage 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 SNR (dB) 2.5 3.3 Vcc (V) 5 SNR (dB) RL = 32 Ω RL = 16 Ω Out. mode 1 - 8 SE, G = +18dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25°C 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 RL = 32 Ω RL = 16 Ω Out. mode 1 - 8 SE, G = +18dB Weighted filter type A THD+N < 0.5% Tamb = 25°C 2.5 3.3 Vcc (V) 5 Figure 47. SNR vs. power supply voltage Figure 48. SNR vs. power supply voltage 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 SNR (dB) 2.5 3.3 Vcc (V) 5 SNR (dB) R L = 32 Ω R L = 16 Ω Out. mode 1 - 8 PHG, G = +2dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25 °C 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 R L = 32Ω R L = 16Ω Out. mode 1 - 8 PHG, G = +2dB Weighted filter type A THD+N < 0.5% Tamb = 25 °C 2.5 3.3 Vcc (V) 5 19/36 Electrical Characteristics Figure 49. SNR vs. power supply voltage 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 TS4975 Figure 50. SNR vs. power supply voltage 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 SNR (dB) 2.5 3.3 Vcc (V) 5 SNR (dB) RL = 32 Ω RL = 16 Ω Out. mode 1 - 8 PHG, G = +18dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% T amb = 25°C RL = 32 Ω RL = 16 Ω Out. mode 1 - 8 PHG, G = +18dB Weighted filter type A THD+N < 0.5% Tamb = 25°C 2.5 3.3 Vcc (V) 5 Figure 51. Frequency response Figure 52. Current consumption vs. power supply voltage 6 5 20 18 16 14 Output level (dB) No loads Tamb = 25 °C PHG, Out. Mode 1, 2, 3, 4 Vcc = 5V, 3.3V, 2.5V G = +18dB 12 10 8 6 4 2 0 20 100 1000 Frequency (Hz) Vcc = 5V, 3.3V, 2.5V G = +2dB Output mode 1 - 8 RL = 32, 16Ω Cin = 330nF SE, PHG BW < 125kHz Tamb = 25 °C 4 Icc (mA) PHG, Out. mode 5, 6, 7, 8 3 2 1 SE, Out. mode 5, 6, 7, 8 0 Reset state SE, Out. mode 1, 2, 3, 4 10000 0 1 2 3 Vcc (V) 4 5 Figure 53. 3dB lower cut off frequency vs. input capacitance Figure 54. 3dB lower cut off frequency vs. output capacitance 100 All gain setting Tamb=25 °C Low -3 dB Cut Off frequency (Hz) Low -3dB Cut Off Frequency (Hz) 100 All gain setting Tamb = 25°C Minimum Input Impedance 10 10 Typical Input Impedance Maximum Input Impedance RL=16 Ω RL=32 Ω 0.1 Input Capacitor Cin ( µF) 1 1 100 1000 Output capacitor Cout ( µF) 20/36 TS4975 Electrical Characteristics Figure 55. Power dissipation vs. output power Figure 56. Power dissipation vs. output power (one channel (one channel 70 Vcc = 2.5V F = 1kHz 60 THD+N < 1% 50 40 30 20 RL=32 Ω , SE 10 0 Power Dissipation (mW) Power Dissipation (mW) 120 Vcc = 3.3V 110 F = 1kHz 100 THD+N < 1% 90 80 70 60 50 40 30 20 10 0 RL=32 Ω , SE RL=16 Ω , SE RL=16 Ω , P HG RL=32Ω , PHG RL=16 Ω , SE RL=16 Ω , PHG RL=32 Ω , PHG 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 45 Output Power (mW) Output Power (mW) Figure 57. Power dissipation vs. output power Figure 58. Power derating curves (one channel 280 Vcc = 5V 260 F = 1kHz 240 THD+N < 1% 220 200 180 160 140 120 100 80 60 40 20 0 0 10 20 30 Flip-Chip Package Power Dissipation (W) 1.4 1.2 1.0 0.8 0.6 0.4 No Heat sink 0.2 0.0 Heat sink surface = 125mm 2 Power Dissipation (mW) RL=16Ω , PHG RL=32 Ω , PHG RL=16 Ω , SE RL=32 Ω , SE 40 50 60 70 80 90 100 110 0 25 50 75 100 125 150 Output Power (mW) Ambiant Temperature (°C) 21/36 Application Information TS4975 4 Application Information The TS4975 integrates 2 monolithic power amplifiers. The amplifier output can be configured as either SE (single-ended) capacitively-coupled output or PHG (phantom ground) output. Figure 1 on page 3 and Figure 2 on page 4 show schemes of these two configurations and Section 4.2: Output configuration describes these configurations. This chapter gives information on how to configure the TS4975 in application. 4.1 I²C bus interface The TS4975 uses a serial bus, which conforms to the I²C protocol (the TS4975 must be powered when it is connected to I²C bus), to control the chip’s functions with two wires: Clock and Data. The Clock line and the Data line are bi-directional (open-collector) with an external chip pull-up resistor (typically 10 kOhm). The maximum clock frequency in Fast-mode specified by the I²C standard is 400kHz, which TS4975 supports. In this application, the TS4975 is always the slave device and the controlling micro controller MCU is the master device. The ADD pin is allows one to set one of two possible 7-bit device addresses. This setting is needed for when a number of chips are connected to the same bus (for example two TS4975 devices), to avoid address conflicts. The two possible TS4975 addresses are: ● ● $CCh when the ADD pin is connected to logic low voltage, $CEh when ADD pin is connected to logic high voltage. Table 8 summarizes the pin descriptions for the I²C bus interface. Table 8. Pin SDA SCL ADD This is the serial data pin This is the clock input pin User-setable portion of device’s I2C address I²C bus interface pin descriptions Functional Description 4.1.1 I²C bus operation The host MCU can write into the TS4975 control register to control the TS4975, and read from the control register to get a configuration from the TS4975. The TS4975 is addressed by the byte consisting of 7-bit slave address and R/W bit. Table 9. A6 1 The first byte after the START message for addressing the device A5 1 A4 0 A3 0 A2 1 A1 1 A0 A0 R/W X In order to write data into the TS4975, after the “start” message, the MCU must send the following data: ● ● send byte with the I²C 7-bit slave address and with a low level for the R/W bit send the data (control register setting) 22/36 TS4975 Application Information All bytes are sent with MSB bit first. The transfer of written data ends with a “stop” message. When transmitting several data, the data can be written with no need to repeat the “start” message and addressing byte with the slave address. In order to read data from the TS4975, after the “start” message, the MCU must send and receive the following data: ● ● send byte with the I²C 7-bit slave address and with a high level for the R/W bit receive the data (control register value) All bytes are read with MSB bit first. The transfer of read data is ended with “stop” message. When transmitting several data, the data can be read with no need to repeat the “start” message and the byte with slave address. In this case the value of control register is read repeatedly. When the thermo shutdown or pop and click reduction is active, specific values are read from the TS4975 (see Section 4.9: Pop and click performance on page 31 and Section 4.10: Thermo shutdown on page 32). Figure 59. I²C write/read operations SLAVE ADDRESS CONTROL REGISTERS SDA S 1 1 0 0 1 1 A0 0 A D7 D6 D5 D4 D3 D2 D1 D0 A P Start condition Volume Control settings Output Mode settings Stop condition Acknowledge from Slave R/W Acknowledge from Slave Phantom Ground settings Table 10. Ouput mode selection: G from -34 dB to + 18dB (by steps of 4dB)(1) Headphone Output 1 SD G x In1 G x In2 G x In1 G x In2 SD SD G x In1 G x In2 Headphone Output 2 SD G x In2 G x In1 G x In1 G x In2 G x In1 G x In2 SD SD Output Mode # 0 1 2 3 4 5 6 7 8 1. SD = Shutdown Mode In1 = Audio Input 1 In2= Audio Input2 G = Gain from Audio Input 1and Input 2 to Output1 and Output2 23/36 Application Information TS4975 4.1.2 Gain setting operation The gain of the TS4975 ranges from -34dB to +18 dB. At Power-up, both the right and left channels are set in Standby mode. Table 11. Gain settings truth table D7 (MSB) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D6 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D5 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 G: Gain (dB) # -34 -30 -26 -22 -18 -14 -10 -6 -2 +2 +6 +10 +14 +18 Table 12. Output mode settings truth table D2 X x 0 0 0 0 1 1 1 1 D1 X x 0 0 1 1 0 0 1 1 D0 X x 0 1 0 1 0 1 0 1 COMMENTS PHG off PHG on MODE 1 MODE 2 MODE 3 MODE4 MODE 5 MODE 6 MODE 7 MODE 8 D3: PHG on / off 0 1 x X X X X X X X Table 13. D7 (MSB) 0 Stand-by mode I²C condition D6 0 D5 0 D4 0 D3 X D2 X D1 X D0 X 24/36 TS4975 Table 14. D7 (MSB) 1 Application Information I²C control byte states D6 1 D5 1 D4 1 D3 x D2 X D1 X D0 X Undefined State 4.1.3 Acknowledge The number of data bytes transferred between the start and the stop conditions from the CPU master to the TS4975 slave is not limited. Each byte of eight bits is followed by one acknowledge bit. The TS4975 which is addressed, generates an acknowledge after the reception of each byte that has been clocked out. 4.2 Output configuration When the device is switched to Mode 5,6,7 or 8, where one channel is in shutdown, it means that corresponding output is in a high impedance state. 4.2.1 Single-ended configuration When the device is woken-up or switched via I²C interface to SE configuration, output amplifiers are biased to the VCC/2 voltage and this voltage is present on OUT1 and OUT2 pins. Pins PHG1 and PHG2 are in high impedance state. In this configuration an output capacitor, Cout, on each output is needed to block the VCC/2 voltage and couples the audio signal to the load. 4.2.2 Phantom ground configuration In a PHG configuration the internal buffers are connected to PHG1 and PHG2 pins and biased to the VCC/2 voltage. Output amplifiers (pins OUT1 and OUT2) are also biased to the VCC/2 voltage. Therefore, no output capacitors are needed. The advantage of the PHG configuration is the need for fewer external components as compared with a SE configuration. However, note that the device has higher power dissipation (see Section 4.3: Power dissipation and efficiency on page 26). In this configuration, PHG1 and PHG2 pins must be shorted and the connection between these pins should be as short as possible. For best crosstalk results, in this case, each speaker should be connected with a separate PHG wire (2 speakers connected with 4 wires) as shown in Figure 2: Phantom ground output configuration on page 4. You should avoid using only one common PHG wire for both speakers (i.e. 2 speakers connected with 3 wires), which would give much poorer crosstalk results. 4.2.3 Shutdown When the device goes to shutdown from SE or PHG mode, PHG1 and PHG2 outputs are in a high impedance state and OUT1 and OUT2 outputs are shorted together and connected to bias voltage. This voltage steadily decreases as the bypass capacitor Cb discharges, and reaches GND voltage when Cbypass is fully discharged. This output configuration is implemented to reach the best pop performance during chip wake-up. 25/36 Application Information TS4975 4.3 Power dissipation and efficiency Hypotheses: ● ● Voltage and current in the load are sinusoidal (Vout and I out). Supply voltage is a pure DC source (VCC). V out = V PEAK sin ω t ( V ) Regarding the load we have: and V out I out = ---------RL (A) and V PEAK P out = ----------------2R L 2 (A ) Single-ended configuration: The average current delivered by the supply voltage is: Icc AVG V PEAK 1 V PEAK = ------ ∫ ----------------- sin ( t ) dt = ----------------2π RL π RL 0 π (A) Figure 60. Current delivered by supply voltage in single-ended model The power delivered by supply voltage is: P supply = V C CI CC AVG (W) So, the power dissipation by each amplifier is P diss = P supply – P out ( W ) 2V CC P diss = ------------------ P out – P out ( W ) π RL and the maximum value is obtained when: ∂P diss ∂ P out =0 26/36 TS4975 and its value is: P diss MAX Application Information V CC = -----------2 π RL 2 (W) Note: This maximum value depends only on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply: π V PEAK P out η = ------------------ = -------------------P supply 2V CC The maximum theoretical value is reached when VPEAK = VCC/2, so π η = -- = 78.5% 4 Phantom ground configuration: The average current delivered by the supply voltage is: Icc AVG 2V PEAK 1 V PEAK = -- ∫ ----------------- sin ( t ) d t = -------------------π RL πR L 0 π (A ) Figure 61. Current delivered by supply voltage in phantom ground mode The power delivered by supply voltage is: P supply = V C CI CC AVG (W) Then, the power dissipation by each amplifier is 2 2V CC P diss = ---------------------- P out – P out π RL (W) and the maximum value is obtained when: ∂P diss ∂ P out =0 and its value is: P diss MAX 2V CC = -------------2 π RL 2 (W) Note: This maximum value depends only on power supply voltage and load values. 27/36 Application Information The efficiency is the ratio between the output power and the power supply: P out π V PEAK η = ------------------ = -------------------P supply 4V CC TS4975 The maximum theoretical value is reached when VPEAK = VCC/2, so π η = -- = 39.25% 8 The TS4975 is a stereo amplifier so it has two independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore the maximum die temperature is the sum of each amplifier’s maximum power dissipation. It is calculated as follows: Pdiss 1 = Power dissipation due to the first channel power amplifier. Pdiss 2 = Power dissipation due to the second channel power amplifier. Total Pdiss = Pdiss 1 + Pdiss 2 (W) In most cases, Pdiss 1 = Pdiss 2 , giving: TotalP diss = 2P diss1 Single ended configuration: 2 2V CC TotalP diss = ---------------------- P out – 2P out ( W ) π RL Phantom ground configuration: 4 2V C C TotalPdiss = ---------------------- P out – 2P out ( W ) π RL 4.4 Low frequency response Input capacitor Cin The input coupling capacitor blocks the DC part of the input signal at the amplifier input. In the low-frequency region, Cin starts to have an effect. Cin with Zin forms a first-order, high-pass filter with -3 dB cut-off frequency. 1 F C L = ----------------------- ( Hz ) 2 π Z in C in Zin is the input impedance of the corresponding input (30 k Ω for In1 & In2). Note: For all inputs, the impedance value remains for all gain settings. This means that the lower cutoff frequency doesn’t change with gain setting. Note also that 30 kΩ is a typical value and there is tolerance around this value (see Chapter 3: Electrical Characteristics on page 5). From Figure 53 you could easily establish the Cin value for a -3dB cut-off frequency required. 28/36 TS4975 Application Information Output capacitor Cout In single-ended mode the external output coupling capacitors Cout are needed. This coupling capacitor Cout with the output load RL also forms a first-order high-pass filter with -3 dB cut off frequency. 1 F CL = ------------------------- ( Hz ) 2 π R L C out See Figure 54 to establish the Cout value for a -3dB cut-off frequency required. These two first-order filters form a second-order high-pass filter. The -3 dB cut-off frequency of these two filters should be the same, so the following formula should be respected: 1 1 ----------------------- ≅ ------------------------2 π Z in C in 2 π R L C out 4.5 Decoupling of the circuit Two capacitors are needed to properly bypass the TS4975 — a power supply capacitor Cs and a bias voltage bypass capacitor Cb. Cs has a strong influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With 1 µF, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1 µF, THD+N increases in high frequency and disturbances on power supply rail are less filtered. To the contrary, if Cs is higher than 1 µF, those disturbances an the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency: ● ● If Cb is lower than 1 µF, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than 1 µF, the benefit on THD+N and PSRR in the lower frequency range is small. The value of Cb also has an influence on startup time. 4.6 Power-on reset When power is applied to VCC, an internal Power On Reset holds the TS4975 in a reset state (shutdown) until the supply voltage reaches its nominal value. The Power On Reset has a typical threshold of 1.75V. During this reset state the outputs configuration is the same like in the shutdown mode (see Section 4.2: Output configuration on page 25). 29/36 Application Information TS4975 4.7 Notes on PSRR measurement What is PSRR? The PSRR is the Power Supply Rejection Ratio. The PSRR of a device is the ratio between a power supply disturbance and the result on the output. In other words, the PSRR is the ability of a device to minimize the impact of power supply disturbance to the output. How we measure the PSRR? The PSRR was measured according to the schematic shown in Figure 62. Figure 62. PSRR measurement schematic Principles of operation ● ● ● The DC voltage supply (VCC) is fixed The AC sinusoidal ripple voltage (Vripple) is fixed No bypasss capacitor Cs is used The PSRR value for each frequency is calculated as: RMS ( Out put ) PSRR = 20Log --------------------------------- ( dB ) RMS ( V ) ripple RMS is a rms selective measurement. 30/36 TS4975 Application Information 4.8 Startup time When the TS4975 is controlled to switch from full standby (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias.This length of this delay depends on the Cb and VCC values. A typical value can be calculated by following formula: VC C t wu = C b × ------------------------ × 50000 + 0.008 ( s ) V CC – 1.2 This formula assumes that Cb voltage is equal to 0 V. If the Cb voltage is not equal 0 V, the startup time will be always lower. In Figure 63 you could easily establish typical startup time for given supply voltage and bypass capacitor Cb. Figure 63. Typical startup time versus bypass capacitance 400 350 300 Startup time (ms) 250 200 150 100 50 0 0.4 0.8 Vcc=2.5V Vcc=3.3V Vcc=5V 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Bypass capacitor Cb (µF) 4.9 Pop and click performance The TS4975 has internal pop and click reduction circuitry which eliminates the output transients, for example during switch-on or switch-off phases, during a switch from an output mode to another or during change in volume. The performance of this circuitry is closely linked to the values of the input capacitor Cin, the output capacitor Cout (for Single-Ended configuration) and the bias voltage bypass capacitor Cb. The value of Cin and Cout is determined by the lower cut-off frequency value requested. The value of Cb will affect the THD+N and PSRR values in lower frequencies. The TS4975 is optimized to have a low pop and click in the typical schematic configuration (see Figure 1 on page 3 and Figure 2 on page 4). During the device start-up period when the pop and click reduction is active, the value $Fxh (1111xxxx binary) can be read from the internal device registry. Once the device is fully operational and the pop and click is inactive, the last value of control register can be read. 31/36 Application Information TS4975 4.10 Thermo shutdown The TS4975 device has internal protection in case of over temperature by thermal shutdown. Thermal shutdown is active when the device reaches temperature 150°C. When thermo shutdown protection is active, value $Fxh (1111xxxx binary) can be read from the internal device registry. When thermo shutdown protection state disappears, the last value of control register can be read. 4.11 Demoboard A demoboard for the TS4975 is available. For more information about this demoboard, please refer to Application Note AN2151, which can be found on www.st.com. Figure 67 on page 33 shows the schematic of the demoboard. Figure 64, Figure 65 and Figure 66, show bottom layer, top layer and the component locations, respectively. Figure 64. Bottom layer Figure 65. Top layer Figure 66. Component location 32/36 TS4975 Figure 67. Demoboard schematic Vcc1 Vcc1 Application Information Cn1 + C1 1µF + C2 1µF 14 U1 Cn6 R1 1k 2 Bypass Bias IN1 Pre-Amplifier P1 IN1 + 330nF PHG1 Amplifier C10 1 OUT1 Amplifier Vcc IN1 OUT1 13 220µF JP1 1 2 3 4 HEADER 4 PHG2 Amplifier 1 2 3 C3 + Cn7 PHG1 Mode Select 12 1 J1 2 3 PHONEJACK STEREO PHG2 10 IN2 Pre-Amplifier P2 IN2 + 330nF C11 6 OUT2 Amplifier C4 IN2 OUT2 9 + 220µF Volume control GND ADD I2C SCL SDA 1 2 3 R2 1k TS4975 Cn8 8 5 3 Vcc1 4 JP2 R3 10k 4 3 2 1 Cn4 Cn3 HEADER 4 Vcc1 Vcc1 Cn2 1 2 3 R4 10k R5 1 0k I2C BUS SDA SCL SDA SCL SDA SDA Vcc2 SCL Vcc1 Vcc2 Vcc2 R8 180R U2A 1 CON1 1 6 2 7 3 8 4 9 5 RS232 GND2 2 KP1040 GND2 15 GND2 13 8 11 10 GND2 R1IN R2IN T1IN T2IN C1+ C1C2+ C2V+ V16 R7 10K Cn5 16 Vcc2 R6 360R U2B 3 4 Vcc2 14 13 C5 1µF KP1040 + U3 R1OUT R2OUT T1OUT T2OUT 12 9 14 7 R9 360R U2C 5 6 KP1040 12 11 DTR GND + C6 0.1µF GND2 C7 0.1µF 1 3 4 5 2 6 C9 0.1µF + + C8 0.1µF + GND GND2 15 ST232 Vcc2 GND2 Vcc TXD 33/36 Package Mechanical Data TS4975 5 Package Mechanical Data Figure 68. TS4975 footprint recommendation 500µm Φ=250µm 500µm 75µm min. 100µm max. Track 500µm Φ=400µm typ. Φ=340µm min. 150µm min. Non Solder mask opening 500µm Pad Pad in Cu 18µm with Flash NiAu (2-6µm, 0.2 µm max.) Figure 69. Pin out (top view) 3 OUT1 PHG1 PHG2 OUT2 2 IN1 VCC GND IN2 1 BYPASS SCL SDA ADD A B C D Figure 70. Marking (top view) ■ ■ ■ ■ Logo: ST Part Number: A75 Date Code: YWW The Dot is for marking pin A1 ● E E Lead Free symbol A75 YW W 34/36 TS4975 Figure 71. Flip-chip - 12 bumps 2300µm Package Mechanical Data ■ ■ 1800µm 500µm Die size: 2.3mm x 1.8mm ± 30µm Die height (including bumps): 600µm Bumps diameter: 315µm ±50µm Bump diameter before reflew: 300µm ±10µm Bumps height: 250µm ±40µm Die height: 350µm ±20µm Pitch: 500µm ±50µm Capillarity: 60µm max ■ ■ ■ 500 500µm ■ ■ 600µm ■ Figure 72. Tape & reel specification (top view) 4 1.5 1 A A Die size Y + 70µm 1 8 Die size X + 70µm 4 All dimensions are in mm User direction of feed 35/36 Revision History TS4975 6 Revision History Date Nov. 2004 July 2005 Nov. 2005 Revision 1 2 3 Initial release. Product in full production The following changes were made in this revision: – Application notes updated – Formatting changes throughout Changes Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 36/36