TS4985
2 X 1.2W Stereo Audio Power Amplifier with
Dedicated Standby Pins
■
Operating from VCC=2.2V to 5.5V
■
1.2W output power per channel @ VCC=5V,
THD+N=1%, RL=8Ω
■
10nA standby current
■
62dB PSRR @ 217Hz with grounded inputs
■
High SNR: 106dB(A) typ.
■
Near zero pop & click
Pin Connection (top view)
■
Lead-free 15 bumps, flip-chip package
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Flip-chip - 15 bumps
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VCC2
Description
let
VCC1
The TS4985 has been designed for top-class
stereo audio applications. Thanks to its compact
and power-dissipation efficient flip-chip package,
it suits various applications.
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With a BTL configuration, this audio power
amplifier is capable of delivering 1.2W per
channel of continuous RMS output power into an
8Ω load @ 5V.
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Each output channel (left and right), has an
external controlled standby mode pin (STDBYL &
STDBYR) to reduce the supply current to less
than 10nA per channel. The device also features
an internal thermal shutdown protection.
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The gain of each channel can be configured by
external gain setting resistors.
IN+R
IN-R
STDBYL
VO+L
VO+R
BYPASS
VO-L
IN+L
GND2
STDBYR
IN-L
VO-R
GND1
Applications
■
Cellular mobile phones
■
Notebook & PDA computers
■
LCD monitors & TVs
■
Portable audio devices
OOrder Codes
Part Number
Temperature Range
Package
Packaging
Marking
-40, +85°C
Lead free flip-chip
Lead free flip-chip +
back coating
Tape & Reel
A85
TS4985EIJT
TS4985EKIJT
May 2005
Rev 2
1/29
www.st.com
29
Typical Application Schematic
1
TS4985
Typical Application Schematic
Figure 1 shows a typical application schematic for the TS4985.
Figure 1.
Application schematic
Cfeed-L
Rfeed-L
22k
+
VCC
Cin-L
Rin-L
GND
A1
IN-L
B2
IN+L
B6
-
22k
100n
VO-L
VCC
1
2
3
+
-
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Bypass
D6
IN+R
+
E5
IN-R
-
100n
22k
VCC
1
2
3
)
(s
C1
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Table 1.
bs
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VO+L
B4
VO-R
E3
VO+R
D4
AV = -1
Neg. Output L
Pos. Output L
Neg. Output R
Pos. Output R
+
Standby R
E1
TS4985
D2
Cfeed-R
Rfeed-R
22k
External component descriptions
Components
Functional Description
RIN L,R
Inverting input resistors which sets the closed loop gain in
conjunction with Rfeed. These resistors also form a high pass
filter with CIN (fc = 1 / (2 x Pi x RIN x CIN))
CIN L,R
Input coupling capacitors which blocks the DC voltage at the
amplifier input terminal
R FEED L,R
Feedback resistors which sets the closed loop gain in
conjunction with RIN
CS
Supply Bypass capacitor which provides power supply filtering
CB
Bypass pin capacitor which provides half supply filtering
AV L, R
2/29
+
GND2
Rin-R
Input R
C3
Cb
1u
GND1
+
AV = -1
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Standby L
Bias
GND
A3
C5
Cin-R
)
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VCC2
Input L
VCC1
A5
Cs
1u
Closed loop gain in BTL configuration = 2 x (RFEED / RIN) on
each channel
TS4985
2
Absolute Maximum Ratings
Absolute Maximum Ratings
Table 2.
Key parameters and their absolute maximum ratings
Symbol
Value
Unit
6
V
Input Voltage (2)
GND to VCC
V
Toper
Operating Free Air Temperature Range
-40 to + 85
°C
Tstg
Storage Temperature
-65 to +150
°C
VCC
Vi
Tj
Rthja
Pd
Parameter
Supply voltage (1)
Maximum Junction Temperature
150
Flip-chip Thermal Resistance Junction to Ambient
180
Power Dissipation
ESD
Human Body Model
ESD
Machine Model
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Internally Limited
(3)
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Latch-up Immunity
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°C
200
200
°C/W
kV
V
mA
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1. All voltages values are measured with respect to the ground pin.
2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V
3. All voltage values are measured from each pin with respect to supplies.
Table 3.
Operating conditions
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Symbol
Parameter
Value
Unit
2.2 to 5.5
V
1.2V to VCC
V
1.35 ≤ V STB ≤ VCC
GND ≤ VSTB ≤ 0.4
V
Load Resistor
≥4
Ω
Resistor Output to GND (VSTB = GND)
≥1
MΩ
Thermal Shutdown Temperature
150
°C
Flip-chip Thermal Resistance Junction to Ambient (1)
110
VCC
Supply Voltage
VICM
Common Mode Input Voltage Range
VSTB
Standby Voltage Input:
Device ON
Device OFF
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RL
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ROUTGND
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TSD
RTHJA
1.
°C/W
When mounted on a 4-layer PCB.
3/29
Electrical Characteristics
3
TS4985
Electrical Characteristics
Table 4.
VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Symbol
ICC
ISTANDBY
Standby Current (1)
No input signal, Vstdby = GND, RL = 8Ω
Output Offset Voltage
No input signal, RL = 8Ω
Po
Output Power
THD = 1% Max, F = 1kHz, RL = 8Ω
PSRR
Crosstalk
Min.
Supply Current
No input signal, no load
Voo
THD + N
0.9
Total Harmonic Distortion + Noise
Po = 1Wrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω
Power Supply Rejection Ratio(2)
RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded
F = 217Hz
F = 1kHz
Channel Separation, RL = 8Ω
F = 1kHz
F = 20Hz to 20kHz
TWU
Wake-Up Time (Cb = 1µF)
TSTDB
Standby Time (Cb = 1µF)
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55
55
Max.
7.4
12
10
1000
1
10
1.2
0.2
-107
-82
nA
mV
W
%
dB
130
10
du
mA
dB
62
64
90
Unit
)
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Typ.
ms
µs
VSTDBH
Standby Voltage Level High
VSTDBL
Standby Voltage Level Low
ΦM
Phase Margin at Unity Gain
RL = 8Ω, CL = 500pF
65
Degrees
GM
Gain Margin
RL = 8Ω, C L = 500pF
15
dB
GBP
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
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Parameter
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1.3
V
0.4
V
1. Standby mode is activated when Vstdby is tied to Gnd.
2. All PSRR data limits are guaranteed by production sapling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon
Vcc
4/29
TS4985
Electrical Characteristics
Table 5.
VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Symbol
ICC
ISTANDBY
Parameter
Min.
Supply Current
No input signal, no load
Standby Current (1)
No input signal, Vstdby = GND, RL = 8Ω
Voo
Output Offset Voltage
No input signal, RL = 8Ω
Po
Output Power
THD = 1% Max, F = 1kHz, RL = 8Ω
375
THD + N
Total Harmonic Distortion + Noise
Po = 400mWrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω
PSRR
Power Supply Rejection Ratio(2)
RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded
F = 217Hz
F = 1kHz
Channel Separation, RL = 8Ω
Crosstalk
F = 1kHz
F = 20Hz to 20kHz
TWU
Wake-Up Time (Cb = 1µF)
TSTDB
Standby Time (Cb = 1µF)
Standby Voltage Level High
VSTDBL
Standby Voltage Level Low
ΦM
Phase Margin at Unity Gain
RL = 8Ω, CL = 500pF
GM
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du
Max.
6.6
12
10
1000
1
10
mA
500
mW
)
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%
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63
-107
-82
110
nA
mV
0.1
55
55
Unit
dB
dB
140
10
ms
µs
1.2
V
0.4
V
65
Degrees
Gain Margin
RL = 8Ω, C L = 500pF
15
dB
GBP
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
GBP
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
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VSTDBH
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Typ.
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1. Standby mode is activated when Vstdby is tied to Gnd.
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon
Vcc
5/29
Electrical Characteristics
Table 6.
TS4985
VCC = +2.6V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Symbol
ICC
ISTANDBY
Min.
Supply Current
No input signal, no load
Standby Current (1)
No input signal, Vstdby = GND, RL = 8Ω
Voo
Output Offset Voltage
No input signal, RL = 8Ω
Po
Output Power
THD = 1% Max, F = 1kHz, RL = 8Ω
220
THD + N
Total Harmonic Distortion + Noise
Po = 200mWrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω
PSRR
Power Supply Rejection Ratio(2)
RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded
F = 217Hz
F = 1kHz
Crosstalk
Channel Separation, RL = 8Ω
F = 1kHz
F = 20Hz to 20kHz
TWU
Wake-Up Time (Cb = 1µF)
TSTDB
Standby Time (Cb = 1µF)
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Typ.
Max.
6.2
12
10
1000
1
10
Unit
mA
nA
300
mV
mW
)
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0.1
%
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55
55
60
62
-107
-82
125
dB
dB
150
10
ms
µs
VSTDBH
Standby Voltage Level High
VSTDBL
Standby Voltage Level Low
ΦM
Phase Margin at Unity Gain
RL = 8Ω, CL = 500pF
65
Degrees
GM
Gain Margin
RL = 8Ω, C L = 500pF
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15
dB
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
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GBP
so
Parameter
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du
1.2
V
0.4
V
1. Standby mode is activated when Vstdby is tied to Gnd.
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6/29
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon
Vcc
TS4985
Electrical Characteristics
Table 7.
Index of graphics
Description
Figure
Page
Open Loop Frequency Response
Figure 2 to 7
page 8
Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 8 to 13
page 9
Power Supply Rejection Ratio (PSRR) vs. DC Output Voltage
Figure 14 to 22
page 10 to
page 11
Power Supply Rejection Ratio (PSRR) at F=217Hz vs. Bypass
Capacitor
Figure 23
page 11
Output Power vs. Power Supply Voltage
Figure 24 to 26
page 11 to
page 12
Output Power vs. Load Resistor
Figure 27 to 29
Power Dissipation vs. Output Power
Figure 30 to 32
Clipping Voltage vs. Power Supply Voltage and Load Resistor
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Figure 33,
Figure 34
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page 12
page 12 to
page 13
page 13
Figure 35
page 13
Figure 36 to 38
page 13 to
page 14
Figure 39
page 14
Figure 40
page 14
Figure 41 to 49
page 14 to
page 15
Figure 50 to 52
page 16
Figure 53 to 55
page 16
SIgnal to Noise Ratio vs. Power Supply with Unweighted Filter
(20Hz to 20kHz)
Figure 56,
Figure 57
page 17
SIgnal to Noise Ratio vs. Power Supply with A-weighted Filter
Figure 58,
Figure 59
page 17
Power Derating Curves
Figure 60
page 17
Current Consumption vs. Power Supply Voltage
let
Current Consumption vs. Standby Voltage
Output Noise Voltage, Device ON
Output Noise Voltage, Device in Standby
)-
THD+N vs. Output Power
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THD+N vs. Frequency
Crosstalk vs. Frequency
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7/29
Electrical Characteristics
Open loop frequency response
Figure 3.
0
60
Open loop frequency response
0
60
Gain
Gain
40
-80
0
-120
Phase
-120
-20
-160
Vcc = 2.6V
RL = 8Ω
Tamb = 25°C
-60
0.1
1
10
100
1000
-40
-200
10000
-160
Vcc = 3.3V
RL = 8Ω
Tamb = 25°C
-60
0.1
1
10
Frequency (kHz)
Figure 4.
Open loop frequency response
)-
-120
s
(
t
c
-20
Vcc = 5V
RL = 8Ω
Tamb = 25°C
-60
0.1
1
b
O
Gain (dB)
-80
0
Phase (°)
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100
1000
-80
Phase
-120
0
-200
10000
-40
0.1
1
10
let
O
Figure 7.
0
100
80
20
-120
Gain (dB)
-80
Phase
Phase (°)
Gain (dB)
-40
60
0
-80
40
Phase
20
-120
0
-160
Vcc = 3.3V
CL = 560pF
Tamb = 25°C
1
-20
10
100
Frequency (kHz)
8/29
Gain
-40
40
-40
0.1
-200
10000
0
100
60
-20
1000
Open loop frequency response
80
Gain
100
Frequency (kHz)
Open loop frequency response
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b
-160
Vcc = 2.6V
CL = 560pF
Tamb = 25°C
Frequency (kHz)
Figure 6.
-40
20
-20
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Gain
40
-160
10
0
1000
-200
10000
-40
0.1
-160
Vcc = 5V
CL = 560pF
Tamb = 25°C
1
10
100
Frequency (kHz)
1000
-200
10000
Phase (°)
Gain (dB)
so
60
Phase
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let
80
-40
-200
10000
Open loop frequency response
100
Gain
20
)
s
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ct
1000
u
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Figure 5.
0
40
100
Frequency (kHz)
60
-40
-80
0
Phase (°)
-20
-40
-40
20
Gain (dB)
Phase
Phase (°)
20
Gain (dB)
40
-40
Phase (°)
Figure 2.
TS4985
TS4985
Figure 8.
Electrical Characteristics
Power supply rejection ratio (PSRR) Figure 9.
vs. frequency
0
PSRR (dB)
-20
-30
0
Vripple = 200mVpp
Rfeed = 22kΩ
Input = Floating
Cb = 0.1µF
RL >= 4Ω
Tamb = 25°C
-20
-40
-50
-30
-50
-60
-70
-70
100
1000
10000
Frequency (Hz)
-80
100000
Vcc = 2.2, 2.6, 3.3, 5V
-40
-60
-80
Vripple = 200mVpp
Rfeed = 22kΩ
Input = Floating
Cb = 1µF
RL >= 4Ω
Tamb = 25°C
-10
Vcc = 2.2, 2.6, 3.3, 5V
PSRR (dB)
-10
Power supply rejection ratio (PSRR)
vs. frequency
100
1000
10000
Frequency (Hz)
)
s
(
ct
100000
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Figure 10. Power supply rejection ratio (PSRR) Figure 11. Power supply rejection ratio (PSRR)
vs. frequency
vs. frequency
0
-20
-30
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = 0.1µF, Cin = 1µF
RL >= 4Ω
Tamb = 25°C
-20
du
-50
-60
100
ro
1000
10000
Frequency (Hz)
P
e
)
(s
ct
Vcc = 5, 3.3, 2.5 & 2.2V
-40
s
b
O
-10
PSRR (dB)
PSRR (dB)
-10
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0
-30
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = Cin = 1µF
RL >= 4Ω
Tamb = 25°C
-40
Vcc :
2.2V
2.6V
3.3V
5V
-50
-60
-70
100000
100
1000
10000
Frequency (Hz)
100000
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Figure 12. Power supply rejection ratio (PSRR) Figure 13. Power supply rejection ratio (PSRR)
vs. frequency
vs. frequency
0
PSRR (dB)
-10
-20
-30
0
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = 0.1µF, Cin = 1µF
RL >= 4Ω
Tamb = 25°C
-10
PSRR (dB)
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-20
Vripple = 200mVpp
Av = 10
Input = Grounded
Cb = Cin = 1µF
RL >= 4Ω
Tamb = 25°C
Vcc :
2.2V
2.6V
3.3V
5V
-30
Vcc = 5, 3.3, 2.5 & 2.2V
-40
-40
-50
-50
-60
100
1000
10000
Frequency (Hz)
100000
100
1000
10000
Frequency (Hz)
100000
9/29
Electrical Characteristics
TS4985
Figure 14. Power supply rejection ratio (PSRR) Figure 15. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
PSRR (dB)
-20
-30
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 5
Tamb = 25°C
-10
PSRR (dB)
-10
0
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 2
Tamb = 25°C
-40
-20
-30
-40
-50
-50
-60
-70
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
-60
-2.5 -2.0 -1.5 -1.0 -0.5
2.5
Differential DC Output Voltage (V)
0.0
0.5
)
s
(
ct
1.0
1.5
2.0
2.5
Differential DC Output Voltage (V)
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Figure 16. Power supply rejection ratio (PSRR) Figure 17. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
t
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0
-20
0
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
-10
-20
)
(s
-30
t
c
u
-40
-50
-2.5 -2.0 -1.5 -1.0 -0.5
Pr
od
0.0
s
b
O
0.5
1.0
1.5
2.0
PSRR (dB)
PSRR (dB)
-10
-30
Vcc = 3.3V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 2
Tamb = 25°C
-40
-50
-60
-70
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
2.5
Differential DC Output Voltage (V)
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Differential DC Output Voltage (V)
Figure 18. Power supply rejection ratio (PSRR) Figure 19. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
-10
-20
0
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
-10
PSRR (dB)
PSRR (dB)
s
b
O
-30
-40
-30
-40
-50
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
Differential DC Output Voltage (V)
10/29
-20
Vcc = 3.3V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
2.0
2.5
-50
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Differential DC Output Voltage (V)
TS4985
Electrical Characteristics
Figure 20. Power supply rejection ratio (PSRR) Figure 21. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
0
Vcc = 5V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 2
Tamb = 25°C
PSRR (dB)
-20
-30
-40
-20
-30
-40
-50
-50
-60
-70
-5
Vcc = 5V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 5
Tamb = 25°C
-10
PSRR (dB)
-10
-4
-3
-2
-1
0
1
2
3
Differential DC Output Voltage (V)
4
-60
-5
5
-4
)
s
(
ct
-3
-2
-1
0
1
2
3
Differential DC Output Voltage (V)
4
5
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P
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Figure 22. Power supply rejection ratio (PSRR) Figure 23. Power supply rejection ratio (PSRR)
vs. DC output voltage
at f=217Hz vs. bypass capacitor
t
e
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0
-20
uc
-40
-50
-5
-4
Pr
od
-3
-2
-1
0
1
2
3
Differential DC Output Voltage (V)
e
t
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)-
t(s
-30
4
s
b
O
PSRR at 217Hz (dB)
PSRR (dB)
-10
Av=10
Vcc:
2.6V
3.3V
5V
-30
Vcc = 5V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
-40
-50
-60
-70
5
Figure 24. Output power vs. power supply
voltage
-80
0.1
Av=2
Vcc:
2.6V
3.3V
5V
Av=5
Vcc:
2.6V
3.3V
5V
Tamb=25°C
1
Bypass Capacitor Cb ( F)
Figure 25. Output power vs. power supply
voltage
s
b
O
11/29
Electrical Characteristics
TS4985
Figure 26. Output power vs. power supply
voltage
Figure 27. Output power vs. load resistor
)
s
(
ct
Figure 28. Output power vs. load resistor
u
d
o
r
P
e
Figure 29. Output power vs. load resistor
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
Figure 30. Power dissipation vs. output power Figure 31. Power dissipation vs. output power
per channel
per channel
s
b
O
12/29
TS4985
Electrical Characteristics
Figure 32. Power dissipation vs. output power Figure 33. Clipping voltage vs. power supply
per channel
voltage and load resistor
)
s
(
ct
Figure 34. Clipping voltage vs. power supply
voltage and load resistor
u
d
o
t
e
l
o
8
du
e
t
e
ol
6
5
Both channels active
4
2
Only One channel active
o
r
P
0
Figure 36. Current consumption vs. power
supply voltage
s
b
O
Icc (mA)
ct
No Loads
Tamb=25 C
s
b
O
6
)
(s
r
P
e
Figure 35. Current consumption vs. power
supply voltage
0
1
2
6
Vcc = 2.6V
No Loads
Tamb=25 C
5
5
Vcc = 3.3V
No Loads
Tamb=25 C
Both channels active
4
Icc (mA)
4
Icc (mA)
4
Figure 37. Current consumption vs. standby
voltage
Both channels active
3
2
3
2
Only one channel active
Only one channel active
1
0
0.0
3
Vcc (V)
1
0.5
1.0
1.5
Vstdb (V)
2.0
2.5
0
0.0
0.5
1.0
1.5
2.0
Vstdb (V)
2.5
3.0
13/29
Electrical Characteristics
TS4985
Figure 38. Current consumption vs. standby
voltage
Figure 39. Output noise voltage device ON
8
7
Both channels active
6
Icc (mA)
5
Only one channel active
4
3
2
0
0.0
)
s
(
ct
Vcc = 5V
No Loads
Tamb=25 C
1
0.5
1.0
1.5
2.0 2.5 3.0
Vstdb (V)
3.5
4.0
4.5
5.0
Figure 40. Output noise voltage device in
Standby
u
d
o
r
P
e
Figure 41. THD + N vs. output power
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
Figure 42. THD + N vs. output power
s
b
O
14/29
Figure 43. THD + N vs. output power
TS4985
Electrical Characteristics
Figure 44. THD + N vs. output power
Figure 45. THD + N vs. output power
)
s
(
ct
Figure 46. THD + N vs. output power
u
d
o
Figure 47. THD + N vs. output power
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
let
P
e
Figure 48. THD + N vs. output power
o
s
b
Figure 49. THD + N vs. output power
O
15/29
Electrical Characteristics
TS4985
Figure 50. THD + N vs. frequency
Figure 51. THD + N vs. frequency
)
s
(
ct
u
d
o
Figure 52. THD + N vs. frequency
Figure 53. Crosstalk vs. frequency
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
let
P
e
Figure 54. Crosstalk vs. frequency
o
s
b
O
16/29
Figure 55. Crosstalk vs. frequency
TS4985
Electrical Characteristics
Figure 56. Signal to noise ratio vs. power
Figure 57. Signal to noise ratio vs. power
supply with unweighted filter (20Hz
supply with unweighted filter (20Hz
to 20kHz)
to 20kHz)
)
s
(
ct
u
d
o
r
P
e
Figure 58. Signal to noise ratio vs. power
Figure 59. Signal to noise ratio vs. power
supply with unweighted filter (20Hz
supply with A weighted filter (20Hz
to 20kHz)
to 20kHz)
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
Figure 60. Power derating curves
s
b
O
17/29
Application Information
4
TS4985
Application Information
The TS4985 integrates two monolithic power amplifiers with a BTL (Bridge Tied Load) output
type (explained in more detail in Section 4.1). For this discussion, only the left-channel amplifier
will be referred to.
Referring to the schematic in Figure 61, we assign the following variables and values:
Vin = IN-L
Vout1 = VO-L
Vout2 = VO+R
)
s
(
ct
Rin = Rin-L,
Rfeed = Rfeed-L
u
d
o
Cfeed = Cfeed-L
Figure 61. Typical application schematic - left channel
r
P
e
Cfeed = Cfeed-L
VCC
+
s
b
O
Cs
1u
t
c
u
Rin = Rin-L
Vin+= IN+L
d
o
r
P
e
t
e
l
o
s
b
O
4.1
Vout 1= VO-L
+
RL
Bias
AV = -1
Bypass
Vout 2 = VO+L
+
+
GND
-
TS4985
VCC2
Vin- = IN-L
VCC1
)
(s
Input L Cin = Cin-L
t
e
l
o
Rfeed = Rfeed-L
Cb
1u
BTL configuration principle
BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended
output amplifiers. Thus, we have:
Single-ended output 1 = Vout1 = Vout (V),
Single-ended output 2 = Vout2 = -Vout (V), Vout1 - Vout2 = 2Vout (V)
The output power is:
2
( 2V outRMS )
P out = -----------------------------------RL
For the same power supply voltage, the output power in a BTL configuration is four times higher
than the output power in a single-ended configuration.
18/29
TS4985
4.2
Application Information
Gain in typical application schematic
The typical application schematic (Figure 61) is shown on page 18.
In the flat region (no Cin effect), the output voltage of the first stage is:
R feed
V out 1 = ( – V in ) ------------R in
(V)
For the second stage: Vout2 = -Vout1 (V)
The differential output voltage is:
R fee d
V out 2 – V out1 = 2V in -------------Ri n
(V)
)
s
(
ct
The differential gain, referred to as Gv for greater convenience, is:
G
v
R feed
V out2 – Vout 1
= ---------------------------------- = 2 ------------Vin
R in
u
d
o
r
P
e
Vout2 is in phase with Vin and Vout1 is phased 180° with Vin. This means that the positive
terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1.
4.3
Low and high frequency response
t
e
l
o
s
b
O
In the low frequency region, Cin starts to have an effect. Cin forms with Rin a high-pass filter with
a -3dB cut-off frequency:
)
(s
t
c
u
1
F CL = -------------------------2 π Ri n Ci n
(Hz)
In the high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in
parallel with Rfeed. It forms a low-pass filter with a -3dB cut-off frequency. FCH is in Hz.
d
o
r
1
F CH = ------------------------------------2 π R feed C fe ed
P
e
(Hz)
t
e
l
o
The following graph (Figure 62) shows an example of Cin and Cfeed influence.
10
5
0
Gain (dB)
s
b
O
Figure 62. Frequency response gain versus Cin & Cfeed
Cfeed = 330pF
Cfeed = 680pF
-5
-10
-15
-20
-25
10
Cin = 470nF
Cfeed = 2.2nF
Cin = 22nF
Cin = 82nF
Rin = Rfeed = 22kΩ
Tamb = 25°C
100
1000
Frequency (Hz)
10000
19/29
Application Information
4.4
TS4985
Power dissipation and efficiency
Hypotheses:
●
Voltage and current in the load are sinusoidal (Vout and Iout).
●
Supply voltage is a pure DC source (Vcc).
Regarding the load we have:
Vout = V PEAK sin ω t
(V)
and
Vout
Iout = ------------RL
(A)
)
s
(
ct
and
V PEA K 2
P out = ------------------------2R L
r
P
e
Therefore, the average current delivered by the supply voltage is:
I
CCAVG
V
PEAK
= 2 --------------------π RL
(A)
t
e
l
o
The power delivered by the supply voltage is:
bs
P supply = V CC ⋅ ICC
AVG
u
d
o
(W)
O
)
(W)
Then, the power dissipated by each amplifier is:
( W)
P diss = P supply – P out
s
(
t
c
u
d
o
r
P
e
P
diss
2 2V CC
= ----------------------- ⋅ Pout – P out
π RL
( W)
and the maximum value is obtained when:
t
e
l
o
bs
O
Note:
∂ Pdiss
--------------------- = 0
∂ P out
and its value is:
2
2V cc
P dissma x = -------------π2 R
L
(W)
This maximum value is only depending on power supply voltage and load values.
The efficiency, η, is the ratio between the output power and the power supply:
Pout
π VPEAK
η = ------------------- = -----------------------P supply
4V CC
The maximum theoretical value is reached when VPEAK = VCC, so that:
π
----- = 78.5%
4
20/29
TS4985
Application Information
The TS4985 has two independent power amplifiers, and each amplifier produces heat due to its
power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier’s
maximum power dissipation. It is calculated as follows:
Pdiss L = Power dissipation due to the left channel power amplifier
Pdiss R = Power dissipation due to the right channel power amplifier
Total Pdiss = Pdiss L + Pdiss R (W)
In most cases, Pdiss L = Pdiss R, giving:
Total P
diss
= 2P
(W)
dis sL
or, stated differently:
4 2VCC
Total P diss = ---------------------- Pout – 2P out
π RL
4.5
)
s
(
ct
(W )
u
d
o
r
P
e
Decoupling the circuit
t
e
l
o
Two capacitors are needed to correctly bypass the TS4985. A power supply bypass capacitor
CS and a bias voltage bypass capacitor CB.
s
b
O
CS has particular influence on the THD+N in the high frequency region (above 7kHz) and an
indirect influence on power supply disturbances. With a value for CS of 1µF, you can expect
similar THD+N performances to those shown in the datasheet. For example:
)
(s
●
In the high frequency region, if CS is lower than 1µF, it increases THD+N and disturbances
on the power supply rail are less filtered.
●
On the other hand, if C S is higher than µF, those disturbances on the power supply rail are
more filtered.
t
c
u
d
o
r
Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result
of PSRR (with input grounded and in the lower frequency region), in the following manner:
●
If Cb is lower than 1µF, THD+N increases at lower frequencies and PSRR worsens.
P
e
t
e
l
o
●
s
b
O
4.6
If Cb is higher than 1µF, the benefit on THD+N at lower frequencies is small, but the benefit
to PSRR is substantial.
Note that Cin has a non-negligible effect on PSRR at lower frequencies. The lower the value of
Cin, the higher the PSRR.
Wake-up time, TWU
When the standby is released to put the device ON, the bypass capacitor Cb will not be charged
immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly
until the Cb voltage is correct. The time to reach this voltage is called wake-up time or TWU and
specified in electrical characteristics table with Cb = 1µF.
If Cb has a value other than 1µF, please refer to the graph in Figure 63 to establish the wake-up
time value.
21/29
Application Information
TS4985
Due to process tolerances, the maximum value of wake-up time could be establish by the graph
in Figure 64.
Figure 64. Maximum wake-up time vs. C b
Figure 63. Typical wake-up time vs. Cb
Tamb=25°C
Startup Time (ms)
Vcc=3.3V
400
Vcc=3.3V
Vcc=2.6V
300
200
Vcc=5V
100
0
Note:
Tamb=25°C
600
500
Max. Startup Time (ms)
600
500
Vcc=2.6V
400
300
200
)
s
(
ct
Vcc=5V
100
1
0.1
2
3
Bypass Capacitor Cb ( F)
4
0
0.1
4.7
1
du
2
3
Bypass Capacitor Cb ( F)
4
4.7
o
r
P
4.7
Bypass capacitor Cb as also a tolerance of typically +/-20%. To calculate the wake-up time with
this tolerance, refer to the previous graph (considering for example for Cb = 1µF in the range of
0.8µF ≤ 1µF ≤ 1.2µF).
e
t
e
ol
Shutdown time
s
b
O
When the standby command is set, the time required to put the two output stages in high
impedance and the internal circuitry in shutdown mode is a few microseconds.
)
(s
Note:
In shutdown mode, Bypass pin and Vin- pin are short-circuited to ground by internal switches.
This allows for the quick discharge of the Cb and Cin capacitors.
4.8
Pop performance
t
c
u
d
o
r
P
e
Pop performance is intimately linked with the size of the input capacitor C in and the bias voltage
bypass capacitor Cb.
t
e
l
o
s
b
O
The size of Cin is dependent on the lower cut-off frequency and PSRR values requested. The
size of Cb is dependent on THD+N and PSRR values requested at lower frequencies.
Moreover, Cb determines the speed with which the amplifier turns ON. In order to reach near
zero pop and click, the equivalent input constant time is:
τin = (Rin + 2kΩ) x Cin (s) with Rin ≥ 5kΩ
must not reach the τin maximum value as indicated in the graph below in Figure 65.
22/29
TS4985
Application Information
Figure 65. τin max. versus bypass capacitor
160 Tamb=25°C
Vcc=3.3V
in max. (ms)
120
Vcc=2.6V
80
40
Vcc=5V
0
1
2
3
Bypass Capacitor Cb ( F)
)
s
(
ct
4
u
d
o
By following previous rules, the TS4985 can reach near zero pop and click even with high gains
such as 20dB.
r
P
e
Example calculation:
t
e
l
o
With Rin = 22kΩ and a 20Hz, -3db low cut-off frequency, Cin = 361nF. So, Cin =390nF with
standard value which gives a lower cut-off frequency equal to 18.5Hz. In this case,
(Rin + 2kΩ) x Cin = 9.36ms. When referring to the previous graph, if Cb =1µF and Vcc = 5V, we
read 20ms max. This value is twice as high as our current value, thus we can state that pop and
click will be reduced to its lowest value. Minimizing both Cin and the gain benefits both the pop
phenomena, and the cost and size of the application.
)
(s
s
b
O
t
c
u
4.9
Dedicated standby control
d
o
r
TS4985 has two standby control inputs to allow to put each channel in standby mode
independently. In case a channel is active and another one in standby mode It’s very important
to be in line with a following recommendation to reach near zero pop. When left (right) channel
is active and right (left) channel is in standby mode it's necessary to put active channel in
standby mode first and then immediately (with regard to Standby time) activate right (left)
channel or both channels together in at the same moment.
P
e
t
e
l
o
s
b
O
4.10
Application example: differential-input BTL power stereo
amplifier
The schematic in Figure 65 shows how to design the TS4985 to work in differential-input mode.
For this discussion, only the left-channel amplifier will be referred to.
Let:
R1R = R2L = R1, R 2R = R2L = R2
CinR = C inL = Cin
The gain of the amplifier is:
R2
Gvdif = 2 × ------R1
23/29
Application Information
TS4985
In order to reach the optimal performance of the differential function, R1 and R2 should be
matched at 1% maximum.
Figure 66. Differential input amplifier configuration
R2L
Pos. Input LEFT
CinL
R1L
VCC
+
R1L
Cs
VCC1
CinL
IN-L
VCC2
Neg. Input LEFT
VO-L
IN+L
R2L
+
StandBy L
LEFT Speaker
8 Ohms
-
StandBy L
Control
Bias
AV = -1
Bypass
+
R2R
CinR
Pos. Input RIGHT
R1R
IN+R
u
d
o
+
VO-R
IN-R
CinR
Neg. Input RIGHT
r
P
e
-
R1R
t
e
l
o
-
AV = -1
StandBy R
Control
StandBy R
+
+
Cb
GND2
s
b
O
GND1
)
(s
R2R
)
s
(
ct
VO+L
RIGHT Speaker
8 Ohms
VO+R
U1
TS4985
t
c
u
The value of the input capacitor CIN can be calculated with the following formula, using the -3dB
lower frequency required (where FL is the lower frequency required):
d
o
r
P
e
t
e
l
o
Note:
s
b
O
1
(F )
2 π R 1 FL
This formula is true only if:
FCB =
1
(Hz )
2 π (R 1 + R 2 ) C B
is 5 times lower than FL.
The following bill of materials (Table 8) is provided as an example of a differential amplifier with
a gain of 2 and a -3dB lower cut-off frequency of about 80Hz.
Table 8.
24/29
C IN ≈
Example of a bill of materials
Designator
Part Type
R1L = R1R
20kΩ / 1%
R2L = R2R
20kΩ / 1%
CinR = CinL
100nF
C b=C S
1µF
U1
TS4985
TS4985
4.11
Application Information
Demoboard
A demoboard for the TS4985 in flip-chip package is available.
For more information about this demoboard, please refer to Application Note AN2152, which
can be found on www.st.com.
Figure 67 shows the schematic of the demoboard. Figure 68, Figure 69 and Figure 70 show the
component locations, top layer and bottom layer respectively.
Figure 67. Demoboard schematic
C2
1
2
1 R2
2
)
s
(
ct
22K
1
VCC
1
2
1
Cn9
Vcc
GND
Cn1
neg
GND
InputL
Cn3
pos.
GND
C1
1
2
1
2
1
1 R1
2
2
6
IN-L
1 R3
2
5
IN+L
Cn7 VCC
1
2
3
Jumper J1
Jumper J2
15
s
(
t
c
8
2
1
r
P
e
t
e
l
o
+
bs
STDBYL
O
)
StandByL
Cn8 VCC
1
2
3
U1
-
22K
100nF
C3
1
2
u
d
o
C8
100nF
TS4985_FC_ADAPTER
VCC2
VCC1
2
2
C7
1uF
VO-L
4
VO+L
3
-
AV = -1
Bias
2
1
Cn2
neg.
pos.
OUTL
+
STDBYR
StandByR
14
IN+R
VO-R
11
+
2
1
Cn5
neg.
pos.
OUTR
1
2
IN-R
R7
-
R8
AV = -1
2
7
Bypass
VO+R
12
+
1 R5
GND1
GND2
C9
1uF
9
Pr
u
d
o
1 R6
13
10
s
b
O
e
t
e
ol
2
22K
2
pos.
GND
1
2
1 R4
2
100nF
C6
1
2
1
Cn6
1
1
InputR
C4
1
2
2
Cn4
neg.
GND
2
22K
C5
1
2
25/29
Application Information
TS4985
Figure 68. Component locations
)
s
(
ct
Figure 69. Top layer
u
d
o
r
P
e
t
e
l
o
)
(s
Figure 70. Bottom layer
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
26/29
s
b
O
TS4985
5
Package Mechanical Data
Package Mechanical Data
Figure 71. Pinout (top view)
6
5
4
3
1
IN-R
STDBYL
VCC1
VO+L
u
d
o
VO+R
BYPASS
VO-L
2
)
s
(
ct
IN+R
VCC2
r
P
e
VO-R
IN+L
GND2
t
e
l
o
GND1
STDBYR
IN-L
Note: Balls are underneath
A
B
C
D
)
(s
Figure 72. Marking (top view)
t
c
u
od
Pr
E
s
b
O
E
Marking shows:
■
ST Logo
■
Product & assembly code: XXX
- A85 from Tours
- 858 from Singapore
- 85K from Shenzhen
■
3-digit datecode: YWW
■
“E” lead-free symbol
■
The dot marks position of pin A1
XXX
ol
ete
bs
YWW
O
27/29
Package Mechanical Data
TS4985
Figure 73. Package mechanical data for 15-bump flip-chip
2.40 mm
0.25m
m
0.5mm
1.90 mm
∅ 0.3mm
0.86mm
60 µm Back coating *
600 µm
■
Die size: 2.40 x 1.90 mm ±30µm
■
Die height (including bumps): 600µm
■
Back coating height (optional): 60µm
■
Bump diameter: 315µm ±50µm
■
Bump diameter before reflow: 300µm
±10µm
■
Bump height: 250µm ±40µm
■
Die height: 350µm ±20µm
■
Pitch: 500µm ±50µm
■
Coplanarity: 60µm max.
u
d
o
r
P
e
* Optional
t
e
l
o
Figure 74. Tape & Reel specification (top view)
bs
4
O
)
s
(
t
c
8
1
1
A
A
Die size Y + 70µm
r
P
e
u
d
o
t
e
l
o
s
b
O
Die size X + 70µm
4
All dimensions are in mm
User direction of feed
28/29
)
s
(
ct
1.5
TS4985
6
Revision History
Revision History
Date
Revision
Changes
November 2004
1
First Release corresponding to the product preview version
May 2005
2
Product in full production
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
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