TS4972EIJT1

TS4972 1.2W Audio Power Amplifier with Standby Mode Active High ■ ■ ■ ■ ■ ■ ■ ■ ■ Operating from VCC = 2.5V to 5.5V Rail-to-rail output 1.2W output power @ Vcc=5V, THD=1%, F=1kHz, with 8Ω load Ultra low consumption in standby mode (10nA) 75dB PSRR @ 217Hz from 2.5 to 5V Low pop & click Ultra low distortion (0.05%) Unity gain stable Flip-chip package 8 x 300µ m bumps Pin Connections (top view) TS4972JT - FLIP CHIP 7 Vin + 6 Vcc 5 Stdby 8 Vout1 Vout2 4 Vin Gnd Bypass Description The TS4972 is an Audio Power Amplifier capable of delivering 1.6W of continuous RMS ouput power into a 4Ω load @ 5V. This Audio Amplifier is exhibiting 0.1% distortion level (THD) from a 5V supply for a Pout = 250mW RMS. An external standby mode control reduces the supply current to less than 10nA. An internal shutdown protection is provided. The TS4972 has been designed for high quality audio applications such as mobile phones and to minimize the number of external components. The unity-gain stable amplifier can be configured by external gain setting resistors. V CC 3 5 B ypass S tandby Audio Input C in 7 Vin+ 1 2 3 TYPICAL APPLICATION SCHEMATIC C feed R feed VCC 6 VCC R in 1 VinVout 1 + RL 8 O hm s A V = -1 + Bias GND Cb 2 Vout 2 4 8 Cs Applications ■ ■ ■ ■ Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices Rstb TS4972 Order Codes Part Number TS4972IJT TS4972EIJT1 Temperature Range -40, +85°C Package Flip-Chip Packing Tape & Reel Marking 4972 1) Lead free Flip-Chip part number October 2004 Revision 2 1/30 TS4972 1 Absolute Maximum Ratings Absolute Maximum Ratings Table 1: Key parameters and their absolute maximum ratings Symbol VCC Vi Toper Tstg Tj Rthja Pd Supply voltage 2 1 Parameter Value 6 GND to VCC -40 to + 85 -65 to +150 150 200 Internally Limited4 2 200 Class A 250 Unit V V °C °C °C °C/W kV V °C Input Voltage Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient 3 Power Dissipation ESD Human Body Model ESD Machine Model Latch-up Latch-up Immunity Lead Temperature (soldering, 10sec) 1) All voltages values are measured with respect to the ground pin. 2) The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3) Device is protected in case of over temperature by a thermal shutdown active @ 150°C. 4) Exceeding the power derating curves during a long period, involves abnormal operating condition. Table 2: Operating Conditions Symbol VCC VICM VSTB RL Rthja Parameter Supply Voltage Common Mode Input Voltage Range Standby Voltage Input : Device ON Device OFF Load Resistor Thermal Resistance Junction to Ambient 1 Value 2.5 to 5.5 GND to VCC - 1.2V GND ≤ VSTB ≤ 0.5V VCC - 0.5V ≤ VSTB ≤ VCC 4 - 32 90 Unit V V V Ω °C/W 1) With Heat Sink Surface = 125mm2 2/30 Electrical Characteristics 2 Electrical Characteristics TS4972 Table 3: VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Parameter Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio2 f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8 Ω, CL = 500pF Gain Margin RL = 8 Ω, CL = 500pF Gain Bandwidth Product RL = 8 Ω Min. Typ. 6 10 5 1.2 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV W % dB Degrees dB MHz 1) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz 3/30 TS4972 Electrical Characteristics Table 4: VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified)3) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Parameter Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio2 f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8 Ω, CL = 500pF Gain Margin RL = 8 Ω, CL = 500pF Gain Bandwidth Product RL = 8 Ω Min. Typ. 5.5 10 5 500 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV mW % dB Degrees dB MHz 1) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz 3. All electrical values are made by correlation between 2.6V and 5V measurements 4/30 Electrical Characteristics Table 5: VCC = 2.6V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol ICC ISTANDBY Voo Po THD + N PSRR ΦM GM GBP Parameter Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = Vcc, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, f = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω Power Supply Rejection Ratio2 f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8 Ω, CL = 500pF Gain Margin RL = 8 Ω, CL = 500pF Gain Bandwidth Product RL = 8 Ω Min. Typ. 5.5 10 5 300 0.1 75 70 20 2 Max. 8 1000 20 TS4972 Unit mA nA mV mW % dB Degrees dB MHz 1) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz Table 6: Components description Components Rin Cin Rfeed Cs Cb Cfeed Rstb Gv Functional Description Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin)) Input coupling capacitor which blocks the DC voltage at the amplifier input terminal Feed back resistor which sets the closed loop gain in conjunction with Rin Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed)) Pull-up resistor which fixes the right supply level on the standby pin Closed loop gain in BTL configuration = 2 x (Rfeed / Rin) Remarks: 1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF. 2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way, the quiescent current remains the same. 3. The standby response time is about 1µs. 5/30 TS4972 Figure 1: Open Loop Frequency Response 0 60 Gain Vcc = 5V RL = 8Ω Tamb = 25°C -20 -40 -60 Phase (Deg) 40 Phase Gain (dB) Electrical Characteristics Figure 4: Open Loop Frequency Response 0 60 Gain Vcc = 5V ZL = 8Ω + 560pF Tamb = 25°C -20 -40 -60 Phase (Deg) Phase (Deg) 40 Gain (dB) Phase 20 -80 -100 -120 -80 -100 -120 20 0 -140 -160 0 -140 -160 -20 -180 -200 -20 -180 -200 -40 0.3 1 10 100 Frequency (kHz) 1000 10000 -220 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 -220 Figure 2: Open Loop Frequency Response 80 60 40 Gain (dB) Figure 5: Open Loop Frequency Response 80 60 40 Phase 20 0 -20 -40 0.3 Gain Vcc = 3.3V ZL = 8Ω + 560pF Tamb = 25°C 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 1 10 100 1000 Frequency (kHz) 10000 -240 Phase (Deg) 0 Gain Vcc = 33V RL = 8Ω Tamb = 25°C -20 -40 -60 -100 -120 -140 -160 -180 -200 -220 -240 Phase (Deg) Gain (dB) -80 Phase 20 0 -20 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 Figure 3: Open Loop Frequency Response 80 60 40 Gain (dB) Figure 6: Open Loop Frequency Response 80 Gain 60 40 Phase (Deg) Gain (dB) 0 Gain Vcc = 2.6V RL = 8Ω Tamb = 25°C -20 -40 -60 -80 Phase -100 -120 -140 -160 -180 -200 -220 -240 0 Vcc = 2.6V ZL = 8Ω + 560pF Tamb = 25°C -20 -40 -60 -80 Phase -100 -120 -140 -160 -180 -200 -220 -240 20 0 -20 -40 0.3 20 0 -20 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 1 10 100 1000 Frequency (kHz) 10000 6/30 Electrical Characteristics Figure 7: Open Loop Frequency Response TS4972 Figure 10: Power Supply Rejection Ratio (PSRR) vs Power supply -30 Vripple = 200mVrms Rfeed = 22Ω Input = floating RL = 8Ω Tamb = 25°C 100 80 60 Gain Gain (dB) -80 Phase -100 -40 -120 -140 -160 -180 Phase (Deg) PSRR (dB) 40 20 0 -20 -40 0.3 -50 -60 Vcc = 5V, 3.3V & 2.6V Cb = 1µF & 0.1µF Vcc = 5V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -70 -80 10 100 1000 10000 Frequency (Hz) 100000 Figure 8: Open Loop Frequency Response Figure 11: Power Supply Rejection Ratio (PSRR) vs Bypass Capacitor -10 Cb=1µF -20 Cb=10µF -30 Phase (Deg) PSRR (dB) 100 80 60 Gain Gain (dB) -80 Phase -100 -120 -140 -160 Vcc = 5, 3.3 & 2.6V Rfeed = 22k Rin = 22k, Cin = 1µF Rg = 100Ω, RL = 8Ω Tamb = 25°C Cb=47µF 40 20 -180 0 -20 -40 0.3 Vcc = 2.6V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -240 -40 -50 -60 -70 -80 10 Cb=100µF 100 1000 Frequency (Hz) 10000 100000 Figure 9: Open Loop Frequency Response Figure 12: Power Supply Rejection Ratio (PSRR) vs Feedback Resistor -10 -20 -30 Phase (Deg) 100 80 60 Gain Gain (dB) -80 Phase -100 -120 PSRR (dB) -140 -160 40 20 -180 0 -20 -40 0.3 Vcc = 3.3V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -240 -40 -50 -60 Vcc = 5, 3.3 & 2.6V Cb = 1µF & 0.1µF Vripple = 200mVrms Input = floating RL = 8Ω Tamb = 25°C Rfeed=110kΩ Rfeed=47kΩ Rfeed=22kΩ -70 Rfeed=10kΩ -80 10 100 1000 10000 Frequency (Hz) 100000 7/30 TS4972 Figure 13: Power Supply Rejection Ratio (PSRR) vs Feedback Capacitor -10 -20 -30 PSRR (dB) Electrical Characteristics Figure 16: Power Dissipation vs Pout 1.4 Vcc = 5, 3.3 & 2.6V Cb = 1µF & 0.1µF Rfeed = 22kΩ Vripple = 200mVrms Input = floating RL = 8Ω Tamb = 25°C Cfeed=0 Cfeed=150pF Cfeed=330pF Power Dissipation (W) Vcc=5V 1.2 F=1kHz THD+N 4.4ms). Increasing Cin value increases the pop and click phenomena to an unpleasant sound at power supply ON and standby function ON/OFF. Why Cs is not important in pop and click consideration ? Hypothesis : • Cs = 100µF • Supply voltage = 5V • Supply voltage internal resistor = 0.1Ω • Supply current of the amplifier Icc = 6mA At power ON of the supply, the supply capacitor is charged through the internal power supply resistor. So, to reach 5V you need about five to ten times the charging time constant of Cs (τs = 0.1xCs (s)). Then, this time equal 50µs to 100µs > tdischCs. Power amplifier design examples Given : TS4972 • Load impedance : 8Ω • Output power @ 1% THD+N : 0.5W • Input impedance : 10kΩ min. • Input voltage peak to peak : 1Vpp • Bandwidth frequency : 20Hz to 20kHz (0, 3dB) • Ambient temperature max = 50°C • SO8 package First of all, we must calculate the minimum power supply voltage to obtain 0.5W into 8Ω. With curves in fig. 15, we can read 3.5V. Thus, the power supply voltage value min. will be 3.5V. Following equation the maximum power dissipation Pdiss max = 2 Vcc 2 π2RL (W) with 3.5V we have Pdissmax=0.31W. Refer to power derating curves (fig. 20), with 0.31W the maximum ambient temperature will be 100°C. This last value could be higher if you follow the example layout shown on the demoboard (better dissipation). The gain of the amplifier in flat region will be: V OUT PP 2 2R L P OUT G V = -------------------- = ----------------------------------- = 5.65 V IN PP V IN PP We have Rin > 10kΩ. Let's take Rin = 10k Ω, then Rfeed = 28.25kΩ. We could use for Rfeed = 30kΩ in normalized value and the gain will be Gv = 6. In lower frequency we want 20 Hz (-3dB cut off frequency). Then: 1 C IN = ----------------------------- = 795nF 2 π R inF CL So, we could use for Cin a 1µF capacitor value which gives 16Hz. In Higher frequency we want 20kHz (-3dB cut off frequency). The Gain Bandwidth Product of the TS4972 is 2MHz typical and doesn't change when the amplifier delivers power into the load. The first amplifier has a gain of: Rfeed ----------------- = 3 Rin 23/30 TS4972 and the theoretical value of the -3dB cut-off higher frequency is 2MHz/3 = 660kHz. We can keep this value or limit the bandwidth by adding a capacitor Cfeed, in parallel on Rfeed. Then: 1 C F EED = -------------------------------------- = 265pF 2 π R F EE D F C H So, we could use for Cfeed a 220pF capacitor value that gives 24kHz. Now, we can calculate the value of Cb with the formula τb = 50kΩxCb >> τin = (Rin+Rfeed)xCin which permits to reduce the pop and click effects. Then Cb >> 0.8µF. We can choose for Cb a normalized value of 2.2µF that gives good results in THD+N and PSRR. In the following tables, you could find three another examples with values required for the demoboard. Application n°1 : 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier Components: Designator R1 R4 R6 R7 R8 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 P1 Part Type 22k / 0.125W 22k / 0.125W Short Cicuit 100k / 0.125W Designator Short Circuit R1 470nF R2 100µF R4 100nF R6 Short Circuit R7 Short Circuit R8 1µF C2 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug C9 C5 C6 C7 P1 Application Information Application n°2 : 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier Components: Designator R1 R4 R6 R7 R8 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 Part Type 110k / 0.125W 22k / 0.125W Short Cicuit 100k / 0.125W Short Cicuit 470nF 100µF 100nF Short Circuit Short Circuit 1µF 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug Application n°3 : 50Hz to 10kHz bandwidth and 10dB gain BTL power amplifier Components: Part Type 33k / 0.125W Short Circuit 22k / 0.125W Short Cicuit 100k / 0.125W Short Cicuit 470pF 150nF 100µF 100nF Short Circuit 24/30 Application Information TS4972 For Vcc=5V, a 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier you could follow the bill of material below. Components: Designator R1 Part Type 110k / 0.125W 22k / 0.125W 22k / 0.125W 110k / 0.125W 100k / 0.125W Short circuit 470nF 470nF 100µF 100nF Short Circuit Short Circuit 1µF 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug Designator C10 C12 S1, S2, S6, S7 S8 P1 Part Type Short Circuit 1µF 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug R4 R5 R6 R7 R8 C4 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 P1, P2 Application n°4 : Differential inputs BTL power amplifier In this configuration, we need to place these components : R1, R4, R5, R6, R7, C4, C5, C12. We have also : R4 = R5, R1 = R6, C4 = C5. The differential gain of the amplifier is: R1 G VDI F F = 2 ------R4 Note : Due to the VICM range (see Operating Condition), GVDIFF must have a minimum value shown in figure 84. Figure 84: Minimum Differential Gain vs Power Supply Voltage 40 35 Differential Gain min. (dB) 30 25 20 15 10 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 5.5 25/30 TS4972 ■ Note on how to use the PSRR curves (page 7) Application Information How we measure the PSRR ? Figure 86: PSRR measurement schematic We have finished a design and we have chosen the components values : • Rin=Rfeed=22kΩ • Cin=100nF • Cb=1µF Now, on fig. 13, we can see the PSRR (input grounded) vs frequency curves. At 217Hz we have a PSRR value of -36dB. In reality we want a value about -70dB. So, we need a gain of 34dB ! Now, on fig. 12 we can see the effect of Cb on the PSRR (input grounded) vs. frequency. With Cb=100µF, we can reach the -70dB value. The process to obtain the final curve (Cb=100µF, Cin=100nF, Rin=Rfeed=22kΩ) is a simple transfer point by point on each frequency of the curve on fig. 13 to the curve on fig. 12. The measurement result is shown on the next figure. Figure 85: PSRR changes with Cb Rfeed Vripple 6 VCC 1 VinVout 1 Rin Cin 7 Vin+ + RL 8 Vs- Vcc AV = -1 3 Rg 100 Ohms Bypass + Vout 2 4 Vs+ 5 Standby Bias GND TS4972 Cb 2 ■ Principle of operation • We fixed the DC voltage supply (Vcc) • We fixed the AC sinusoidal ripple voltage (Vripple) • No bypass capacitor Cs is used The PSRR value for each frequency is: -30 Cin=100nF Cb=1µF Vcc = 5, 3.3 & 2.6V Rfeed = 22k, Rin = 22k Rg = 100Ω, RL = 8Ω Tamb = 25°C R ms ( V ri ppl e ) PSRR ( dB ) = 20 x Log 10 -------------------------------------------Rms ( Vs + - Vs - ) Remark : The measure of the Rms voltage is not a Rms selective measure but a full range (2 Hz to 125 kHz) Rms measure. It means that we measure the effective Rms signal + the noise. -40 PSRR (dB) -50 Cin=100nF Cb=100µF -60 -70 10 100 1000 Frequency (Hz) 10000 100000 ■ Note on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. It's a kind of SVR in a determined frequency range. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. 26/30 Mechanical Data 4 Mechanical Data TS4972 Figure 87: TS4972 Footprint Recommendation (Non Solder Mask Defined) 500µm Φ=250µm 500µm 75µm min. 100µm max. Track Solder mask opening 500µm 500µm Φ=400µm 150µm min. Pad in Cu 35µm with Flash NiAu (6µm, 0.15µm) Figure 88: Top View Of The Daisy Chain Mechanical Data ( all drawings dimensions are in millimeters 7 Vin+ 6 Vcc 5 Stdby 8 Vout1 Vout2 4 1.6 mm Vin Gnd Bypass 1 2 2.26 mm 3 Remarks: Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested. Order Codes Package Part Number TSDC03IJT Temperature Range J -40, +85°C • DC3 Marking 27/30 TS4972 Figure 89: Tape & reel specification (top view) Mechanical Data 1 A A 1 All dimensions are in mm User direction of feed 28/30 5.1 5.1 Di e e s s zii e e Y Y + + 7 0 0 µ µ m m 4 mµ07 + X ezis eiD mµ07 + X ezis eiD 4 8 Package Mechanical Data 5 Package Mechanical Data TS4972 5.1 Flip-Chip - 8 BUMPS 0.5 0.5 1.6 0.5 ■ ■ ■ ■ ■ Die size : (2.26mm ±10%) x (1.6mm ±10%) Die height (including bumps) : 650µm ± 50 Bumps diameter : 315µm ±15µm Silicon thickness : 400µm ±25µm Pitch: 500µm ±10µm 0.5 2.26 400µm 650µm 250µm Figure 90: Pin Out (top view) Figure 91: Marking (top view) E A72 A72 YWW ■ Balls are underneath 29/30 TS4972 Revision History Date January 2003 October 2004 Revision 1 2 First Release Package Mechanical Data Description of Changes Update Mechanical Data for Flip-Chip package Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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