RBHV57009DG

HV57009 64-Channel Serial To Parallel Converter With P-Channel Open Drain Controllable Output Current Ordering Information Package Options Device 80-Lead Quad Ceramic Gullwing 80 Lead Quad Plastic Gullwing Die 80 Lead Quad Ceramic Gullwing (MIL-Std-833 Processed*) RBHV57009DG HV57009 HV57009DG HV57009PG HV57009X * For Hi-Rel process flows, refer to page 5-3 of the Databook. Features ❏ Processed with HVCMOS technology ® General Description The HV570 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rate twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source. ❏ 5V CMOS Logic ❏ Output voltage up to -85V ❏ Output current source control ❏ 16MHz equivalent data rate ❏ Latched data outputs ❏ Forward and reverse shifting options (DIR pin) ❏ Diode to VDD allows efficient power recovery ❏ Hi-Rel processing available Absolute Maximum Ratings Supply voltage, VDD1 Output Voltage, VNN Logic input levels1 Ground Current2 dissipation3 Plastic Ceramic 1 -0.5V to +7.5V VDD + 0.5V to -95V -0.3V to VDD +0.3V 1.5A 1200mW 1900mW Continuous total power Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Plastic -40°C to +85°C Ceramic -55°C to +125°C -65°C to +150°C 260°C Notes: 1. All voltages are referenced to VSS. 2. Limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic. 03/12/02 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV57009 Electrical Characteristics DC Characteristics (All voltages are referenced to VSS, VSS = 0, TA = 25°C) Symbol IDD INN IDDQ VOH VOL IIH IIL ICS Parameter VDD supply current High voltage supply current Quiescent VDD supply current High-level output Data out HVOUT Low-level output High-level logic input current Low-level logic input current HV output source current -0.1 ∆ICS HV output source current for IREF = 2.0mA 10 Data out VDD -0.5 +1 VDD +0.5 1 -1 -2 Min Max 15 -10 100 Units mA µA µA V V V µA µA mA mA % Conditions VDD = VDD, max fCLK = 8MHz Outputs off, HVOUT = -85V (total of all outputs) All inputs = VDD, except +IN = VSS = GND IO = -100µA IO = -2mA IO = 100µA VIH = VDD VIL = 0V VREF = 2V, REXT = 1K, see Figures 8a and 8b VREF = 0.1V, REXT = 1K, see Figure 8a and 8b VREF = 2V, REXT = 1K Notes 1: Current going out of the chip is considered negative. AC Characteristics (Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points] for measurements) Symbol fCLK tWL, tWH tSU tH tON, tOFF tDHL tDLH tDLE tWLE tSLE tr, tf Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time for latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse LE set-up time before clock rises Maximum allowable clock rise and fall time (10% and 90% points) 25 25 0 100 Min DC 62 10 15 500 70 70 Max 8 Units MHz ns ns ns ns ns ns ns ns ns ns CL = 15pF CL = 15pF CL = 15pF Conditions Per register 2 HV57009 Recommended Operating Conditions Symbol VDD HVOUT VIH VIL fCLK TA Logic supply voltage HV output off voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Plastic Ceramic Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above. Parameter Min 4.5 -85 VDD - 1.2V 0 DC -40 -55 Max 5.5 VDD VDD 1.2 8 +85 +125 Units V V V V MHz °C °C Figure 1: Input and Output Equivalent Circuits VDD VDD Input Data Out VSS Logic Inputs VSS Logic Data Output VDD VDD ICS PCTL Input To Internal Circuits VSS Analog Input High Voltage Output HVOUT 3 HV57009 Figure 2: Switching Waveforms VDD Data Input 50% tSU CLK 50% tWL 50% tWH 50% VSS Data Out tDLH 50% tDHL VDD VSS Data Valid tH 90% 50% 50% VSS tf tr VDD 10% 10% 90% 50% VSS VDD LE tDLE 50% tWLE 50% tSLE VDD VSS HVOUT w/ data input LOW Previous IO = IREF tOFF 90% 10% IO = 0 VDD HVOUT (off) HVOUT w/ data input HIGH 10% Previous IO = 0 tON 90% IO = IREF VDD HVOUT (off) 4 HV57009 Figure 3: Functional Block Diagram DI/O2A DI/O1A LE BL VDD I/O DIR CLK Latch SR1 Latch HVOUT1 HVOUT2 HVOUT3 • • • HVOUT32 HVOUT33 HVOUT34 HVOUT35 • • • HVOUT64 Latch SR2 Latch I/O Programmable Current DI/O2B DI/O1B VSS VBP +IN -IN Note: Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64. Figure 4: Function Table Inputs Function All O/P High Data Falls Through (Latches Tansparent) Data Stored in Latches I/O Relation Data In X L H X DI/O1-2A DI/O1-2A DI/O1-2B DI/O1-2B X CLK X LE X H H L H L L H BL L H H H H H H H DIR X X X X H H L L Shift Reg * L....L H....H * Qn→Qn+1 Qn→Qn+1 Qn→Qn-1 Qn→Qn-1 Outputs HV Outputs ON ON OFF Inversion of Stored Data New ON or OFF Previous ON or OFF Previous ON or OFF Data Out * L H * DI/O1-2B DI/O1-2B DI/O1-2A DI/O1-2A New ON or OFF Notes: * = dependent on previous stage’s state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift. H = VDD (Logic)/VNN (HV Outputs) L = VSS 5 HV57009 Figure 5: Pin Configurations 80-pin Gullwing Package Pin Pin Function 41 1 HVOUT 24 42 2 HVOUT 23 43 3 HVOUT 22 44 4 HVOUT 21 45 5 HVOUT 20 46 6 HVOUT 19 47 7 HVOUT 18 48 8 HVOUT 17 49 9 HVOUT 16 50 10 HVOUT 15 51 11 HVOUT 14 52 12 HVOUT 13 53 13 HVOUT 12 54 14 HVOUT 11 55 15 HVOUT 10 56 16 HVOUT 9 57 17 HVOUT 8 58 18 HVOUT 7 59 19 HVOUT 6 60 20 HVOUT 5 61 21 HVOUT 4 62 22 HVOUT 3 63 23 HVOUT 2 64 24 HVOUT 1 65 25 DI/O1A 66 26 DI/O2A 67 27 N/C 68 28 N/C 69 29 LE 70 30 CLK 71 31 BL 72 32 VSS 73 33 DIR 74 34 VDD 75 35 -IN 76 36 DI/O2B 77 37 DI/O1B 78 38 N/C 79 39 +IN 40 VBP 80 Function HVOUT 64 HVOUT 63 HVOUT 62 HVOUT 61 HVOUT 60 HVOUT 59 HVOUT 58 HVOUT 57 HVOUT 56 HVOUT 55 HVOUT 54 HVOUT 53 HVOUT 52 HVOUT 51 HVOUT 50 HVOUT 49 HVOUT 48 HVOUT 47 HVOUT 46 HVOUT 45 HVOUT 44 HVOUT 43 HVOUT 42 HVOUT 41 HVOUT 40 HVOUT 39 HVOUT 38 HVOUT 37 HVOUT 36 HVOUT 35 HVOUT 34 HVOUT 33 HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 Figure 6: Package Outline 64 65 41 40 Index 80 1 top view 80-pin Gullwing Package 24 25 Figure 7: Shift Register Operation HVOUT 32 • DIR = VDD; CW (HVOUT1→HVOUT64) DIR = VSS; CCW (HVOUT64→HVOUT1) HVOUT 33 • • SR1 • →CW • • • →CW SR2 HVOUT 2 HVOUT 1 Pin 25 26 36 37 • • • HVOUT 63 HVOUT 64 DIR = VDD: DIR = VSS: DI/O1A DI/O2A DI/O2A DI/O1A DI/O2B DI/O1B DI/O1B DI/O2B Notes: 1. Pin designation for DIR = VDD. 2. A 0.1µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. See Fig. 8a and 8b. 6 HV57009 Typical Current Programming Circuits 0.1µF HV570 VBP To other outputs Logic -+ IOUT HVOUT +IN -IN REXT IREF VREF RD* 10K C D* 390pF VSS VDD Since IOUT = IREF = VREF REXT Therefore, if IOUT = 2mA and VREF = -5V → REXT = 2.5KΩ. If IOUT = 1mA and REXT = 1KΩ → VREF = -1V. If REXT >10KΩ, add series network RD and CD to ground for stability as shown. This control method behaves linearly as long as the operational amplifier is not saturated. However, it requires a negative power source and needs to provide a current IREF = IOUT for each HV570 chip being controlled. If HVOUT ≥ +1V, the HVOUT cascode may no longer operate as a perfect current source, and the output current will diminish. This effect depends on the magnitude of the output current. Given IOUT and VREF, the REXT can be calculated by using: REXT = VREF IREF = VREF IOUT Figure 8a: Negative Control 0.1µF HV570 VBP VDD The intersection of a set of IOUT and VREF values can be located in the graph shown below. The value picked for REXT must always be in the shaded area for linear operation. This control method has the advantage that VREF is positive, and draws only leakage current. If REXT > 10K, add series network RD and CD to ground for stability as shown. Note: Lower reference current IREF, results in higher distortion, ∆ICS, on the output. To other outputs Logic -+ IOUT HVOUT 8 7 +IN VREF -IN REXT IREF RD* 10K CD* 390pF VSS 6 5 4 3 IOUT (mA) 100 250 500 Figure 8b: Positive Control *Required if REXT > 10K or REXT is replaced by a constant current source. REXT = 1K 2K 2 1 0 5K 1 2 3 VREF (V) 4 5 03/12/02 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com