SI1902DL-T1-E3

Si1902DL www.vishay.com Vishay Siliconix Dual N-Channel 20 V (D-S) MOSFET FEATURES SC-70 (6 leads) SOT-363 Dual D1 6 G2 5 • TrenchFET® power MOSFETs: 2.5 V rated S2 4 • 100% Rg tested • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Available 1 S1 Top View 2 G1 3 D2 D1 D2 Marking Code: PA PRODUCT SUMMARY VDS (V) 20 RDS(on) max. () at VGS = 4.5 V 0.385 RDS(on) max. () at VGS = 2.5 V 0.630 Qg typ. (nC) G2 G1 S1 N-Channel MOSFET 0.8 ID (A) f 0.70 Configuration Dual S2 N-Channel MOSFET ORDERING INFORMATION Package SC-70 Lead (Pb)-free with Tape and Reel Si1902DL-T1-E3 Lead (Pb)-free and halogen-free Si1902DL-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 20 Gate-source voltage VGS ± 12 TA = 25 °C Continuous drain current (TJ = 150 °C) a TA = 85 °C Pulsed drain current Continuous source current (diode conduction) a TA = 25 °C Maximum power dissipation a TA = 85 °C Operating junction and storage temperature range UNIT V 0.66 ID 0.48 IDM 1 IS 0.23 0.27 PD 0.14 TJ, Tstg -55 to +150 A W °C THERMAL RESISTANCE RATINGS PARAMETER Maximum junction-to-ambient a Maximum junction-to-foot (drain) SYMBOL t 5 s Steady state Steady state RthJA RthJF TYPICAL MAXIMUM 360 415 400 460 300 350 UNIT °C/W Note a. Surface Mounted on 1" x 1" FR4 board S11-2043-Rev. J, 17-Oct-11 Document Number: 71080 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902DL www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Gate threshold voltage VGS(th) VDS = VGS, ID = 250 μA 0.6 - 1.5 V Gate-body leakage IGSS VDS = 0 V, VGS = ±12 V - - ±100 nA Zero gate voltage drain current IDSS On-state drain current a ID(on) Drain-source on-state resistance a RDS(on) VDS = 16 V, VGS = 0 V - - 1 VDS = 16 VGS = 0 V, TJ = 85°C - - 5 μA VDS 3 5 V, VGS = 4.5 V 1 - - A VGS = 4.5 V, ID = 0.66 A - 0.320 0.385 VGS = 2.5 V, ID = 0.40 A - 0.560 0.630  Forward transconductance a gfs VDS = 10 V, ID = 0.66 A - 1.5 - S Diode forward voltage a VSD IS = 0.23 A, VGS = 0 V - 0.8 1.2 V Dynamic b Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Gate resistance Rg Turn-on delay time Rise time Turn-off delay time - 0.8 1.2 VDS = 10 V, VGS = 4.5 V, ID = 0.66 A - 0.06 - - 0.30 - f = 1 MHz 0.2 1 1.7 - 10 20 - 16 30 - 10 20 - 10 20 - 20 40 td(on) tr td(off) Fall time tf Source-drain reverse recovery time trr VDD = 10 V, RL = 20  ID  0.5 A, VGEN = 4.5 V, Rg = 6  IF = 0.23 A, dI/dt = 100 A/μs nC  ns Notes a. Pulse test; pulse width 300 μs, duty cycle  2% b. Guaranteed by design, not subject to production testing          Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S11-2043-Rev. J, 17-Oct-11 Document Number: 71080 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902DL www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.0 1.0 VGS = 5 V thru 2.5 V 0.8 I D - Drain Current (A) I D - Drain Current (A) 0.8 2V 0.6 0.4 0.6 0.4 TC = 125 °C 0.2 0.2 1.5 V 25 °C - 55 °C 1V 0.5 1.0 1.5 2.0 2.5 0.0 0.0 3.0 0.5 1.0 1.5 2.0 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 1.0 100 0.8 80 0.6 C - Capacitance (pF) R DS(on) - On-Resistance () 0.0 0.0 VGS = 2.5 V 0.4 VGS = 4.5 V 0.2 2.5 Ciss 60 40 Coss 20 Crss 0.0 0.0 0 0.2 0.4 0.6 0.8 1.0 0 4 ID - Drain Current (A) 8 20 1.6 5 VGS = 4.5 V ID = 0.66 A VDS = 10 V ID = 0.66 A 1.4 4 RDS(on) - On-Resistance (Normalized) VGS - Gate-to-Source Voltage (V) 16 Capacitance On-Resistance vs. Drain Current 3 2 1.2 1.0 0.8 1 0 0.0 12 VDS - Drain-to-Source Voltage (V) 0.2 0.4 0.6 Qg - Total Gate Charge (nC) Gate Charge S11-2043-Rev. J, 17-Oct-11 0.8 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature Document Number: 71080 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902DL www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.0 1 R DS(on) - On-Resistance () I S - Source Current (A) ID = 0.66 A TJ = 150 °C TJ = 25 °C 0.1 0.6 0.4 0.2 0.0 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Surge-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.2 5 0.1 4 ID = 250 µA 0 Power (W) VGS(th) Variance (V) 0.8 - 0.1 3 2 - 0.2 1 - 0.3 - 0.4 - 50 - 25 0 25 50 75 100 TJ - Temperature (°C) Threshold Voltage S11-2043-Rev. J, 17-Oct-11 125 150 0 10-3 10-2 10-1 1 Time (s) 10 100 600 Single Pulse Power, Junction-to-Ambient Document Number: 71080 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902DL www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = R thJA = 400 °C/W 3 . TJM - T A = PDMZthJA(t) Single Pulse 0.01 10-4 4. Surface Mounted 10-3 10 -2 10-1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71080 S11-2043-Rev. J, 17-Oct-11 Document Number: 71080 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SCĆ70: 6ĆLEADS MILLIMETERS 6 5 Dim A A1 A2 b c D E E1 e e1 L 4 E1 E 1 2 3 -B- e b e1 D -Ac A2 A L A1 Document Number: 71154 06-Jul-01 INCHES Min Nom Max Min Nom Max 0.90 – 1.10 0.035 – 0.043 – – 0.10 – – 0.004 0.80 – 1.00 0.031 – 0.039 0.15 – 0.30 0.006 – 0.012 0.10 – 0.25 0.004 – 0.010 1.80 2.00 2.20 0.071 0.079 0.087 1.80 2.10 2.40 0.071 0.083 0.094 1.15 1.25 1.35 0.045 0.049 0.053 0.65BSC 0.026BSC 1.20 1.30 1.40 0.047 0.051 0.055 0.10 0.20 0.30 0.004 0.008 0.012 7_Nom 7_Nom ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5550 www.vishay.com 1 AN814 Vishay Siliconix Dual-Channel LITTLE FOOTR SC-70 6-Pin MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION This technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel LITTLE FOOT power MOSFETs in the SC-70 package. These new Vishay Siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 250 mA) need to be switched, either directly or by using a level shift configuration. Vishay provides these devices with a range of on-resistance specifications in 6-pin versions. The new 6-pin SC-70 package enables improved on-resistance values and enhanced thermal performance. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the dual-channel SC-70 device in the 6-pin configuration. SOT-363 SC-70 (6-LEADS) S1 1 6 D1 G1 2 5 G2 D2 3 4 S2 applications for which this package is intended. For the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 20% when using a 1-inch square with full copper on both sides of the printed circuit board (PCB). EVALUATION BOARDS FOR THE DUAL SC70-6 The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches by 0.5 inches. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows interrogation from the outer pins to 6-pin DIP connections permitting test sockets to be used in evaluation testing. The thermal performance of the dual SC-70 has been measured on the EVB with the results shown below. The minimum recommended footprint on the evaluation board was compared with the industry standard 1-inch square FR4 PCB with copper on both sides of the board. THERMAL PERFORMANCE Top View FIGURE 1. For package dimensions see outline drawing SC-70 (6-Leads) (http://www.vishay.com/doc?71154) Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the dual SC-70 6-pin package measured as junction-to-foot thermal resistance is 300_C/W typical, 350_C/W maximum. The “foot” is the drain lead of the device as it connects with the body. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 42 lead-frame compared with a standard copper lead-frame. Junction-to-Ambient Thermal Resistance (dependent on PCB size) BASIC PAD PATTERNS See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the 6-pin SC-70. This basic pad pattern is sufficient for the low-power Document Number: 71237 12-Dec-03 The typical RθJA for the dual 6-pin SC-70 is 400_C/W steady state. Maximum ratings are 460_C/W for the dual. All figures based on the 1-inch square FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-70 package at two different ambient temperatures. www.vishay.com 1 AN814 Vishay Siliconix SC-70 (6-PIN) PD + Dual EVB Elevated Ambient 60 _C TJ(max) * TA Rq JA o o PD + 150 Co* 25 C 400 CńW PD + 312 mW PD + TJ(max) * TA Rq JA o o PD + 150 Co* 60 C 400 CńW PD + 225 mW NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.2 W. 400 Thermal Resistance (C/W) Room Ambient 25 _C 500 300 200 100 1” Square FR4 PCB 0 10-5 10-4 Testing LITTLE FOOT SC-70 (6-PIN) 1) Minimum recommended pad pattern (see Figure 2) on the EVB of 0.5 inches x 0.6 inches. 518_C/W 2) Industry standard 1” square PCB with maximum copper both sides. 413_C/W 2 10-2 10-1 1 10 100 1000 Time (Secs) To aid comparison further, Figure 2 illustrates the dual-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of RθJA for the dual 6-pin SC-70 are as follows: www.vishay.com 10-3 FIGURE 2. Comparison of Dual SC70-6 on EVB and 1” Square FR4 PCB. The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to 20%. This fact confirms that the power dissipation is restricted with the package size and the Alloy 42 leadframe. ASSOCIATED DOCUMENT Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN815, (http://www.vishay.com/doc?71334). Document Number: 71237 12-Dec-03 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead 0.067 0.026 (0.648) 0.045 (1.143) 0.096 (2.438) (1.702) 0.016 0.026 0.010 (0.406) (0.648) (0.241) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 18 Document Number: 72602 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000