SI2392DS-T1-GE3

Si2392DS Vishay Siliconix N-Channel 100 V (D-S) MOSFET FEATURES MOSFET PRODUCT SUMMARY VDS (V) 100 RDS(on) () Max. ID (A)a 0.126 at VGS = 10 V 3.1 0.144 at VGS = 6 V 2.9 0.189 at VGS = 4.5 V 2.6 Qg (Typ.) 2.9 nC DC/DC Converters / Boost Converters Load Switch LED Backlighting in LCD TVs Power Management for Mobile Computing 1 3 S APPLICATIONS • • • • TO-236 (SOT-23) G • TrenchFET® Power MOSFET • 100 % Rg and UIS Tested • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 D 2 Top View Si2392DS (E2)* * Marking Code Ordering Information: Si2392DS-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Symbol VDS VGS TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Continuous Drain Current (TJ = 150 °C) Limit 100 ± 20 3.1 2.5 2.2b,c 1.8b,c 8 2.1 1b, c 3 0.45 2.5 1.6 1.25b, c 0.8b, c - 55 to 150 ID IDM Pulsed Drain Current (t = 300 µs) Continuous Source-Drain Diode Current TC = 25 °C TA = 25 °C IS Single Pulse Avalanche Current Single Pulse Avalanche Energy L = 0.1 mH IAS EAS Maximum Power Dissipation TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C PD TJ, Tstg Operating Junction and Storage Temperature Range Unit V A mJ W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambientb, d Maximum Junction-to-Foot (Drain) 5 s Steady State Symbol RthJA RthJF Typical 75 40 Maximum 100 50 Unit °C/W Notes: a. Based on TC = 25 °C. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 166 °C/W. Document Number: 64024 S13-0793-Rev. A, 15-Apr-13 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si2392DS Vishay Siliconix MOSFET SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = 250 µA 100 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS/TJ VDS Temperature Coefficient V 59 mV/°C VGS(th) Temperature Coefficient VGS(th)/TJ ID = 250 µA Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 3 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V -1 VDS = 100 V, VGS = 0 V, TJ = 55 °C - 10 On-State Drain Currenta ID(on) Drain-Source On-State Resistancea RDS(on) Forward Transconductancea gfs VDS 5 V, VGS = 10 V - 4.8 1.2 5 µA A VGS = 10 V, ID = 2 A 0.102 0.126 VGS = 6 V, ID = 1 A 0.120 0.144 VGS = 4.5 V, ID = 1 A 0.135 0.189 VDS = 20 V, ID = 2 A 5  S b Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg 196 VDS = 50 V, VGS = 0 V, f = 1 MHz 67 VDS = 50 V, VGS = 10 V, ID = 2.2 A 5.2 10.4 2.9 5.8 14 VDS = 50 V, VGS = 4.5 V, ID = 2.2 A tr Rise Time td(off) Turn-Off Delay Time Fall Time Turn-On Delay Time 8.6 40 60 68 102 14 21 20 30 8 16 10 20 VDD = 50 V, RL = 27.7  ID = 1.8 A, VGEN = 10 V, Rg = 1  tf Fall Time 4.3 td(on) td(off) Turn-Off Delay Time VDD = 50 V, RL = 27.7  ID = 1.8 A, VGEN = 4.5 V, Rg = 1  0.9 tf tr Rise Time 1 nC 1.4 f = 1 MHz td(on) Turn-On Delay Time pF 10 20 7 14  ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current a IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C - 2.1 -8 IS = 1.8 A IF = 1.8 A, dI/dt = 100 A/µs, TJ = 25 °C A - 0.8 - 1.2 23 35 ns 21 32 nC 17 6 V ns Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 For technical questions, contact: pmostechsupport@vishay.com Document Number: 64024 S13-0793-Rev. A, 15-Apr-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si2392DS Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 8 VGS = 10 V thru 5 V VGS = 4.5 V 0.8 ID - Drain Current (A) ID - Drain Current (A) 6 VGS = 4 V 4 0.6 TC = 25 °C 0.4 2 0.2 TC = 125 °C VGS = 3 V TC = - 55 °C 0 0 0.5 1 1.5 2 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.21 280 0.17 210 C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 0 VGS = 4.5 V VGS = 6 V 0.13 VGS = 10 V 0.09 Ciss 140 Coss 70 Crss 0.05 0 2 4 ID - Drain Current (A) 6 0 8 0 20 40 On-Resistance vs. Drain Current and Gate Voltage 2 RDS(on) - On-Resistance (Normalized) VGS - Gate-to-Source Voltage (V) 8 6 VDS = 25 V VDS = 80 V 4 2 0 3 4.5 Qg - Total Gate Charge (nC) Gate Charge Document Number: 64024 S13-0793-Rev. A, 15-Apr-13 100 VGS = 10 V, 2 A ID = 2.2 A 1.5 80 Capacitance 10 0 60 VDS - Drain-to-Source Voltage (V) 6 1.7 1.4 VGS = 4.5 V, 1 A 1.1 VGS = 6 V, 1 A 0.8 0.5 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature For technical questions, contact: pmostechsupport@vishay.com www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si2392DS Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100.0 0.35 ID = 2 A RDS(on) - On-Resistance (Ω) IS - Source Current (A) 0.28 10.0 TJ = 150 °C TJ = 25°C 1.0 TJ = 125 °C 0.21 0.14 TJ = 25 °C 0.07 0.1 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 10 2.8 8 Power (W) VGS(th) (V) 2.5 ID = 250 μA 2.2 6 4 1.9 2 1.6 - 50 - 25 0 25 50 75 100 125 TA = 25 °C 0 0.01 150 0.1 1 10 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 100 1000 100 Limited by RDS(on)* ID - Drain Current (A) 10 100 μs 1 1 ms 10 ms 0.1 100 ms 10 s, 1s DC 0.01 0.001 TA = 25 °C Single Pulse 0.1 BVDSS Limited 1 10 100 1000 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area www.vishay.com 4 For technical questions, contact: pmostechsupport@vishay.com Document Number: 64024 S13-0793-Rev. A, 15-Apr-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si2392DS Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.5 ID - Drain Current (A) 2.8 2.1 1.4 0.7 0 0 25 50 75 100 125 150 0 25 TC - Case Temperature (°C) 3 1.0 2.4 0.8 1.8 0.6 Power (W) Power (W) Current Derating* 1.2 0.6 0.4 0.2 0 0.0 0 25 50 75 100 125 150 50 75 100 125 TC - Case Temperature (°C) TA - Ambient Temperature (°C) Power, Junction-to-Foot Power, Junction-to-Ambient 150 * The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 64024 S13-0793-Rev. A, 15-Apr-13 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si2392DS Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 PDM 0.05 t1 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 166 °C/W 3. TJM - TA = PDMZthJA(t) 0.01 10 -4 4. Surface Mounted Single Pulse 10 -3 10 -2 10 -1 1 100 10 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64024. www.vishay.com 6 For technical questions, contact: pmostechsupport@vishay.com Document Number: 64024 S13-0793-Rev. A, 15-Apr-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 1 E 2 e S e1 D 0.10 mm C 0.004" A2 A C q Gauge Plane Seating Plane Seating Plane C A1 Dim 0.25 mm L L1 MILLIMETERS Min INCHES Max Min Max 0.044 A 0.89 1.12 0.035 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 e 0.95 BSC e1 L 1.90 BSC 0.40 L1 q 0.0748 Ref 0.60 0.016 0.64 Ref S 0.024 0.025 Ref 0.50 Ref 3° 0.055 0.0374 Ref 0.020 Ref 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 09-Jul-01 www.vishay.com 1 AN807 Vishay Siliconix Mounting LITTLE FOOTR SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. ambient air. This pattern uses all the available area underneath the body for this purpose. 0.114 2.9 0.081 2.05 0.150 3.8 0.059 1.5 0.0394 1.0 0.037 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the Document Number: 70739 26-Nov-03 Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. www.vishay.com 1 Application Note 826 Vishay Siliconix 0.049 (1.245) 0.029 0.022 (0.559) (0.724) 0.037 (0.950) (2.692) 0.106 RECOMMENDED MINIMUM PADS FOR SOT-23 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72609 Revision: 21-Jan-08 www.vishay.com 25 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000