SIC453ED-T1-GE3

SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix 4.5 V to 20 V Input, 15 A, 25 A, 40 A microBuck® DC/DC Converter With PMBus Interface FEATURES • Versatile LINKS TO ADDITIONAL RESOURCES Evaluation Boards Design Tools DESCRIPTION The SiC45x is a PMBus 1.3 compliant non-isolated DC/DC buck regulator with integrated MOSFETs. It is capable of supplying up to 40 A (SiC450) continuous output current. Its output voltage is digitally adjustable from 0.3 V to 12 V from a 4.5 V to 20 V input with switching frequencies up to 1.5 MHz. SiC45x architecture delivers ultrafast transient response with minimum output capacitance and tight regulation over a broad load range. The device has integrated internal compensation and is stable with any type of output capacitor. The device incorporates a power saving scheme that significantly increases light load efficiency. The SiC45x allows power block configuration programs to be stored in non volatile memory (NVM). Various operation parameters can all be locally stored and used to determine fault behavior. Operation is firmware based and is field upgradable Pinstrap option is also available for default configuration without PMBus. The SiC45x is available in lead (Pb)-free power enhanced MLP 5 mm x 7 mm package. APPLICATIONS • • • • Server, cloud, and infrastructure Networking, telecom, storage applications Distributed point of load power architectures DDR memory Axis Title 98 TYPICAL APPLICATION CIRCUIT 96 94 BOOT PGOOD EN VIN PVIN PVCC SiC45x PH SW VSEN+ VSEN- VDD ADDR SALRT VSET SCL AGND SDA PGND RT/SYNC VOUT 2nd line eff - Efficiency (%) PGOOD ENABLE INPUT 4.5 V to 20 V 10000 1000 92 2.5 Vo 90 3.3 Vo 5 Vo 1st line 2nd line Design Tool - Single supply operation from 4.5 V to 20 V input voltage - Scalable solution with continuous output current of 40 A (SiC450), 25 A (SiC451), 15 A (SiC453) - Adjustable output voltage from 0.3 V to 12 V - Built in 5 V regulator for internal circuits and driver supply - 1 % output voltage accuracy over temperature - Ultrafast transient response • Highly efficient - 98 % peak efficiency - Optional power save mode • Highly configurable - PMBus 1.3 compliant with 1 MHz bus speed - Internal NVM - VOUT adjustability and reading resolution of 2 mV - Supports over 50 PMBus commands - Supports in phase or 180° out of phase synchronization - Output voltage source and sink capability • Robust and reliable - PVIN, VOUT, IIN and IOUT and temperature reporting - Over current protection in pulse-by-pulse mode - Output over and under voltage protection - Over temperature protection with hysteresis - Differential output remote sensing 88 86 100 VIN = 12 V Fsw = 600 kHz 84 82 80 10 0 5 10 15 20 25 30 35 40 IOUT - Output Current (A) Fig. 1 - Typical Application Circuit S21-0213-Rev. B, 08-Mar-2021 Fig. 2 - SiC450 Efficiency Curve Document Number: 77863 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PIN CONFIGURATION NC 9 NC 8 AGND 7 BOOT 6  GH 5 PH 4 PVIN 3 PVIN 2 PVIN 1  10 NC 11 VSEN12   VSEN+ 13 PGOOD 14 ADDR 15 VSET 16 AGND  17 RT / SYNC  18 SALRT PVIN 34 PGND 33 PGND 32  SW 31  19 SDA  20 SCL 21 EN 22 VDD 23 VIN 24 PVCC 25 GL 26 SW 27 SW 28 SW 29 SW 30 SW Fig. 3 - Pin Configuration - Bottom View PIN DESCRIPTION PIN NUMBER 1, 2, 3, 34 SYMBOL PVIN DESCRIPTION Input voltage for power stage 4 PH Phase node, return path of high side gate driver 5 GH High side MOSFET gate monitor 6 BOOT 7, 16 AGND Bootstrap voltage for high side gate driver (referenced to PH) Analog signal return ground 8 NC Not used in Vishay device 9 NC Not used in Vishay device 10 NC 11 VSEN- Remote sense amplifier negative input connect to output ground 12 VSEN+ Remote sense amplifier positive input connect to output 13 PGOOD Power good; open-drain output indicating VOUT is within set limits. Connect a pull up resistor typically 10 kΩ to VDD 14 ADDR PMBus address programming pin 15 VSET 17 RT/SYNC 18 SALRT 19 SDA 20 SCL PMBus clock. Connect to external host interface 21 EN Enable pin. Active high 5 V logic level input Not used in Vishay device Output voltage set point by connecting a resistor from VSET to AGND Clock synchronization pin. Frequency can be set by connecting a resistor to AGND. Pending on master / salve configuration, a clock can be send / receive via the pin PMBus alert. Connect to external host interface if desired PMBus data. Connect to external host interface 22 VDD Internal 5 V circuits supply voltage. VDD is a LDO output, connect a 1 μF decoupling capacitor to AGND 23 VIN Internal driver supply voltage 24 PVCC Supply voltage for internal gate drive. PVCC is a LDO output. Connect a 4.7 μF decoupling capacitor to PGND 25 GL Low side MOSFET gate monitor 26 to 31 SW Switch node 32, 33 PGND Power ground. Common return for internal MOSFETs ORDERING INFORMATION PART NUMBER SiC450ED-T1-GE3 PART MARKING MAXIMUM CURRENT PACKAGE SiC450 40 A PowerPAK MLP34-57 SiC450EVB SiC451ED-T1-GE3 Reference board SiC451 SiC451EVB SiC453ED-T1-GE3 SiC453EVB S21-0213-Rev. B, 08-Mar-2021 25 A PowerPAK MLP34-57 Reference board SiC453 15 A PowerPAK MLP34-57 Reference board Document Number: 77863 2 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PART MARKING INFORMATION = pin 1 indicator P/N P/N = = Siliconix logo LL = ESD symbol F = assembly factory code Y = year code WW = week code LL = lot code FYWW part number code ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) ELECTRICAL PARAMETER PVIN, VIN SW / PH SW / PH (AC) BOOT BOOT to SW Drive supply voltage (PVCC) Bias supply voltage (VDD) AGND to PGND All other pins Temperature Junction temperature Storage temperature Power Dissipation Junction-to-ambient thermal impedance (RthJA) Thermal resistance from junction to case (RthJ-C) Thermal resistance from junction to PCB (RthJ-PCB) ESD Protection Electrostatic discharge protection CONDITIONS LIMITS UNIT Reference to PGND Reference to PGND Reference to PGND (100 ns) -0.3 to +28 -0.3 to +28 -8 to +33 -0.3 to VPH + PVCC -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to +0.3 -0.3 to VDD + 0.3 V -40 to +150 -65 to +150 °C 24 4.5 5 °C/W 2 750 kV V Reference to AGND HBM CDM Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating / conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V) ELECTRICAL PARAMETER MIN. TYP. MAX. UNIT PVIN, VIN Logic pins VOUT Drive supply voltage (PVCC) Bias supply voltage (VDD) Temperature Recommended ambient temperature Operating junction temperature 4.5 0 0.3 4.75 4.75 5 5 20 5.5 12 5.25 5.25 V S21-0213-Rev. B, 08-Mar-2021 -40 to +85 -40 to +125 °C Document Number: 77863 3 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (PVIN = 12 V, TJ = -40 °C to +125 °C, unless otherwise specified) PARAMETER Power Supplies PVIN, VIN VIN_ON, default VIN_OFF, default PVCC supply VDD supply PVCC UVLO threshold PVCC UVLO hysteresis Input current Shutdown current PVIN Monitoring PVIN monitor accuracy PVIN min. monitor resolution PVIN monitor full scale PVIN read frequency IIN Fault Response Time IIN fault response time Pin (Input power) Pin sense accuracy Pin sense resolution Output Voltage VOUT default set-point VOUT set-point accuracy VOUT set-point range VOUT set-point resolution Line regulation Load regulation VOUT min. monitor resolution VOUT start up delay range SYMBOL TEST CONDITIONS PVIN, VIN VIN_ON VIN_OFF VPVCC VDD Default setting Default setting VIN = 4.5 V to 20 V Logic supply voltage VPVCC_UVLO_TH VPVCC_UVLO_HYS IVIN IVIN_SDN TJ = 25 °C, non-switching, no load, VOUT > VSET, IPVCC + IPVDD + IPVIN EN = 0 V, IPVCC + IPVDD + IPVIN VPVIN_MON_ACC VPVIN_MON_RSO VPVIN_MON_SCL tPVIN_RSP LIMITS UNIT MIN. TYP. MAX. 4.5 4.5 4.5 3.4 - 10 9 5 5 3.6 300 20 5.5 5.5 3.8 - - 3.5 6 - 2.5 6 - 3 70 78 28 - % mV V Hz V mV mA tIIN_RSP IIN_OC_WARN - 78 - Hz PPVIN_SNS_ACC PPVIN_SNS_RSO 5 W to 160 W - 5 0.5 - % W VOUT VOUT_ACC VOUT_RNG VOUT_RSO VOUT_REG VOUT_REG VSET resistor = OPEN or SHORT Measured as ΔV (VSEN+ – VSEN-) VOUT scale loop = 1 From PVIN valid until 1st PWM pulse 0.6 2 1 1 5 0 1 12 - V % V mV VOUT_MON_RSO tS_DLY_RNG -1 0.3 - % mV ms VSEN+ common mode range VVSNS_RNG -0.2 - 12 V VSEN- common mode range VOUT read conversion frequency Controller and Timing Minimum on-time Minimum off-time tON accuracy Frequency, default Frequency setting range VOUT Soft Start / Soft Stop tON rise, default tON rise, setting range tOFF fall, default tOFF fall, setting range tON delay, default tON delay, setting range tOFF delay, default tOFF delay, setting range tON max. fault limit, default tON max. fault limit, setting range VVSNS_RNG tVOUT_RSP -200 - 78 200 - mV Hz tON_MIN tOFF_MIN tON_ACC fSW fSW_RNG -10 540 300 50 250 600 - 10 660 1500 0 0 0 0 0 5 5 0 0 20 - 127 127 127 127 127 S21-0213-Rev. B, 08-Mar-2021 tON_RISE tON_RNG tSSP tSSP,RNG tON_DLY tON_DLY,RNG tOFF_DLY tOFF_DLY,RNG tmax_FLT tmax_FLT,RNG CCM mode From VOUT = 0 V to VOUT set point From VOUT = 0 V to VOUT set point ns % kHz ms Document Number: 77863 4 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (PVIN = 12 V, TJ = -40 °C to +125 °C, unless otherwise specified) PARAMETER Enable EN pull down resistance RT/SYNC Logic high level Logic low level Input minimum pulse width Sync switching Power Good Power good output rising threshold Power good output falling threshold Power good hysteresis Power good on resistance SYMBOL TEST CONDITIONS MAX. REN - 5 - VRT/SYNC_HI VRT/SYNC_LO tIN Pulse_min FSYNC 2 300 100 - 0.8 1500 - 90 - VFB_FALLING_TH - 85 - VFB_HYST - 5 - RPG - 5.5 - Ω - 25 100 - μs -40 -5 - 1 125 35 +150 +5 - °C 2 - 0.1 5 0.8 - - 56 35 21 115 80 - -3 - 3 -15 -6 -5 -9 -4 -3 - 15 6 5 9 4 3 -6 - 6 -7 - 7 -12 -4 -3 -9 -4 -3 - 12 4 3 9 4 3 VFB_RISING_TH Default value respect to VOUT default setting = 0.6 V Valley current limit, default IOCP SiC450 (40 A), TJ = -40 °C to +85 °C SiC451 (25 A), TJ = -40 °C to +85 °C SiC453 (15 A), TJ = -40 °C to +85 °C Output OVP threshold, default Output UVP threshold, default Telemetry VOVP VUVP VOUT with respect to VSET VIN VIN IIN IIN PIN PIN VOUT IOUT IOUT POUT POUT S21-0213-Rev. B, 08-Mar-2021 UNIT TYP. Power good delay time (rising) tPG_RISE_DLY Power good delay time (falling) tPG_FALL_DLY Temperature Monitor and Temperature Shutdown Monitoring resolution TMON_RSO Monitoring range TMON_RNG Monitoring accuracy TMON_ACC Thermal shutdown TSD Thermal shutdown hysteresis TSD_HYS Digital Inputs (ADDR, SALRT, SCLK, SDA, EN) Input high threshold VIH Input low threshold VIL Input hysteresis VHYST Pin capacitance CPIN Fault Protections VOUT LIMITS MIN. Load current, 20 % to 100 % (TA = -40 °C to +125 °C) 20 % of load current (TA = 25 °C) 50 % of load current (TA = 25 °C) 100 % of load current (TA = 25 °C) 20 % of load current (TA = 25 °C) 50 % of load current (TA = 25 °C) 100 % of load current (TA = 25 °C) 2 V < VOUT < 5.5 V, load current, 20 % to 100 % (TA = -40 °C to +125 °C) 0.5 V < VOUT < 2 V, load current, 20 % to 100 % (TA = -40 °C to +125 °C) 20 % of load current (TA = 25 °C) 50 % of load current (TA = 25 °C) 100 % of load current (TA = 25 °C) 20 % of load current (TA = 25 °C) 50 % of load current (TA = 25 °C) 100 % of load current (TA = 25 °C) MΩ V ns kHz % V pF A % % Document Number: 77863 5 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM V IN PVCC VDD Charge pump PFD BOOT Ramp generator Differential amplifier PWM comparator tON generator OTA Rcomp Ccomp Bandgap VSET VSET ADC ADDR ADC High side driver PEC/BUS management PMBus interface SCLK Control logic Over current protection Fault management Monitoring compensation PIN / POUT calculation ADC Monitoring sense circuits PVCC Low side driver Command registers 1K NVM SDA PH SW Minimum tOFF Cp Reference generator and DAC SALRT A GND PV IN PVCC VDD UVLO SW VSEN- UVLO Linear regulator RT / SYNC V SEN+ EN PGND Zero crossing detector PGOOD circuit PGOOD Fig. 4 - Functional Block Diagram S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 6 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix OPERATIONAL DESCRIPTION Device Overview SiC45x is a high efficiency synchronous buck regulator capable of delivering up to 25 A continuous current. The device has programmable switching frequency of 300 kHz to 1.5 MHz. The control scheme delivers fast transient response and minimizes external components. Thanks to the internal current ramp information, no high ESR output bulk or virtual ESR network is required for the loop stability. This device also incorporates a power saving feature by enabling diode emulation mode and frequency fold back as the load decreases. PVIN PVIN SW Constant on time PWM generator In addition, a built in PLL allows in phase or 180° out of phase synchronization under master / slave configuration. OTA CP SiC45x has a full set of protection and monitoring features with response that can be set with PMBus: • Power good open drain output This device is available in MLP34-57 package to deliver high power density and minimize PCB area. PWM Control Mechanism SiC45x employs a voltage - mode COT control mechanism. During steady-state operation, feedback voltage is compared with internal reference and the amplified error signal (VCOMP) is generated in the internal comp node. An internally generated ramp signal and VCOMP are fed into a comparator. Once VRAMP crosses VCOMP, a single shot on-time pulse is generated for a fixed time, programmed by the external Rfsw. During the on-time pulse, the high side MOSFET will be turned on. Once the on-time pulse expires, the low side MOSFET will be turned on after a break-before-make period. The low side MOSFET will be on for duration of minimum off-time pulse until VRAMP crosses VCOMP. The cycle is then repeated. Fig. 5 illustrates the basic block diagram for VM-COT architecture. In this architecture the following is achieved: • The reference of a basic ripple control regulator is replaced with a high again error amplifier loop • This establishes two parallel voltage regulating feedback paths, a fast and slow path • Fast path is the ripple injection which ensures rapid correction of the transient perturbation • Slow path is the error amplifier loop which ensures the DC component of the output voltage follows the internal accurate reference voltage S21-0213-Rev. B, 08-Mar-2021 REF VSEN- AGND Fig. 5 - VM-COT Block Diagram • Output over voltage protection • Dedicated enable pin for easy power sequencing Rcomp Differential amplifier Ccomp • Over current protection in pulse-by-pulse mode • Over temperature protection with hysteresis VSEN+ Ramp generator Comparator • Output under voltage protection Load PGND All components for RAMP signal generation and error amplifier compensation required for the control loop are internal to the IC, see Fig. 5. In order for the device to cover a wide range of VOUT operation, the internal RAMP signal components are automatically selected depending on the VOUT voltage and switching frequency. The error amplifier internal compensation consists of a resistor in series with a capacitor (RCOMP, CCOMP). Fig. 6 demonstrates the basic operational waveforms: Basic operational waveforms VRAMP VCOMP PWM Fixed on-time Fig. 6 - VM-COT Operational Principle Light Load Condition To improve efficiency at light-load condition, SiC45x provide a set of innovative implementations to eliminate LS recirculating current and switching losses. The internal zero crossing detector monitors SW node voltage to determine when inductor current starts to flow negatively. In power saving mode, as soon as inductor valley current crosses zero, the device deploys diode emulation mode by turning off low side MOSFET. If load further decreases, switching frequency is reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. The switching frequency is set by the controller to Document Number: 77863 7 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix maintain regulation. In the standard power save mode, there is no minimum switching frequency. If ultrasonic mode is selected via PMBus, the minimum switching frequency that the regulator will reduce to is > 20 kHz as the part avoids switching frequencies in the audible range. Power Stage SiC45x integrates a high performance power stage with a 4 mΩ n-channel high side MOSFET and a 1.4 mΩ n-channel low side MOSFET. The MOSFETs are optimized to achieve up to 96 % efficiency. The power input voltage (PVIN) can go up to 20 V and down as low as 4.5 V. The output voltage must always be less than the input voltage. pulses in a row, secondary level OC fault is recognized and both HS and LS MOSFETs are turned off. The device continues restart attempt in a delay time until the OC fault condition no longer exists. The consecutive switching pulse in a row, the delay time, and other types of fault responses can be programmed via PMBus (see PMBus command section). The default number is 128 for counting consecutive switching pulse in a row. The default delay time is 20 ms. The OCP is enabled immediately after VDD passes UVLO level. Sequencing of Input / Output Supplies SiC45x has no sequencing requirements on any of its input / output, PVIN, PVCC, VIN, VDD and EN. VIN is internal supply voltage and is used to implement on time of COT control. VIN shall be directly connected to PVIN. OCPthreshold Iload Iinductor EN The SiC45x has an EN pin to turn the part on and off. Driving this pin high enables the device, while grounding it turns it off. There are no sequencing requirements with respect to input / output supplies. GH Skipped GH pulse Fig. 7 - Over-Current Protection Illustration Output Overcurrent Protection (OCP) Output Undervoltage Protection (UVP) SiC45x has pulse-by-pulse overcurrent (OC) limit control. The inductor valley current is monitored during low-side (LS) FET turn-on period through RDS(on) sensing. After a pre-defined blanking time, the valley current is compared with an internal OCP threshold named IOUT_OC_FAULT_LIMIT, which can be programmed via PMBus. Once monitored valley current is larger than IOUT_OC_FAULT_LIMIT, a pulse-by-pulse over-current limit is broken, high-side (HS) turn-on pulse is skipped and LS FET is kept on until the inductor valley current returns below OCP limit as illustrated by Fig. 7. UVP is implemented by monitoring the output voltage. If the output voltage drops below a threshold voltage VOUT_UV_FAULT_LIMIT (VUFL), the output-undervoltage (UV) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device continues restart attempt in a delay time until the UV condition no longer exists. An equation is given in (1) to calculate IOUT_OC_FAULT_LIMIT from steady-state value of DC load current when OCP happens. The VUFL and the delay time can be programmed via PMBus (see PMBus command section). The default value of VUFL is 20 % less than the target VOUT. The default delay time is 20 ms. The UVP is only active after the completion of soft-start sequence. Output-Overvoltage Protection (OVP) IOUT_OC_FAULT_LIMIT = ( PV IN – V OUT ) × V OUT I OUT_OCP – ---------------------------------------------------------2 × L × PV IN × f SW (1) where: IOUT_OC_FAULT_LIMIT is the OCP threshold to be programmed via PMBus; IOUT_OCP is the steady-state value of DC load current when pulse-by-pulse OC event happens; PVIN is the input voltage for power stage; VOUT is the output voltage for power stage; L is inductance of power inductor; and fSW is switching frequency for power stage. OVP is implemented by monitoring the output voltage. If the output voltage is above a threshold voltage VOUT_OV_FAULT_LIMIT (VOFL), the output-overvoltage (OV) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device restarts when the OV fault condition no longer exists. The UVFL can be programmed via PMBus (see PMBus command section). The default value of VOFL is 15 % more than the target VOUT. The OVP is enabled immediately after VDD passes UVLO level. SiC45x also provides secondary level OCP protection. If the pulse-by-pulse overcurrent limit is persistently broken for more than a specific number of consecutive switching S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 8 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Input-Overvoltage Protection (VIN-OVP) VIN-OVP is implemented by monitoring the input voltage. When the input voltage is pulled above a threshold voltage VIN_OV_FAULT_LIMIT (VIN-OFL), the input-overvoltage (VIN-OV) fault condition is recognized and both the HS and LS MOSFETs are turned off. When the input voltage is pulled below the VIN-OFL, the VIN-OV fault condition no longer exists and the device restarts. The VIN-OFL can be programmed via PMBus (see PMBus command section). The default value of VIN-OFL is 15 V. The VIN-OVP is enabled immediately after VDD passes UVLO level. Input-Undervoltage Protection (VIN-UVP) VIN-UVP is implemented by monitoring the input voltage. When the input voltage is pulled below a threshold VIN_OFF, the input-undervoltage (VIN-UV) fault condition is recognized and both the HS and LS MOSFETs are turned off. When the input voltage is pulled above a threshold VIN_ON, the VIN-UV fault condition no longer exists and the device restarts. The VIN-OFF and VIN_ON can be programmed via PMBus (see PMBus command section). The default value of VIN-OFF is 9 V. The default value of VIN_ON is 10 V. The VIN-UVP is enabled immediately after VDD passes UVLO level. tON-MAX. Protection (tMP) SiC45x has power up time limit control. When the device does not power up the output voltage above the VUFL in a time interval longer than tON_MAX_FAULT_LIMIT (tMFL), the tON-MAX. (tM) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device continues restart attempt after the shutdown in a delay time until the tM fault no longer exists. The tMFL and delay time can be programmed via PMBus (see PMBus command section). The default value of tMFL is 20 ms. The default delay time is 20 ms. Fig. 8 - Pre-Bias Start-Up Output Voltage Setting Connecting a resistor from VSET to AGND will set output voltage (VOUT), eight VOUT related warning and fault voltage limits, and the value of VOUT_SCALE_LOOP as listed in the “VOUT_SCALE_LOOP look up” table. See below table for the list of supported output voltage (VOUT) set by the VSET resistor value. After VOUT is set by the resistor, the voltage level of eight VOUT related warning and fault limits defined by PMBus and the VOUT_SCALE_LOOP register are automatically set also. See below table for the list of the eight VOUT related warning and fault limits set by VOUT setting resistor. Please do not leave the setting resistor open or short, or contact Vishay for technical support. The resistor setting VOUT or anyone of the eight VOUT related warning and fault limits can be separately overridden by a PMBus command with resolution 1.953 mV (see PMBus command table). OUTPUT VOLTAGE SETTINGS VSET RESISTOR (kΩ) VOUT (V) 0.845 0.60 1.30 0.90 1.78 0.95 2.32 1.00 2.87 1.05 3.48 1.20 4.12 1.25 4.75 1.50 5.49 1.80 The OFL can be programmed via PMBus (see PMBus command section). The default value of OFL is 125 °C. 6.19 2.10 6.98 2.50 The OTP is enabled immediately after VDD passes UVLO level. 7.87 3.30 The tMP is enabled immediately after VDD passes UVLO level. Overtemperature Protection (OTP) SiC45x has internal thermal monitor block to support device temperature control. When the device temperature rises above OT_FAULT_LIMIT (OFL), the overtemperature (OT) fault condition is recognized and both the HS and LS MOSFETs are turned off. When OT fault condition no longer exists, the device restarts. Pre-Bias Start-Up 8.87 5.00 11.0 12.00 VOUT is monitored through differential output voltage sense pins Vsen+ and Vsen-. If the sensed voltage is higher than VSET, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 9 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com VOUT RELATED WARNINGS AND FAULTS Vishay Siliconix VOLTAGE LEVEL FREQUENCY SETTINGS RT RESISTOR (kΩ) FREQUENCY (kHz) 0.845 300 1.30 400 1.78 500 2.32 550 2.87 600 3.48 650 4.12 700 4.75 750 RT/SYNC PIN and Mode of Switching Configuration 5.49 800 The SiC45x has an RT / SYNC pin. This pin can be used to set the switching frequency and to send or receive a clock signal for synchronization between a master and slave. SiC45x will inject less than 1 mA DC current across the RT/SYNC pin to the ground during initial power up process, and connecting a resistor from the RT/SYNC pin to ground will be used to set the switching frequency according to the table listed below. The following table shows the supported frequency settings by the RT resistor value. Please do not leave the setting resistor open or short, or contact Vishay for technical support. The frequency set by the external resistor can be overridden by a PMBus command with resolution 50 kHz (see PMBus command table). 6.19 850 6.98 900 POWER_GOOD_ON 90 % VOUT POWER_GOOD_OFF 85 % VOUT VOUT_OV_FAULT_LIMIT 115 % VOUT VOUT_OV_WARN_LIMIT 110 % VOUT VOUT_UV_WARN_LIMIT 90 % VOUT VOUT_UV_FAULT_LIMIT 80 % VOUT VOUT_MARGIN_LOW 95 % VOUT VOUT_MARGIN_HIGH 105 % VOUT 7.87 950 8.87 1000 10 1250 11 1500 SiC45x supports four modes of switching configuration, including standalone mode, master mode, slave mode in phase, and slave mode 180° out of phase. The master mode is default one of switching configuration and user can override it to be either standalone mode, slave mode in phase, or slave mode 180° out of phase by PMBus command INTERLEAVE (see PMBus command table). The following table introduces four modes of switching configuration, recommended RT/SYNC pin connections, and content of related PMBus command INTERLEAVE. MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus MODE DESCRIPTION SWITCHING FREQUENCY AND RECOMMENDED RT/SYNC PIN CONNECTION SWITCHING PHASE INTERLEAVE COMMAND Chip works individually Cross a resistor RRT from RT / SYNC pin to ground. During power up, less than 1 mA DC current will be injected into resistor RRT to determine default switching frequency. The default switching frequency can be overridden by PMBus command. After power up, RT / SYNC pin is released and connected to ground via RRT. Self determined 0x0000 Chip works as a master chip outputting a clock signal in phase with its switching to drive an external slave chip’s switching frequency and phase Cross a resistor RRT from RT / SYNC pin to ground. During power up, less than 1 mA DC current will be injected into resistor RRT to determine default switching frequency. The default switching frequency can be overridden by PMBus command. After power up, RT / SYNC pin outputs a 50 % duty cycle pulse signal toggling between 0 and VDD, which is in phase with the chip’s switching node. Self determined 0x0100 Cross a resistor RRT from RT / SYNC pin to ground. During power up, less than 1 mA DC current will be injected into resistor RRT to determine default switching frequency. The Chip works as a slave default switching frequency can be overridden by PMBus In phase with the chip receiving an external command. When there is an external clock signal external clock, or clock signal and presented at the RT / SYNC pin, the switching frequency self determined Slave in phase synchronize its switching will be overridden and the chip’s switching node is in when individually in phase with the clock phase with the external clock signal. If the external clock works signal signal comes from a SiC45x working in master mode switching configuration, the resistor RRT shall be same to the RRT used by the master chip. 0x0120 MODE TYPE Standalone Master S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 10 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus MODE TYPE Slave 180 ° out of phase MODE DESCRIPTION SWITCHING FREQUENCY AND RECOMMENDED RT/SYNC PIN CONNECTION SWITCHING PHASE INTERLEAVE COMMAND Cross a resistor RRT from RT / SYNC pin to ground. During power up, less than 1 mA DC current will be injected into resistor RRT to determine default switching frequency. The Chip works as a slave 180° out of phase default switching frequency can be overridden by PMBus chip receiving an external with the external command. When there is an external clock signal clock signal and clock, or self presented at the RT / SYNC pin, the switching frequency synchronize its switching determined when will be overridden and the chip’s switching node is 180° 180 ° out of phase with individually out of phase with the external clock signal. If the external the clock signal works clock signal comes from a SiC45x working in master mode switching configuration, the resistor RRT shall be same to the RRT used by the master chip 0x0121 PMBus ADDRESS (ADDR pin) The SiC45x has a 7-bit register that are used to set the base PMBus address of the device. A resistor assembled between ADDR pin and ground sets an offset from the default pre-configured MFR base address in the memory. Up to 15 different offsets can be set allowing 15 SiC45x devices with unique addresses in a single system. This offset and therefore the device address is read by the ADC during the initialization sequence. The table below provides the resistor values needed to set the 15 offsets from the base address. Please do not leave the setting resistor open or short, or contact Vishay for technical support. MFR_BASE_ADDRESS Vishay provides another 15 options of PMBus address listed in table of MFR_BASE_ADDRESS_2. Please contact Vishay for technical support. MFR_BASE_ADDRESS_2 CONNECTION ADDRESS HEX [3 : 0] NVM [6 : 4] BIN [6 : 0] 0.845K 1 0 101b 1010 000b 1.3K 2 1 101b 1010 001b 1.78K 3 2 101b 1010 010b 2.32K 4 3 101b 1010 011b 2.87K 5 4 101b 1010 100b 3.48K 6 5 101b 1010 101b 4.12K 7 6 101b 1010 110b CONNECTION ADDRESS HEX [3 : 0] NVM [6 : 4] BIN [6 : 0] 0.845K 1 0 001b 0010 000b 4.75K 8 7 101b 1010 111b 0010 001b 5.49K 9 8 101b 1011 000b 0010 010b 6.19K 10 9 101b 1011 001b 0010 011b 6.98K 11 A 101b 1011 010b 0010 100b 7.87K 12 B 101b 1011 011b 0010 101b 8.87K 13 C 101b 1011 100b 14 D 101b 1011 101b 15 E 101b 1011 110b 1.3K 1.78K 2.32K 2.87K 3.48K 2 3 4 5 6 1 2 3 4 5 001b 001b 001b 001b 001b 4.12K 7 6 001b 0010 110b 10K 4.75K 8 7 001b 0010 111b 11K 5.49K 9 8 001b 0011 000b 6.19K 10 9 001b 0011 001b 6.98K 11 A 001b 0011 010b 7.87K 12 B 001b 0011 011b 8.87K 13 C 001b 0011 100b 10K 14 D 001b 0011 101b 11K 15 E 001b 0011 110b S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 11 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PMBus COMMAND LIST ADDRESS 01h PMBus COMMAND NAME OPERATION TYPE R/W DATA FORMAT (UNITS) - [7 : 5] 000: reserved [4] 1: no power up until commanded by the CONTROL and OPERATION [3] 1: to start, the unit requires on/off portion of the OPERATION 1Fh command (0001,1111) [2] 1: to start, the unit requires CONTROL asserted [1] 1: active high to start the unit [0] 1: turn off VOUT as fast as possible, ignore TOFF_DELAY and TOFF_FALL - R/W Byte 03h CLEAR_FAULTS Write - Write VALID RANGE Byte ON_OFF_CONFIGURATION WRITE_PROTECT DEFAULT [7] 1: PMBus unit output is on [6] 0: output is turned off immediately and any power down sequencing commads are ignored [5 : 4] 00: VOUT set by VOUT_COMMAND [3 : 2] 10: faults caused by selecting VOUT_MARGIN_HIGH or 88h VOUT_MARGIN_LOW (1000,1000) as the nominal output voltage source are acted upon according to the settings of the VOUT_OV_FAULT_RESPONSE and VOUT_IV_FAULT_RESPONSE data bytes [1] 0: not used [0]: reserved 02h 02h 10h DEFAULT VALUE IN NVM Byte - - 00h [7 : 0]: 0000,0000: (0000,0000) allows write to all registers - 15h STORE_USER_ALL Write - - - - 16h RESTORE_USER_ALL Write - - - - 19h CAPABILITY Read Byte [7] 1: packet error checking is supported [6 : 5] 10: maximum supported bus speed is 1 MHz [4] 1: the unit has SMBALERT# pin D0h and supports SMBus alert response (1101,0000) protocol [3] 0: numeric data is in LINEAR11, LINEAR16, or DIRECT format [2] 0: AVSBUS not supported [1 : 0] 00: reserved 1Bh SMBALERT_MASK R/W Block 0x0000 (0000,0000, 0000,0000) - 20h VOUT_MODE Read [7 : 5] 000: the unit uses LINEAR16 format for VOUT related commands 17h LINEAR16 [4 : 0] 1,0111: five bit two is (V) (0001,0111) complement exponent equals -9 for VOUT related commands 21h VOUT_COMMAND R/W 0133h LINEAR16 (0000,0001, (V) 0011,0011) S21-0213-Rev. B, 08-Mar-2021 0.6 V - - - 0.3 V to 14 V, 1.953 mV resolution Document Number: 77863 12 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PMBus COMMAND LIST ADDRESS PMBus COMMAND NAME TYPE DATA FORMAT (UNITS) DEFAULT VALUE IN NVM This command deviates from xxxxh standard PMBus 1.3 specifications; (xxxx,xxxx, a factory trim value varying by xxxx,xxxx) devices DEFAULT VALID RANGE -2 V to 2 V, 1.953 mV resolution 22h VOUT_TRIM R/W LINEAR16 (V) 24h VOUT_MAX R/W 1C00h LINEAR16 (0001,1100, (V) 0000,0000) 14 V 0.3 V to 14 V, 1.953 mV resolution 25h VOUT_MARGIN_HIGH R/W 0142h LINEAR16 (0000,0001, (V) 0100,0010) 0.63 V 0.3 V to 14 V, 1.953 mV resolution 26h VOUT_MARGIN_LOW R/W 0123h LINEAR16 (0000,0001, (V) 0010,0011) 0.57 V 0.3 V to 14 V, 1.953 mV resolution 27h VOUT_TRANSITION_RATE R/W E002h LINEAR11 (1110,0000, (mV/μs) 0000,0010) 0.125 mV/μs 0.0625 mV/μs to2 mV/μs, 0.0625 mV/μs resolution 29h VOUT_SCALE_LOOP R/W E808h This command deviates from LINEAR11 (1110,1000, standard PMBus 1.3 specifications; (V/V) 0000,1000) 1 V/V 33h FREQUENCY_SWITCH R/W 0258h LINEAR11 (0000,0010, (kHz) 0101,1000) 600 kHz 300 kHz to 1500 kHz, 50 kHz resolution 35h VIN_ON R/W F814h LINEAR11 (1111,1000, (V) 0001,0100) 10 V 1 V to 80 V, 0.5 V resolution 36h VIN_OFF R/W 0100h LINEAR11 (0000,0001, (V) 0000,0000) 9V 1 V to 80 V, 0.5 V resolution 37h INTERLEAVE R/W 40h VOUT_OV_FAULT_LIMIT R/W Word [15 : 12] 0000: reserved [11 : 8] 0001: sets unit as 0100h (0000,0001, Master or Slave 0000,0000) [7 : 4] 0000: sets unit as master [3 : 0] 0000: not used 0161h LINEAR16 (0000,0001, (V) 0011,0011) Standalone, master, slave in phase, slave 180° out of phase 0.3 V to 14 V, 1.953 mV resolution The device’s output is disabled while the fault is present. Operation resumes and the output is enabled 00h, 16h, when the fault condition no longer 22h, exists. It attempts to restart F8h 36h, C0h, continuously, without limitation, until (1111,1000) D6h, it is commanded off (by the CONTROL pin or OPERATION E2h, F6h, F8h command or both), bias power is removed, or another fault condition causes the unit to shut down 41h VOUT_OV_FAULT_RESPONSE R/W 42h VOUT_OV_WARN_LIMIT R/W 0151h LINEAR16 (0000,0001, (V) 0101,0001) 0.66 V 0.3 V to 14 V, 1.953 mV resolution 43h VOUT_UV_WARN_LIMIT R/W 0114h LINEAR16 (0000,0001, (V) 0001,0100) 0.54 V 0 V to 14 V, 1.953 mV resolution S21-0213-Rev. B, 08-Mar-2021 Byte 0.69 V 0.125 V/V, 0.25 V/V, 0.5 V/V, 1 V/V Document Number: 77863 13 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PMBus COMMAND LIST ADDRESS 44h 45h 46h 47h PMBus COMMAND NAME TYPE VOUT_UV_FAULT_LIMIT R/W VOUT_UV_FAULT_RESPONSE IOUT_OC_FAULT_LIMIT IOUT_OC_FAULT_RESPONSE R/W R/W R/W DATA FORMAT (UNITS) DEFAULT VALUE IN NVM 00F5h LINEAR16 (0000,0000, (V) 1111,0101) Byte 4Ah IOUT_OC_WARN_LIMIT R/W 4Fh OT_FAULT_LIMIT R/W 007Dh LINEAR11 (0000,0000, (°) 0111,1101) OT_FAULT_RESPONSE R/W 51h OT_WARN_LIMIT R/W S21-0213-Rev. B, 08-Mar-2021 Byte 0.48 V 0 V to 14 V, 1.953 mV resolution SiC455: 56 A SiC456: 35 A SiC458: 21 A This command deviates from standard PMBus 1.3 specifications. The device continues operation for A1h 128 consecutive OC cycles and then (1010,0001) shut down. Waiting for 20 ms, it hiccups until the fault condition no longer exists SiC455: F868h (1111,1000, 0110,1000) SiC456: F841h LINEAR11 (A) (1111,1000, 0100,0010) SiC458: F827h (1111,1000, 0010,0111) 50h VALID RANGE The device shuts down (disables the output) and attempts to restart continuously, without limitation, until B9h it is commanded off (by the EN pin or (1011,1001) OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 20 ms delay SiC455:F87 0h (1111,1000, 0111,0000) SiC456: F846h LINEAR11 (A) (1111,1000, 0100,0110) SiC458: F82Ah (1111,1000, 0010,1010) Byte DEFAULT 0 A to 127 A, 0.5 A resolution 00h, 16h, 22h, 36h, A1h, C0h, D6h, E2h, F6h, F8h SiC455: 52 A SiC456: 32.5 A SiC458: 19.5 A 0 A to 127 A, 0.5 A resolution 125 °C 0 °C to 150 °C, 1 °C resolution The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. It attempts to restart F9h continuously, without limitation, until (1111,1001) it is commanded off (by the EN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down 0069h LINEAR11 (0000,0000, (°) 0110,1001) 00h, 16h, 22h, 36h, B9h, C0h, D6h, E2h, F6h 105 °C 00h, 16h, 22h, 36h, C0h, D6h, E2h, F6h, F9h 0 °C to 150 °C, 1 °C resolution Document Number: 77863 14 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PMBus COMMAND LIST ADDRESS 55h PMBus COMMAND NAME TYPE VIN_OV_FAULT_LIMIT R/W DATA FORMAT (UNITS) DEFAULT VALUE IN NVM F81Eh LINEAR11 (1111,1000, (V) 0001,1110) Byte DEFAULT VALID RANGE 15 V 1 V to 80 V, 0.5 V resolution This command deviates from standard PMBus 1.3 specifications.The device’s output is disabled while the fault is present. B8h Operation resumes and the output is (1011,1000) enabled when the fault condition no longer exists. It does not attempt to restart. The output remains disabled until the fault is cleared 00h, 16h, 22h, 36h, B8h, C0h, D6h, E2h, F6h 56h VIN_OV_FAULT_RESPONSE R/W 58h VIN_UV_WARN_LIMIT R/W F812h LINEAR11 (1111,1000, (V) 0001,0010) 9V 1 V to 80 V, 0.5 V resolution 5Dh IIN_OC_WARN_LIMIT R/W F80Ah LINEAR11 (1111,1000, (A) 0000,1010) 5A 0 A to 127 A, 0.5 A resolution 5Eh POWER_GOOD_ON R/W 0114h LINEAR16 (0000,0001, (V) 0001,0100) 0.54 V 0.24 V to 14 V, 1.953 mV resolution 5Fh POWER_GOOD_OFF R/W 0105h LINEAR16 (0000,0001, (V) 0000,0101) 0.51 V 0.24 V to 14 V, 1.953 mV resolution 60h TON_DELAY R/W 0000h LINEAR11 (0000,0000, (ms) 0000,0000) 0 ms 0 ms to 127 ms, 1 ms resolution 61h TON_RISE R/W 0005h LINEAR11 (0000,0000, (ms) 0000,0101) 5 ms 0 ms to 127 ms, 1 ms resolution 62h TON_MAX_FAULT_LIMIT R/W 0014h LINEAR11 (0000,0000, (mS) 0001,0100) 20 ms 0 ms to 127 ms, 1 ms resolution 80h, 83h, 86h, 88h, 89h, 8Ah, 8Bh, B9h 63h TON_MAX_FAULT_RESPONSE R/W 64h TOFF_DELAY R/W 0000h LINEAR11 (0000,0000, (ms) 0000,0000) 0 ms 0 ms to 127 ms, 1 ms resolution 65h TOFF_FALL R/W 0005h LINEAR11 (0000,0000, (ms) 0000,0101) 5 ms 0 ms to 127 ms, 1 ms resolution 66h TOFF_MAX_WARN_LIMIT R/W 003Ch LINEAR11 (0000,0000, (ms) 0011,1100) 60 ms 0 ms to 127 ms, 1 ms resolution 78h STATUS_BYTE Read Byte 00h (0000,0000) No faults - 79h STATUS_WORD Read Word 0000h (0000,0000, 0000,0000) No faults - 7Ah STATUS_VOUT Read Byte 00h (0000,0000) No faults - S21-0213-Rev. B, 08-Mar-2021 Byte The device shuts down (disables the output). It attempts to restart continuously, without limitation, until B9h it is commanded off (by the EN pin or (1011,1001) OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 20 ms delay Document Number: 77863 15 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PMBus COMMAND LIST PMBus COMMAND NAME TYPE DATA FORMAT (UNITS) DEFAULT VALUE IN NVM DEFAULT VALID RANGE 7Bh STATUS_IOUT Read Byte 00h (0000,0000) No faults - 7Ch STATUS_INPUT Read Byte 00h (0000,0000) No faults - 7Dh STATUS_TEMPERATURE Read Byte 00h (0000,0000) No faults - 7Eh STATUS_CML Read Byte 00h (0000,0000) No faults - 80h STATUS_MFR_SPECIFIC Read Byte 00h (0000,0000) No faults - 88h READ_VIN Read LINEAR11 (V) n/a n/a 0 V to 80 V 89h READ_IIN Read LINEAR11 (A) n/a n/a exp: (-4) to (-16) 8Bh READ_VOUT Read LINEAR16 (V) n/a n/a 0 V to 48 V 8Ch READ_IOUT Read LINEAR11 (A) n/a n/a exp: (-4 ) to (-10) 8Dh READ_TEMPERATURE Read LINEAR11 (°) n/a n/a (-50)° to 150° 94h READ_DUTY_CYCLE Read LINEAR11 (%) n/a n/a 0 % to 100 % 96h READ_POUT Read LINEAR11 (W) n/a n/a exp: (-4) to (-16) 97h READ_PIN Read LINEAR11 (W) n/a n/a exp: (-4) to (-16) 98h PMBUS_REVISION Read Byte 9Eh MFR_SERIAL R/W Block n/a ADDRESS 33h [7 :4] 0011: part I revision 1.3 (0011,0011) [3 : 0] 0011: part II revision 1.3 For user to store customized information ADh IC_DEVICE_ID R/W Block 0000h - D7h MFR_BASE_ADDRESS Pins program 7-bit 10h - E2h MFR_BASE_ADDRESS_2 Pins program 7-bit 50h - PMBus COMMAND DETAILS OPERATION (01 h) The OPERATION command sets the operational state of the regulator. It is used for the following functions: • Turn the regulator output on and off in conjunction with the input from EN signal • Set the output voltage with upper or lower margins • Select the fault handling behavior when fault is caused by margining state COMMAND Bit position Function Default (88 h) S21-0213-Rev. B, 08-Mar-2021 7 On/off 1 6 Off B 0 5 4 Margin 0 0 OPERATION 3 2 MRGNFLT 1 0 1 Nouse 0 0 RSV 0 Document Number: 77863 16 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Bit Description (default setting in bold) BITS SYMBOL 7 On/off 6 Off B 5:4 3:2 1 0 Margin VALUE 0b 1b 0b 1b Regulator turns off following the TOFF_DELAY and TOFF_FALL command 00b 01b 10b 11b 00b Output voltage is set by the PMBus VOUT_COMMAND data Output voltage is set by the PMBus VOUT_MARGIN_LOW data Output voltage is set by the PMBus VOUT_MARGIN_HIGH data Not supported Not supported 01b Faults caused by selecting VOUT_MARGIN_HIGH or VOUT_MARGIN_LOW as the nominal output voltage source are ignored 10b Faults caused by selecting VOUT_MARGIN_HIGH or VOUT_MARGIN_LOW as the nominal output voltage source are acted upon according to the settings of the VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE 11b x x Not supported Not used Reserved MRGNFLT Nouse RSV ACTION Output is disabled Output is enabled Output is turned off immediately and power off sequence commands ignored ON_OFF_CONFIGURATION (02 h) The ON_OFF_CONFIG command configures the combination of EN pin input and PMBus commands needed to turn the unit on and off. This includes how the unit responds when power is applied. COMMAND Bit position Function Default (1Fh) 7 0 6 RSV 0 5 0 ON/OFF_CONFIGURATION 4 3 2 PU CMD EN 1 1 1 1 ENPOL 1 0 Off B1 1 Bit Description (default setting in bold) BITS 7:5 SYMBOL RSV 4 PU 3 CMD 2 EN 1 ENPOL 0 OFFB1 VALUE 000b 0b 1b 0b 1b 0b 1b 0b 1b ACTION Reserved Regulator powers up any time power is present regardless of state of the EN signalpin Regulator does not power up until commanded by the CONTROLEN pin and OPERATION command Regulator ignores the “on” bit in the OPERATION command Regulator responds the “on” bit in the OPERATION command Regulator ignores the EN pin. Power conversion is controlled only by the OPERATION command Regulator requires the EN pin to be asserted to start the unit EN signal is active low EN signal is active high 0b Regulator turns off following the tOFF_DELAY and tOFF_FALL command when EN signal is used to turn off 1b Regulator turns off immediately CLEAR_FAULTS (03 h) The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status registers simultaneously. At the same time, the device negates (clears, releases) its SALRT ALERT# signal output if the device is asserting the SALRT ALERT# signal. WRITE_PROTECT (10 h) The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command is not intended to provide protection against deliberate or malicious changes to a device’s configuration or operation. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 17 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix COMMAND WRITE_PROTECT Bit position 7 6 Function 5 4 3 2 WTPRT Default (00h) 0 1 0 0 0 Nouse 0 0 0 0 0 Bit Description (default setting in bold) BITS SYMBOL 7:5 VALUE WTPRT 4:0 Nouse ACTION 000b Enable writes to all commands 100b Disable all writes except to the WRITE_PROTECT command 010b Disable all writes except to the WRITE_PROTECT and OPERATION commands 001b Disable all writes except to the WRITE_PROTECT, OPERATION, ON_OFF_CONFIG and VOUT_COMMAND commands 00000b Not used STORE_USER_ALL (15 h) The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the operating memory to the matching locations in the non-volatile User Store memory. Any items in operating memory that do not have matching locations in the User Store are ignored. RESTORE_USER_ALL (16 h) The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the nonvolatile user store memory (NVM) to the matching locations in the operating memory. The values in the operating memory are overwritten by the value retrieved from the user store. This feature is protected by the EEPROM_PASSWORD (DBh) command, see the section below for more information. Any items in user store that do not have matching locations in the operating memory are ignored, see the summary table for details. CAPABILITY (19 h) The CAPABILITY command provides a way for a host system to determine some key capabilities of the PMBus device. This is a read only register. COMMAND WRITE_PROTECT Bit position 7 Function 6 PEC Default (D0h) 5 SPD 1 1 0 4 3 2 ALRT NFMT AVS 1 1 0 0 0 RSV 0 0 Bit Description BITS 7 6:5 4 3 2 1:0 SYMBOL PEC SPD ALRT NFMT AVS RSV VALUE 1b 10b 1b 0b 0b 00b ACTION Packet error checking is supported Maximum supported bus speed is 1 MHz The unit has ALERT# pin and supports PMBus alert response protocol Numeric data is in LINEAR11, LINEAR16, or DIRECT format AVSBUS not supported Reserved SMBALERT_MASK (1Bh) The SMBALERT_MASK command may be used to prevent a warning or fault condition from asserting the SMBALERT# signal. The command format used to block a status bit or bits from causing the SMBALERT# signal to be asserted is shown in Fig. 9. The bits in the mask byte align with the bits in the corresponding status register. For example, if the STATUS_TEMPERATURE command code were sent with the mask byte 01000000b, then an over temperature warning OT_WARNING (overtemperature warning) condition would be blocked from asserting SMBALERT#. 7 S Slave Address 1 W 1 A 8 SMBalert_mask Command_code 1 A 8 Status_x Command code 1 A 8 Mask BYTE 1 A P Fig. 9 - SMBALSER_MASK Command Packet Format S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 18 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix The command format used by the host to determine the SMALER_MASK setting for a given status register is shown in Fig. 10. 7 1 Slave S 1 W address 8 1 SMBalert_Mask A A Command_code 7 S Slave r address 8 1 1 R A 1 Block count A (=1) 8 8 A (=1) A Command code 1 Block count 1 Status_x 8 1 N Mask byte P A Fig. 10 - Retrieving the SMBALSER_MASK Setting for a Given Status Register VOUT_MODE (20 h) The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the linear or direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the values. This is a read only register COMMAND WRITE_PROTECT Bit position 7 6 Function 5 4 3 2 Mode Default (D0h) 0 1 0 1 1 EXP 0 0 1 0 1 Bit Description BITS SYMBOL VALUE 7:5 Mode 000b 4:0 EXP 10111b ACTION The unit uses ULINEAR16 format for VOUT related commands 5-bit two’s complement binary integer equals -9 for VOUT related commands VOUT_COMMAND (21 h) The VOUT_COMMAND is used to directly set the output voltage using the ULINEAR16 format, which is a 16- bit unsigned integer. This is a read and write register. The output voltage, in volts, is calculated from the equation: VOUT_SET = VOUT_COMMAND x 2N Where: VOUT_SET is the set output voltage in volt VOUT_COMMAND is the 16- bit unsigned binary integer specified in the command N is a 5- bit two’s complement binary integer specified in VOUT mode [4 : 0] VOUT COMMAND COMMAND Bit position 7 6 5 Function 4 3 2 1 0 7 6 5 Data byte high Default (133h) 0 0 0 0 0 4 3 2 1 0 0 1 1 Data byte low 0 0 1 0 0 1 1 0 Bit Description BITS FORMAT VALUE 15 : 0 Unlinear 16 0133h ACTION VOUT_COMMAND is specified as 307 x 2-9 = 0.6 V The output voltage’s range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0133h equivalent to 0.6 V. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 19 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix VOUT_TRIM (22 h) The VOUT_TRIM command is used to apply a fixed offset voltage to the output voltage command value. This is a read and write register. The VOUT_TRIM has two data bytes formatted as a two’s complement binary integer (SLINEAR16 format). It is most typically used by the end user to trim the output voltage at the time the PMBus device is assembled into the end user’s system. The VOUT_TRIM command deviates from standard PMBus 1.3 specifications, at which it requires adding an integer calculating from the expected offset voltage and the VOUT_SCALE_LOOP to VOUT_TRIM’s NVM register default store value varying by devices. The effect of this command on the output voltage, in volts, is calculated from the equation: N ΔV × 2 ΔVoltage = --------------------------------------------------------VOUT_SCALE_LOOP Where: Δvoltage is the fixed offset voltage to the output voltage in volt ΔV is the 16-bit two’s complement integer specified in VOUT_TRIM VOUT_SCALE_LOOP is the dimensionless scale factor specified in VOUT_SCALE_LOOP command N is a 5-bit two’s complement binary integer specified in VOUT_MODE [4:0]. COMMAND VOUT TRIM Bit position 15 Function 14 13 12 11 10 9 8 sign Default (0000h) 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 data 0 0 0 0 0 0 0 0 Bit Description BITS FORMAT VALUE 15 : 0 Unlinear 16 0000h ACTION ΔV is 0 V The offset voltage’s range is -2 V to 2 V, resolution is 1.953 mV, and its NVM register default store value is a factory trim value varying by devices. The users need to calculate a 16-bit two’s complement integer number following the above equation and add the number to the factory trim value, so as to achieve the expected offset voltage to the output voltage. VOUT_MAX (24 h) The VOUT_MAX command sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary output overvoltage protection. This is a read and write register. The VOUT_MAX uses ULINEAR16 format, which is a 16- bit unsigned integer according to the setting of the VOUT_MAX command. Bit Description BITS FORMAT VALUE 15 : 0 Unlinear 16 1C00h ACTION The VOUT_MAX is specified as 14 V The VOUT_MAX range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 1C00h equivalent to 14 V. VOUT_MARGIN_HIGH (25 h) The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to “margin high”. This is a read and write register. The VOUT_MARGIN_HIGH uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS FORMAT VALUE ACTION 15 : 0 Unlinear 16 0142h The VOUT_MARGIN_HIGH is specified as 0.63 V The VOUT_MARGIN_HIGH range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0142h equivalent to 0.63 V. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 20 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix VOUT_MARGIN_LOW (26 h) The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to margin low. This is a read and write register. The VOUT_MARGIN_LOW uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS FORMAT VALUE ACTION 15 : 0 Unlinear 16 0123h The VOUT_MARGIN_LOW is specified as 0.57 V The VOUT_MARGIN_LOW range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0123h equivalent to 0.57 V. VOUT_TRANSITION_RATE (27 h) The VOUT_TRANSITION_RATE command sets the rate in mV/μs at which the output voltage should change voltage when a PMBus device receives either a VOUT_COMMAND or OPERATION (margin high, margin low) that causes the output voltage to change. This commanded rate of change does not apply when the unit is commanded to turn on or to turn off. This is a read and write register. The VOUT_TRANSITION_RATE uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VOUT_TRANSITION_RATE command is constant as 5’b11100, that is, -4 in decimal. The LINEAR11 format of the two data bytes is illustrated in table below. Table - LINEAR11 Numeric Format Data Bytes COMMAND VOUT_TRANSITION_RATE Bit position 15 14 Function 13 12 11 10 9 8 7 6 EXP Default (E002h) 1 1 1 5 4 3 2 1 0 0 0 0 1 0 MAN 0 0 0 0 0 0 0 0 Bit Description BITS SYMBOL VALUE 15 EXP SGN 1b 14 : 11 EXP 1100b 10 MAN SGN 0b 19 : 0 MAN DATA 00, 0000, 0010b ACTION Exponent value with negative sign Five 5-bit two’s complement exponent equals -4 for VOUT_TRANSITION_RATE command Mantissa value with positive sign Eleven 11-bit two’s complement mantissa equals 2 for VOUT_TRANSITION_RATE command The VOUT_TRANSITION_RATE range is 0.0625 - 2 mV/μs, resolution is 0.0625 mV/μs, and its NVM register default store value is E002h equivalent to 0.125 mV/μs. Any commands out of the valid range or with incorrect resolution will be ignored and reported. VOUT_SCALE_LOOP (29 h) The VOUT_SCALE_LOOP command deviates from standard PMBus 1.3 specifications. The VOUT_SCALE_LOOP command is used to scale down both the VOUT_COMMAND and the sense differential output voltage at the unit input, so as to extend operational range of the PMBus unit to reach the maximum output voltage 12 V without the requirement of external resistor divider on board. This is a read and write register. The VOUT_SCALE_LOOP uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VOUT_SCALE_LOOP command is constant as 5’b11101, that is, -3 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table “LINEAR11 Numeric Format Data Bytes”. Table - VOUT_SCALE_LOOP Look Up SET OUTPUT VOLTAGE (V) 0.3 V < VOUT < 1.8 V SCALE DOWN FACTOR (V/V) VOUT_SCALE_LOOP BITS [15 : 0] 1.0 E808h E804h 1.8 V ≤ VOUT < 3.3 V 0.5 3.3 V ≤ VOUT ≤ 5.0 V 0.25 E802h 5.0 V < VOUT ≤ 12.0 V 0.125 E801h S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 21 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Bit Description BITS SYMBOL VALUE 15 to 0 Linear 11 E808h ACTION The VOUT_SCALE_LOOP is specified as 1 V/V The VOUT_SCALE_LOOP offers four options of scale down factor: 1.0 V/V, 0.5 V/V, 0.25 V/V, and 0.125 V/V. When VOUT is set by a resistor between VSET pin and ground, the value of VOUT_SCALE_LOOP is automatically chosen according to the “VOUT_SCALE_LOOP look up” table. When VOUT is set by PMBus VOUT_COMMAND, the value of the VOUT_SCALE_LOOP shall be updated according to the “VOUT_SCALE_LOOP look up” table. The VOUT_SCALE_LOOP NVM register default store value is E808h equivalent to 1.0 V/V. Any commands out of the valid options will be ignored and reported. FREQUENCY_SWITCH (33 h) The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the PMBus unit. This is a read and write register. The FREQUENCY_SWITCH uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the FREQUENCY_SWITCH command is constant as 5’b00000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0258h ACTION FREQUENCY_SWITCH is specified 600 kHz. The FREQUENCY_SWITCH range is 300 kHz to 1500 kHz, resolution is 50 kHz, and its NVM register default store value is 0258h equivalent to 600 kHz. Any commands out of the valid range or with incorrect resolution will be ignored and reported. VIN_ON (35 h) The VIN_ON command sets the value of the input voltage, in volt, at which the PMBus unit should start power conversion. This is a read and write register. The VIN_ON uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_ON command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 F814h ACTION The VIN_ON is specified as 10 V The VIN_ON range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F814h equivalent to 10 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. VIN_OFF (36 h) The VIN_OFF command sets the value of the input voltage, in volt, at which the PMBus unit, once operation has started, should stop power conversion. This is a read and write register. The VIN_OFF uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_OFF command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 F812h ACTION The VIN_OFF is specified as 9 V The VIN_OFF range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F812h equivalent to 9 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. INTERLEAVE (37 h) The INTERLEAVE command deviates from standard PMBus 1.3 specifications. The INTERLEAVE command is used to sets the mode of switching frequency and phase, at which the PMBus unit, once operation has started, should use to generate switching frequency and phase angle. This is a read and write register. The INTERLEAVE commands offer four modes of switching configuration: STANDALONE, MASTER, SLAVE in phase, and SALVE 180° out of phase. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 22 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix The description of all four modes and the corresponding INTERLEAVE command is listed in the table below. INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION DESCRIPTION INTERLEAVE BITS [15 : 0] STANDALONE The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC unit designated pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving the PMBus command FREQUENCY_SWITCH command. The RT/SYNC pin shall not be used for other purposes 0000h MASTER The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving the PMBus command FREQUENCY_SWITCH command. After inside power VDD of the unit is above its under voltage level, the RT/SYNC pin will output a 50% duty cycle pulse signal in phase with the switching frequency, which may be used to drive other units set as the SLAVE mode by INTERLEAVE command. The RT/SYNC pin shall not be used for other purposes 0100h SLAVE in phase The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving the PMBus command FREQUENCY_SWITCH command. When an external pulse switching signal is connected to the /SYNC pin, the unit will synchronize its switching frequency to the external pulse switching signal with 0º phase difference. The RT/SYNC pin shall not be used for other purpose 0120h SLAVE 180º out of phase The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving the PMBus command FREQUENCY_SWITCH command. When an external pulse switching signal is connected to the /SYNC pin, the unit will synchronize its switching frequency to the external pulse switching signal with 180º phase difference. The RT/SYNC pin shall not be used for other purposes 0121h Bit Description BITS SYMBOL VALUE ACTION 15:0 Linear 11 0100h The INTERLEAVE is specified as MASTER mode The INTERLEAVE NVM register default store value is 0100h equivalent to MASTER mode. Any commands out of the options will be ignored and reported. VOUT_OV_FAULT_LIMIT (40 h) The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output overvoltage fault. This is a read and write register. The VOUT_OV_FAULT_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS SYMBOL VALUE 15:0 Ulinear 16 0161h ACTION The VOUT_OV_FAULT_LIMIT is specified as 0.69 V The VOUT_OV_FAULT_LIMIT range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0161h equivalent to 0.69 V. VOUT_OV_FAULT_RESPONSE (41h) The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. This is a read and write register and the NVM register default store value is F8h. COMMAND Bit position VOUT_OV_FAULT_RESPONSE 7 Function Default (F8h) S21-0213-Rev. B, 08-Mar-2021 6 5 OVRSP 1 4 3 2 OVRTY 1 1 1 1 0 OVDLY 1 0 0 0 Document Number: 77863 23 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Supported Commands OVRSP OVRTY OVDLY DESCRIPTIONS 1 1 1 1 1 0 0 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. It attempts to restart continuously, without limitation, until it is commanded off (by the CONTROL pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down 0 0 0 0 0 0 0 0 The device continues operation 0 0 0 1 0 1 1 0 The device continues operation 0 0 1 0 0 0 1 0 The device continues operation 0 0 1 1 0 1 1 0 The device continues operation 1 1 0 0 0 0 0 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists 1 1 0 1 0 1 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists 1 1 1 0 0 0 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists 1 1 1 1 0 1 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists VOUT_OV_WARN_LIMIT (42h) The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output voltage high warning. This is a read and write register. The VOUT_OV_WARN_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS SYMBOL VALUE 15:0 Ulinear 16 0151h ACTION The VOUT_OV_WARN_LIMIT is specified as 0.66 V The VOUT_OV_WARN_LIMIT range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0151h equivalent to 0.66 V. VOUT_UV_WARN_LIMIT (43h) The VOUT_UV_WARN_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output voltage low warning. This is a read and write register. The VOUT_UV_WARN_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS SYMBOL VALUE 15:0 Ulinear 16 0114h ACTION The VOUT_UV_WARN_LIMIT is specified as 0.54 V The VOUT_UV_WARN_LIMIT range is 0 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0114h equivalent to 0.54 V. VOUT_UV_FAULT_LIMIT (44h) The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output undervoltage fault. This is a read and write register. The VOUT_UV_FAULT_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS SYMBOL VALUE 15:0 Ulinear 16 00F5h ACTION The VOUT_UV_FAULT_LIMIT is specified as 0.48 V The VOUT_UV_FAULT_LIMIT range is 0 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 00F5h equivalent to 0.48 V. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 24 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix VOUT_UV_FAULT_RESPONSE (45h) The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. This is a read and write register and the NVM register default store value is B9h. COMMAND VOUT_UV_FAULT_RESPONSE Bit position 7 Function 6 5 4 UVRSP Default (B9h) 1 3 2 UVRTY 0 1 1 1 0 UVDLY 1 0 0 1 Supported Commands UVRSP UVRTY UVDLY DESCRIPTIONS 1 0 1 1 1 0 0 1 The device shuts down (disables the output) and attempts to restart continuously, without limitation, until it is commanded off (by the EN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 20 ms delay 0 0 0 0 0 0 0 0 The device continues operation 0 0 0 1 0 1 1 0 The device continues operation 0 0 1 0 0 0 1 0 The device continues operation 0 0 1 1 0 1 1 0 The device continues operation 1 1 0 0 0 0 0 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. The device does not attempt to restart. The output remains disabled until the fault is cleared 1 1 0 1 0 1 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. The device does not attempt to restart. The output remains disabled until the fault is cleared 1 1 1 0 0 0 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. The device does not attempt to restart. The output remains disabled until the fault is cleared 1 1 1 1 0 1 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. The device does not attempt to restart. The output remains disabled until the fault is cleared IOUT_OC_FAULT_LIMIT (46h) The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in Amperes, that causes the overcurrent detector to indicate an overcurrent fault condition. This is a read and write register. The IOUT_OC_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the IOUT_OC_FAULT_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS 15:0 SYMBOL Linear 11 VALUE ACTION F870h The IOUT_OC_FAULT_LIMIT is 56 A for SiC450 F846h The IOUT_OC_FAULT_LIMIT is 35 A for SiC451 F82Ah The IOUT_OC_FAULT_LIMIT is 21 A for SiC453 The IOUT_OC_FAULT_LIMIT range is 0 A to 127 A, resolution is 0.5 A, and its NVM register default store value is F846h for SiC451 equivalent to 35 A. Any commands out of the valid range or with incorrect resolution will be ignored and reported. IOUT_OC_FAULT_RESPONSE (47h) The IOUT_OC_FAULT_RESPONSE is used to set device over current protection response (OCP) when valley inductor current is higher than IOUT_OC_FAULT_LIMIT. This is a read and write register and the NVM register default store value is A1h. COMMAND Bit position Function Default (0xA1h) IOUT_OC_FAULT_RESPONSE 7 6 5 0 1 OCRSP 1 4 OCCYCL 0 3 2 0 0 1 OCDLY 0 0 1 This command deviates from standard PMBus 1.3 specifications. It provides users 3-bit [5 : 3] setting to generate OC fault based on total number of consecutive pulse-by-pulse OC counts. It also provides users 3-bit [2 : 0] delay time option between shutdown and next restart attempt. In case of bits [5 : 3] = 111b, the device does not report OC fault and continues to operate indefinitely while maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 25 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Supported Commands OCRSP OCRTY OCDLY 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 0 DESCRIPTIONS The device continues operation for 128 consecutive OC cycles and then shut down. Waiting for 20 ms, it hiccups until the fault condition no longer exists The device continues operation The device continues operation The device continues operation The device continues operation The device continues operation for 8 consecutive OC cycles and then shut down without delay The device continues operation for 32 consecutive OC cycles and then shut down without delay The device continues operation for 128 consecutive OC cycles and then shut down without delay. The device continues operation for 512 consecutive OC cycles and then shut down without delay The device continues operation and never shut down when OCP happens IOUT_OC_WARN_LIMIT (4Ah) The IOUT_OC_WARN_LIMIT command sets the value of the output current, in ampere, that causes an output overcurrent warning. This is a read and write register. The IOUT_OC_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the IOUT_OC_WARN_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS 1 5: 0 SYMBOL Linear 11 VALUE ACTION F868h The IOUT_OC_WARN_LIMIT is 52 A SiC450 F841h The IOUT_OC_WARN_LIMIT is 32.5 A for SiC451 F827h The IOUT_OC_WARN_LIMIT is 19.5 A for SiC453 The IOUT_OC_WARN_LIMIT range is 0 A to 127 A, resolution is 0.5 A, and its NVM register default store value is F841h for SiC451 equivalent to 32.5 A. Any commands out of the valid range or with incorrect resolution will be ignored and reported. OT_FAULT_LIMIT (4Fh) The OT FAULT LIMIT command sets the temperature of the unit, in degree celsius, at which it should indicate an overtemperature fault. This is a read and write register. The OT_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5- bit two’s complement exponent (scaling factor). The 5- bit two’s complement exponent of the OT_FAULT_LIMIT command is constant as 5’b00000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15:0 Linear 11 007Dh ACTION The OT_FAULT_LIMIT is specified as 125 °C The OT_FAULT_LIMIT range is 0 °C to 150 °C, resolution is 1 °C, and its NVM register default store value is 007Dh equivalent to 125 °C. Any commands out of the valid range or with incorrect resolution will be ignored and reported. OT_FAULT_RESPONSE (50h) The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an overtemperature fault. This is a read and write register and the NVM register default store value is F9h. COMMAND Bit position OT FAULT RESPONSE 7 Function Default (F9h) S21-0213-Rev. B, 08-Mar-2021 6 5 1 1 OTRSP 1 4 3 2 1 0 OTRTY 1 1 0 OTDLY 0 1 Document Number: 77863 26 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Supported Commands OTRSP OTRTY OTDLY DESCRIPTIONS 1 1 1 1 1 0 0 1 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. It attempts to restart continuously, without limitation, until it is commanded off (by the EN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down 0 0 0 0 0 0 0 0 The device continues operation 0 0 0 1 0 1 1 0 The device continues operation 0 0 1 0 0 0 1 0 The device continues operation 0 0 1 1 0 1 1 0 The device continues operation 1 1 0 0 0 0 0 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. It does not attempt to restart. The output remains disabled until the fault is cleared 1 1 0 1 0 1 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists 1 1 1 0 0 0 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists 1 1 1 1 0 1 1 0 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists OT_WARN_LIMIT (51h) The OT_WARN_LIMIT command sets the temperature of the unit, in degree celsius, at which it should indicate an overtemperature warning alarm. This is a read and write register. The OT_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the OT WARN LIMIT command is constant as 5’b00000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0069h ACTION The OT_WARN_LIMIT is specified as 105 °C The OT_WARN_LIMIT range is 0 °C to 150 °C, resolution is 1 °C, and its NVM register default store value is 0069h equivalent to 105 °C. Any commands out of the valid range or with incorrect resolution will be ignored and reported. VIN_OV_FAULT_LIMIT (55h) The VIN_OV_FAULT_LIMIT command sets the value of the input voltage, in volt, that causes an input overvoltage fault. This is a read and write register. The VIN_OV_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5 bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_OV_FAULT_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 F81Eh ACTION The VIN_OV_FAULT_LIMIT is specified as 15 V The VIN_OV_FAULT_LIMIT range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F81Eh equivalent to 15 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. VIN_OV_FAULT_RESPONSE (56h) The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. This is a read and write register and the NVM register default store value is B8h. COMMAND Bit position VIN_OV_FAULT_RESPONSE 7 Function Default (B8h) S21-0213-Rev. B, 08-Mar-2021 6 5 VIOVRSP 1 4 3 2 VIOVRTY 0 1 1 1 0 VIOVDLY 1 0 0 0 Document Number: 77863 27 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Supported Commands OTRSP OTRTY OTDLY 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 DESCRIPTIONS This command deviates from standard PMBus 1.3 specifications. The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. It does not attempt to restart. The output remains disabled until the fault is cleared The device continues operation The device continues operation The device continues operation The device continues operation The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. It does not attempt to restart. The output remains disabled until the fault is cleared The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists VIN_UV_WARN_LIMIT (58h) The VIN_UV_WARN_LIMIT command sets the value of the input voltage, in volt, that causes an input voltage low warning. This is a read and write register. The VIN_UV_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_UV_WARN_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 F812h ACTION The VIN_UV_WARN_LIMIT is specified as 9 V The VIN_UV_WARN_LIMIT range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F812h equivalent to 9 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. IIN_OC_WARN_LIMIT (5Dh) The IIN_OC_WARN_LIMIT command sets the value of the input current, in ampere, that causes an input current overcurrent Warning. This is a read and write register. The IIN_OC_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the IIN_OC_WARN_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 F80Ah ACTION The IIN_OC_WARN_LIMIT is specified as 5 A The IIN_OC_WARN_LIMIT range is 0 A to 127 A, resolution is 0.5 A, and its NVM register default store value is F80Ah equivalent to 5 A. Any commands out of the valid range or with incorrect resolution will be ignored and reported. POWER_GOOD_ON (5Eh) The POWER_GOOD_ON command sets the value of the output voltage at which an optional power good signal should be asserted, indicating that the output voltage is valid. This is a read and write register. The POWER_GOOD_ON uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. Bit Description BITS SYMBOL VALUE 15 : 0 Ulinear 16 0114h ACTION The POWER_GOOD_ON is specified as 0.54 V The POWER_GOOD_ON range is 0.24 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0114h equivalent to 0.54 V. POWER_GOOD_OFF (5Fh) The POWER_GOOD_OFF command sets the value of the output voltage at which an optional power good signal should be negated, indicating that the output voltage is not valid. This is a read and write register. The POWER_GOOD_OFF uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 28 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Bit Description BITS SYMBOL VALUE 15 : 0 Ulinear 16 0105h ACTION The POWER_GOOD_OFF is specified as 0.51 V The POWER_GOOD_OFF range is 0.24 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0105h equivalent to 0.51 V. TON_DELAY(60h) The TON_DELAY command sets the time, in millisecond, from which a start condition is received (as programmed by the ON_OFF_CONFIG command) until the output voltage starts to rise. This is a read and write register. The TON_DELAY uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5 bit two’s complement exponent of the TON_DELAY command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0000h ACTION The TON_DELAY is specified as 0 ms The TON_DELAY range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0000h equivalent to 0 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. TON_RISE (61h) The TON_RISE command sets the time, in millisecond, from when the output starts to rise until the voltage has entered the regulation band. This is a read and write register. The TON_RISE uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TON_RISE command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0005h ACTION The TON_RISE is specified as 5 ms The TON_RISE range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0005h equivalent to 5 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. TON_MAX_FAULT_LIMIT (62h) The TON_MAX_FAULT_LIMIT command sets an upper limit, in millisecond, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. This is a read and write register. The TON_MAX_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TON_MAX_FAULT_LIMIT command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0014h ACTION The TON_MAX_FAULT_LIMIT is specified as 20 ms The TON_MAX_FAULT_LIMIT range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0014h equivalent to 20 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. TON_MAX_FAULT_RESPONSE (63h) The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to an input overcurrent fault. This is a read and write register and the NVM register default store value is B9h. COMMAND Bit position Function Default (0xB9h) S21-0213-Rev. B, 08-Mar-2021 TON_MAX_FAULT_RESPONSE 7 6 5 ONMXRSP 1 0 4 3 2 ONMXRTY 1 1 1 0 ONMXDLY 1 0 0 1 Document Number: 77863 29 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Supported Commands ONMXRSP ONMXRTY ONMXDLY DESCRIPTIONS 1 0 1 1 1 0 0 1 The device shuts down (disables the output). It attempts to restart continuously, without limitation, until it is commanded off (by the EN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 20 ms delay 1 0 0 0 0 0 0 0 The device shuts down (disables the output). It does not attempt to restart. The output remains disabled until the fault is cleared 1 0 0 0 0 0 1 1 The device shuts down (disables the output). It does not attempt to restart. The output remains disabled until the fault is cleared 1 0 0 0 0 1 1 0 The device shuts down (disables the output). It does not attempt to restart. The output remains disabled until the fault is cleared 1 0 0 0 1 0 0 0 The device shuts down (disables the output). It attempts to restart 1 time. No delay 1 0 0 0 1 0 0 1 The device shuts down (disables the output). It attempts to restart 1 time. 20 ms delay 1 0 0 0 1 0 1 0 The device shuts down (disables the output). It attempts to restart 1 time. 30 ms delay 1 0 0 0 1 0 1 1 The device shuts down (disables the output). It attempts to restart 1 time. 40 ms delay TOFF_DELAY (64h) The TOFF_DELAY command sets the time, in millisecond, from when a stop condition is received until the unit stops transferring energy to the output. This is a read and write register. The TOFF_DELAY uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TOFF_DELAY command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0000h ACTION The TOFF_DELAY is specified as 0 ms The TOFF_DELAY range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0000h equivalent to 0 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. TOFF_FALL (65h) The TOFF_FALL command sets the time, in millisecond, from the end of the turn-off delay time until the voltage is commanded to zero. Note that this command can only be used with a device whose output can sink enough current to cause the output voltage to decrease at a controlled rate. This is a read and write register. The TOFF_FALL uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TOFF_FALL command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 0005h ACTION The TOFF_FALL is specified as 5 ms The TOFF_FALL range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0005h equivalent to 5 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. TOFF_MAX_WARN_LIMIT (66h) The TOFF_MAX_WARN_LIMIT command sets an upper limit, in millisecond, on how long the unit can attempt to power down the output without reaching 12.5 % of the output voltage programmed at the time the unit is turned off. This is a read and write register. The TOFF_MAX_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5- bit two’s complement exponent of the TOFF_MAX_WARN_LIMIT command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. Bit Description BITS SYMBOL VALUE 15 : 0 Linear 11 003Ch ACTION The TOFF_MAX_WARN_LIMIT is specified as 60 ms The TOFF_MAX_WARN_LIMIT range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 003Ch equivalent to 60 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 30 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix STATUS_BYTE (78h) The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. The STATUS_BYTE message content is described in the table below. This is a read register. Table - STATUS_BYTE Message Contents BIT STATUS BIT NAME MEANING 7 BUSY A fault was declared because the device was busy and unable to respond 6 OFF This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled 5 VOUT_OV_FAULT An output overvoltage fault has occurred 4 IOUT_OC_FAULT An output overcurrent fault has occurred 3 VIN_UV_FAULT An input undervoltage fault has occurred 2 Temperature A temperature fault or warning has occurred 1 CML A communications, memory or logic fault has occurred 0 None of the above A fault or warning not listed in bits (7 to 1) has occurred STATUS_WORD (79h) The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the status word is the same register as the STATUS_BYTE command. The STATUS_WORD message content is described in the following table. This is a read register. BYTE Low High BIT STATUS BIT NAME MEANING 7 Busy A fault was declared because the device was busy and unable to respond 6 OFF This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled An output overvoltage fault has occurred 5 VOUT_OV_FAULT 4 IOUT_OC_FAULT An output overcurrent fault has occurred 3 VIN_UV_FAULT An input undervoltage fault has occurred 2 Temperature A temperature fault or warning has occurred 1 CML A communications, memory or logic fault has occurred 0 None of the above A fault or warning not listed in bits [7 : 1] has occurred 7 VOUT An output voltage fault or warning has occurred 6 IOUT / POUT An output current or output power fault or warning has occurred 5 Input An input voltage, input current, or input power fault or warning has occurred 4 MFR specific A manufacturer specific fault or warning has occurred 3 PG status # The power good signal, if present, is negated 2 Fans Not available 1 Other Not available 0 Unknown Not available STATUS_VOUT (7Ah) The STATUS_VOUT command returns one byte with contents described in the following table. This is a read register. BIT MEANING 7 VOUT OV fault (output overvoltage fault) 6 VOUT OV warning (output overvoltage warning) 5 VOUT UV warning (output undervoltage warning) 4 VOUT OV fault (output undervoltage fault) 3 VOUT max. min. (an attempt has been made to set the output voltage toa value higher than allowed by the VOUT max. or lower than the limited allowed by the VOUT min.) 2 tON max. fault (output overvoltage fault) 1 tOFF max. warning (output overvoltage fault) 0 Not available S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 31 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix STATUS_IOUT (7Bh) The STATUS_IOUT command returns one byte with contents described in the following table. This is a read register. BIT MEANING 7 IOUT OC fault (output overcurrent fault) 6 Not available 5 IOUT OC warning (output overcurrent warning) 4 Not available 3 Not available 2 Not available 1 Not available 0 Not available STATUS_INPUT (7Ch) The STATUS_INPUT command returns one byte with contents described in the following table. This is a read register. BIT MEANING 7 VIN OV fault (input overvoltage fault) 6 Not available 5 VIN UV warning (input undervoltage warning) 4 Not available 3 Unit off for insufficient input voltage 2 Not available 1 IIN OC warning (input overcurrent warning) 0 Not available STATUS_TEMPERATURE (7Dh) The STATUS_TEMPERATURE command returns one byte with contents described in the following table. This is a read register. BIT MEANING 7 OT fault (overtemperature fault) 6 OT warning (overtemperature warning) 5 to 0 Not available STATUS_CML (7Eh) The STATUS_CML command returns one byte with contents described in the following table. This is a read register. BIT MEANING 7 Invalid or unsupported command received 6 Invalid or unsupported data received 5 Packet error check failed 4 Memory fault detected 3 Not available 2 Reserved 1 A communication fault other than the ones listed in this table has occurred 0 Not available STATUS_MFR Specific (80h) The STATUS_MFR specific command returns one byte with contents described in the following table. This is a read register. BIT MEANING 7 to 4 Not available 3 IL master fault 2 YF verify fault 1 YF erase fault 0 YF PGM fault S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 32 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix READ_VIN (88h) The READ_VIN command returns the input voltage in volt. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. READ_IIN (89h) The READ_IIN command returns the input current in ampere. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. READ_VOUT (8Bh) The read VOUT command returns the actual, measured output voltage in volt. The two data bytes are encoded in ULINEAR16 format, which is a 16 bit unsigned integer according to the setting of the VOUT_MODE command. This is a read register. READ_IOUT (8Ch) The READ_IOUT command returns the measured output current in ampere. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. READ_TEMPERATURE (8Dh) The READ_TEMPERATURE command returns the measured temperature of the PMBus unit in degree celsius. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. READ_DUTY_CYCLE (94h) The READ_DUTY_CYCLE command returns the duty of the PMBus unit’s power conversion in percent. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. READ_POUT (96h) The READ_POUT command returns the output power, in watt, of the PMBus unit. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. READ_PIN (97h) The READ_PIN command returns the input power, in watt, of the PMBus unit. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. PMBus_REVISION (98h) The PMBUS_REVISION command stores or reads the revision of the PMBus to which the device is compliant. The command has one data byte. Bits (7 to 4) indicate the revision of PMBus specification Part I to which the device is compliant. Bits (3 to 0) indicate the revision of PMBus specification part II to which the device is compliant. The permissible values are shown in the table below. This is a read register. Table - PMBUS_REVISION DATA Byte Contents BITS (7 TO 4) PART I REVISION BIT (3 TO 0) PART II REVISION 0000b 1.0 0000b 1.0 0001b 1.1 0001b 1.1 0010b 1.2 0010b 1.2 0011b 1.3 0011b 1.3 MFR_SERIAL (9Eh) The MFR_SERIAL command is used to store user’s customized information. This is a read and write 16-bit block register. Bit Description BITS 15 to 0 SYMBOL VALUE Block 0000h S21-0213-Rev. B, 08-Mar-2021 ACTION A block register to store user’s customized information Document Number: 77863 33 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix IC_DEVICE_ID (ADh) The IC_DEVICE_ID command is used to either set or read the type or part number of an IC embedded within a PMBus that is used for the PMBus interface. Each manufacturer uses the format of their choice for the IC device identification. IC_DEVICE_ID is typically only set once, at the time of manufacture. Bit Description BITS 15 to 0 SYMBOL VALUE Block 0000h ACTION The part number of the unit MFR_BASE_ADDRESS (D7h) The MFR_BASE_ADDRESS command is used to read or set the unit’s PMBus address when a designated voltage setting resistor is assembled between VSET pin of the PMBus unit and ground. The four least significant bits (LSB) [3 : 0] of the MFR_BASE_ADDRESS are set by resistance of the resistor assembled between ADDR pin and ground. The three most significant bits (MSB) [6 : 4] of the MFR_BASE_ADDRESS are set by the MSB [6 : 4] 3-bit of the MFR_BASE_ADDRESS NVM register store value. The default store value of MFR_BASE_ADDRESS NVM register is 10h. This is a read and write register. Bit Description BITS SYMBOL VALUE ACTION 6 to 0 Pins program 10h NVM register of MFR_BASE_ADDRESS default store value is 10h. Thus, MSB 3-bit [6 : 4] of MFR_BASE_ADDRESS is 001b. When a 0.845 kΩ resistor is connected between ADDR pin and ground and a Vout setting resistor is connected between VSET pin and ground, the LSB 4-bit [3 : 0] of MFR_BASE_ADDRESS is 0000b. EEPROM_PASSWORD (DBh) The EEPROM_PASSWORD command will unlock write access to the internal NVM. This command must be sent before the STORE_USER_ALL command. Access to the NVM can be disabled by sending any other data and will be automatically disabled on each power-cycle. Bit Description BITS 15 to 0 SYMBOL Block VALUE 1234h ACTION Default password for unlocking access to the NVM before the STORE_USER_ALL command MFR_BASE_ADDRESS_2 (E2h) The MFR_BASE_ADDRESS_2 command is used to read or set the unit’s PMBus address when there is no voltage setting resistor assembled between VSET pin of the PMBus unit and ground. The four least significant bits (LSB) [3 : 0] of the MFR_BASE_ADDRESS_2 are set by resistance of the resistor assembled between ADDR pin and ground. The MSB [6 : 4] 3-bit of the MFR_BASE_ADDRESS_2 are set by the MSB [6 : 4] 3-bit of MFR_BASE_ADDRESS_2 NVM register store value. The default store value of MFR_BASE_ADDRESS_2 NVM register is 50h. This is a read and write register. Bit Description BITS 6 to 0 SYMBOL Pins program S21-0213-Rev. B, 08-Mar-2021 VALUE ACTION 50h NVM register of MFR_BASE_ADDRESS_2 default store value is 50h. Thus, MSB 3-bit [6 : 4] of MFR_BASE_ADDRESS_2 is 101b. When a 0.845 kΩ resistor is connected between ADDR pin and ground and there is not a VOUT setting resistor assembled between VSET pin and ground, the LSB 4-bit [3 : 0] of MFR_BASE_ADDRESS_2 is 0000b. Document Number: 77863 34 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC453 (15 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Enable: 5V/div VIN: 5V/div Vo: 500mV/div Vo: 500mV/div Pgood: 5V/div Pgood: 5V/div Vdd: 5V/div Vdd: 5V/div Fig. 11 - SiC453 Startup with VIN, t = 5 ms/div Fig. 14 - SiC453 Shut down with EN, t = 100 ms/div VIN: 5V/div Vo: 200mV/div load: 5A/div Vo: 500mV/div Salert: 5V/div Pgood: 5V/div Vdd: 5V/div SW: 5V/div Fig. 12 - SiC453 Shut Down with VIN, t = 100 ms/div Fig. 15 - SiC453 OCP Vo: 200mV/div Enable: 5V/div Salert: 5V/div Vo: 500mV/div Pgood: 5V/div Vdd: 5V/div SW: 5V/div Fig. 13 - SiC453 Startup with EN, t = 5 ms/div S21-0213-Rev. B, 08-Mar-2021 Fig. 16 - SiC453 UVP Document Number: 77863 35 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC453 (15 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Vo: 50mV/div(AC) Vo: 50mV/div(AC) Istep: 4A/div Istep: 4A/div(AC) SW: 10V/div Fig. 17 - SiC453 Load Step, 7.5 A to 15 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) SW: 10V/div Fig. 20 - SiC453 Load Step, 0 A to 7.5 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) Istep: 4A/div(AC) Istep: 4A/div SW: 10V/div SW: 10V/div Fig. 18 - SiC453 Load Step, 15 A to 7.5 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) Fig. 21 - SiC453 Load Step, 0 A to 7.5 A, 1 A/μs, t = 10 μs/div Skip Mode Enabled Vo: 50mV/div(AC) Istep: 4A/div Istep: 4A/div SW: 10V/div Fig. 19 - SiC453 Load Step, 0 A to 7.5 A, 1 A/μs, t = 10 μs/div S21-0213-Rev. B, 08-Mar-2021 SW: 10V/div Fig. 22 - SiC453 Load Step, 7.5 A to 0 A, 1 A/μs, t = 10 μs/div Skip Mode Enabled Document Number: 77863 36 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC453 (15 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Vo: 20mV/div(AC) SW: 5V/div Fig. 23 - SiC453 Output Ripple, 0.01 A, t = 1 μs/div Forced Continuous Conduction Mode Vo: 20mV/div(AC) SW: 5V/div Fig. 26 - SiC453 Output Ripple, 15 A, t = 1 μs/div Vo: 20mV/div(AC) Enable: 5V/div Vo: 200mV/div SW: 5V/div SW: 10V/div Fig. 24 - SiC453 Output Ripple, 0.01 A, t = 20 μs/div DCM Mode Fig. 27 - SiC453 Prebias Startup Vo: 20mV/div(AC) SW: 5V/div Fig. 25 - SiC453 Output Ripple, 7.5 A, t = 1 μs/div S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 37 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC451 (25 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Enable: 5V/div VIN: 5V/div Vo: 500mV/div Vo: 500mV/div Pgood: 5V/div Pgood: 5V/div Vdd: 5V/div Vdd: 5V/div Fig. 28 - SiC451 Startup with VIN, t = 5 ms/div VIN: 5V/div Fig. 31 - SiC451 Shut down with EN, t = 100 ms/div Vo: 200mV/div load: 10A/div Vo: 500mV/div Salert: 5V/div Pgood: 5V/div SW: 10V/div Vdd: 5V/div Fig. 29 - SiC451 Shut Down with VIN, t = 100 ms/div Fig. 32 - SiC451 OCP Vo: 200mV/div Enable: 5V/div Salert: 5V/div Vo: 500mV/div SW: 5V/div Pgood: 5V/div Vdd: 5V/div Fig. 30 - SiC451 Startup with EN, t = 2 ms/div S21-0213-Rev. B, 08-Mar-2021 Fig. 33 - SiC451 UVP Document Number: 77863 38 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC451 (25 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Vo: 50mV/div(AC) Vo: 50mV/div(AC) Istep: 10A/div Istep: 10A/div(AC) SW: 5V/div Fig. 34 - SiC451 Load Step, 12.5 A to 25 A, 10 A/μs, t = 10 μs/div Vo: 50mV/div(AC) SW: 5V/div Fig. 37 - SiC451 Load Step, 12.5 A to 0 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) Istep: 10A/div(AC) Istep: 10A/div SW: 5V/div SW: 5V/div Fig. 35 - SiC451 Load Step, 25 A to 12.5 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) Fig. 38 - SiC451 Load Step, 0 A to 12.5 A, 1 A/μs, t = 10 μs/div Skip Mode Enabled Vo: 50mV/div Istep: 10A/div Istep: 10A/div SW: 5V/div Fig. 36 - SiC451 Load Step, 0 A to 12.5 A, 1 A/μs, t = 10 μs/div S21-0213-Rev. B, 08-Mar-2021 SW: 5V/div Fig. 39 - SiC451 Load Step, 12.5 A to 0 A, 1 A/μs, t = 10 μs/div Skip Mode Enabled Document Number: 77863 39 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC451 (25 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Vo: 20mV/div(AC) SW: 5V/div Fig. 40 - SiC451 Output Ripple, 0.01 A, t = 1 μs/div Forced Continuous Conduction Mode Vo: 20mV/div(AC) Vo: 20mV/div(AC) SW: 5V/div Fig. 43 - SiC451 Output Ripple, 25 A, t = 1 μs/div Forced Continuous Conduction Mode Enable: 5V/div Vo: 200mV/div SW: 5V/div Fig. 41 - SiC451 Output Ripple, 0.01 A, t = 2 ms/div DCM Mode SW: 10V/div Fig. 44 - SiC451 Prebias Startup Vo: 20mV/div(AC) SW: 5V/div Fig. 42 - SiC451 Output Ripple, 12.5 A, t = 1 μs/div Forced Continuous Conduction Mode S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 40 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC450 (40 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Enable: 5V/div Vo: 500mV/div VIN: 5V/div Vo: 500mV/div Pgood: 5V/div Pgood: 5V/div Vdd: 5V/div Vdd: 5V/div Fig. 45 - SiC450 Startup with VIN, t = 5 ms/div Fig. 48 - SiC450 Shut down with EN, t = 100 ms/div VIN: 5V/div Salert: 5V/div Vo: 500mV/div load: 20A/div Vo: 500mV/div Pgood: 5V/div Vdd: 5V/div SW: 5V/div Fig. 46 - SiC450 Shut Down with VIN, t = 100 ms/div Fig. 49 - SiC450 Overcurrent Protection Behavior, t = 10 μs Salert: 5V/div Enable: 5V/div Vo: 500mV/div SW: 5V/div Vo: 500mV/div Pgood: 5V/div Vdd: 5V/div Fig. 47 - SiC450 Startup with EN, t = 5 ms/div S21-0213-Rev. B, 08-Mar-2021 Fig. 50 - SiC450 Output Undervoltage Protection Behavior, t = 5 μs/div Document Number: 77863 41 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC450 (40 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Vo: 50mV/div(AC) Vo: 50mV/div(AC) Istep: 10A/div(AC) Istep: 10A/div SW: 10V/div Fig. 51 - SiC450 Load Step, 20 A to 40 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) SW: 10V/div Fig. 54 - SiC450 Load Step, 20 A to 0 A, 1 A/μs, t = 10 μs/div Vo: 50mV/div(AC) Istep: 10A/div(AC) Istep: 10A/div SW: 10V/div SW: 10V/div Fig. 52 - SiC450 Load Step, 40 A to 20 A, 10 A/μs, t = 10 μs/div Fig. 55 - SiC450 Load Step, 0 A to 20 A, 1 A/μs, t = 10 μs/div Skip Mode Enabled Vo: 50mV/div(AC) Vo: 50mV/div(AC) Istep: 10A/div Istep: 10A/div SW: 10V/div Fig. 53 - SiC450 Load Step, 0 A to 20 A, 1 A/μs, t = 10 μs/div S21-0213-Rev. B, 08-Mar-2021 SW: 10V/div Fig. 56 - SiC450 Load Step, 20 A to 0 A, 1 A/μs, t = 10 μs/div Skip Mode Enabled Document Number: 77863 42 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, fsw = 600 kHz, SiC450 (40 A), CIN = 2.2 μF x 3, COUT = 47 μF x 12, unless otherwise noted) Vo: 20mV/div(AC) Vo: 20mV/div(AC) SW: 5V/div Fig. 57 - SiC450 Output Ripple, 0.01 A, t = 1 μs/div Forced Continuous Conduction Mode SW: 5V/div Fig. 60 - SiC450 Output Ripple, 40 A, t = 1 μs/div Forced Continuous Conduction Mode Vo: 20mV/div(AC) Enable: 5V/div Vo: 200mV/div SW: 5V/div SW: 10V/div Fig. 58 - SiC450 Output Ripple, 0.01 A, t = 50 μs/div DCM Mode Fig. 61 - SiC450 Prebias Startup Vo: 20mV/div(AC) SW: 5V/div Fig. 59 - SiC450 Output Ripple, 20 A, t = 1 μs/div Forced Continuous Conduction Mode S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 43 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes and Decoupling Step 3: VSWH Plane VIN plane Snubber VIN PGND plane VSWH PGND plane VSWH Fig. 62 1. Layout VIN and PGND planes as shown above 2. Ceramic capacitors should be placed right between VIN and PGND, and very close to the device for best decoupling effect 3. Difference values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603 4. Smaller capacitance value, closer to device VIN pin(s) better high frequency noise absorbing Fig. 64 1. Connect output inductor to SiC45x with large plane to lower the resistance Step 2: VIN Pin 2. If any snubber network is required, place the components on the bottom side as shown above A GND plane VIN decouple cap Fig. 63 1. VIN (pin 23) is the input pin for both internal LDO and tON block. tON time varies based on input voltage. It is necessary to put a decouple cap close to this pin S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 44 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Step 4: VDD/PVCC Input Filter Vishay Siliconix Step 6: Signal Routing VOUT sense signals PGND GND AGND plane Fig. 67 Fig. 65 1. CVDD and CPVCC caps should be placed close to the IC to filter noise and provide maximum instantaneous driver current for low side MOSFET during switching cycle Step 5: BOOT Resistor and Capacitor Placement 1. Separate the small analog signal from high current path. As shown above, the high current paths with high dv/dt, di/dt are placed on the right side of the IC, while the small control signals are placed on the left side of the IC. All the components for small analog signal should be placed closer to IC with minimum trace length 2. Pin 16 is considered as IC analog ground, which should have single connection to power ground. The AGND ground plane connected with pin 16 helps to keep AGND quite and improve noise immunity 3. Vsen+ / Vsen- differential analog signal pair should layout using minimum clearance. Also, the differential pair should be far away from VSWH node and other signals throughout the length of the trace. Ground shield is highly recommended Fig. 66 1. These components need to be placed very close to SiC45x, right between PHASE (pin 4) and BOOT (pin 6) 2. To reduce parasitic inductance, chip size 0402 can be used S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 45 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix Step 7: Adding Thermal Relief Vias and Duplicate Power Path Plane Step 8: Ground Layer VIN plane PGND plane A GND plane PGND plane Fig. 69 1. It is recommended to make the whole inner 1 layer (next to top layer) ground plane VSWH Fig. 68 1. Thermal relief Vias can be added on the VIN and PGND pads to utilize inner layers for high current and thermal dissipation 2. This ground plane provides shielding between noise source on top layer and signal trace within inner layer 3. The ground plane can be broken into two section as power ground and analogue ground 2. To achieve better thermal performance, additional Vias can be put on VIN plane and PGND plane. It is also necessary to duplicate the VIN and ground plane at bottom layer to maximize the power dissipation capability from PCB 3. VSWH pad is a noise source and not recommended to put Vias on this pad 4. 8 mil drill for pads and 10 mils drill for plane can be the optional Via size. The Vias on pad may drain solder during assembly and cause assembly issue. Please consult with the assembly house for guideline S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 46 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PRODUCT SUMMARY Part number SiC450 SiC451 SiC453 Description 4.5 V to 20 V input 40 A microBUCK DC/DC converter with PMBus 4.5 V to 20 V input 25 A microBUCK DC/DC converter with PMBus 4.5 V to 20 V input 15 A microBUCK DC/DC converter with PMBus Input voltage min. (V) 4.5 4.5 4.5 Input voltage max. (V) 20 20 20 Output voltage min. (V) 0.3 0.3 0.3 Output voltage max. (V) 12 12 12 Continuous current (A) 40 25 15 Switch frequency min. (kHz) 300 300 300 Switch frequency max. (kHz) 1500 1500 1500 Pre-bias operation (yes / no) yes yes yes Internal bias reg. (yes / no) yes yes yes internal internal internal Enable (yes / no) yes yes yes PGOOD (yes / no) yes yes yes Over current protection yes yes yes OVP, OCP, UVP/SCP, OTP, UVLO OVP, OCP, UVP/SCP, OTP, UVLO OVP, OCP, UVP/SCP, OTP, UVLO Light load mode yes yes yes Peak efficiency (%) 96 96 96 PowerPAK MLP34-57 PowerPAK MLP34-57 PowerPAK MLP34-57 5.0 x 7.0 x 0.75 Compensation Protection Package type Package size (W, L, H) (mm) 5.0 x 7.0 x 0.75 5.0 x 7.0 x 0.75 Status code 1 1 1 Product type microBUCK microBUCK microBUCK Applications Computer, industrial, networking Computer, industrial, networking Computer, industrial, networking Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?77863. S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 47 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 09-Jul-2021 1 Document Number: 91000