SiHFPS37N50A
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Power MOSFET
FEATURES
D
• Low gate charge Qg results in simple drive
requirement
Super-247
• Improved gate, avalanche and dynamic dV/dt
ruggedness
G
• Fully
characterized
capacitance
avalanche voltage and current
S
D
G
• Effective Coss specified
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
N-Channel MOSFET
PRODUCT SUMMARY
APPLICATIONS
VDS (V)
500
RDS(on) (Max.) (Ω)
and
• Switch mode power supply (SMPS)
VGS = 10 V
0.13
• Uninterruptible power supply
Qg (Max.) (nC)
180
Qgs (nC)
46
• High speed power switching
71
TYPICAL SMPS TOPOLOGIES
Qgd (nC)
Configuration
Single
• Full bridge converters
• Power factor correction boost
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
Super-247
SiHFPS37N50A-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
500
Gate-source voltage
VGS
± 30
VGS at 10 V
Continuous drain current
TC = 25 °C
TC = 100 °C
ID
UNIT
V
36
23
A
Pulsed drain currenta
IDM
144
3.6
W/°C
Single pulse avalanche energy b
EAS
1260
mJ
Repetitive avalanche current a
IAR
36
A
Repetitive avalanche energy a
EAR
44
mJ
Linear derating factor
Maximum power dissipation
TC = 25 °C
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature)
for 10 s
PD
446
W
dV/dt
3.5
V/ns
TJ, Tstg
- 55 to + 150
300 d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 1.94 mH, Rg = 25 Ω, IAS = 36 A (see fig. 12)
c. ISD ≤ 36 A, dI/dt ≤ 145 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
40
Case-to-sink, flat, greased surface
RthCS
0.24
-
Maximum junction-to-case (drain)
RthJC
-
0.28
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
Static
Drain-source breakdown voltage
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 150 °C
-
-
250
Gate-source threshold voltage
Drain-source on-state resistance
Forward transconductance
RDS(on)
gfs
ID = 22 A b
VGS = 10 V
VDS = 50 V, ID = 22 A b
μA
-
-
0.13
Ω
20
-
-
S
-
5579
-
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Output capacitance
Effective output capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VDS = 1.0 V, f = 1.0 MHz
VGS = 0 V
Coss eff.
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
-
810
-
-
36
-
-
7905
-
VDS = 400 V, f = 1.0 MHz
-
221
-
VDS = 0 V to 400 V
-
400
-
-
-
180
-
-
46
ID = 36 A, VDS = 400 V,
see fig. 6 and 13 b
Gate-drain charge
Qgd
-
-
71
Turn-on delay time
td(on)
-
23
-
Rise time
Turn-off delay time
Fall time
tr
td(off)
VDD = 250 V, ID = 36 A,
RG = 2.15 Ω, RD = 7.0 Ω,
see fig. 10 b
tf
pF
nC
-
98
-
-
52
-
-
80
-
-
-
36
-
-
144
-
-
1.5
-
570
860
ns
-
8.6
13
μC
ns
Drain-source body diode characteristics
Continuous source-drain diode current
Pulsed diode forward current a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 36 A, VGS = 0 V b
TJ = 25 °C, IF = 36 A, dI/dt = 100 A/μs b
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS
S21-0019-Rev. D, 18-Jan-2021
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
TOP
100
10
4.5V
1
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
100
ID = 36A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
100000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
60
80 100 120 140 160
V GS = 0V,
f = 1MHz
C iss = C gs + C gd, C dsSHORTED
C rss = C gd
C oss = C ds + C gd
C, Capacitance (pF)
TOP
I D , Drain-to-Source Current (A)
40
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
10
4.5V
10000
C iss
1000
C oss
100
Crss
20µs PULSE WIDTH
TJ = 150 ° C
1
0.1
1
10
10
100
A
1
VDS , Drain-to-Source Voltage (V)
20
VGS , Gate-to-Source Voltage (V)
100
TJ = 150 ° C
TJ = 25 ° C
10
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
1000
ID = 36A
VDS = 400V
VDS = 250V
VDS = 100V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
9.0
VGS , Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0019-Rev. D, 18-Jan-2021
100
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
1000
1
4.0
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
I D , Drain-to-Source Current (A)
20
TJ , Junction Temperature ( °C)
VDS , Drain-to-Source Voltage (V)
100
VGS = 10V
0
0
40
80
120
160
200
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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1000
ISD , Reverse Drain Current (A)
VDS
VGS
100
RD
D.U.T.
RG
+
- VDD
TJ = 150 ° C
10 V
10
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
TJ = 25 ° C
Fig. 10a - Switching Time Test Circuit
1
0.1
0.2
VDS
V GS = 0 V
0.4
0.6
0.8
1.0
1.2
1.4
90 %
VSD ,Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
10 %
VGS
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
td(on)
tr
td(off) tf
ID , Drain Current (A)
Fig. 10b - Switching Time Waveforms
10us
100
100us
10
1
1ms
10ms
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
ID , Drain Current (A)
40
30
20
10
0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
S21-0019-Rev. D, 18-Jan-2021
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Thermal Response (Z thJC )
1
D = 0.50
0.1
0.20
0.10
0.05
PDM
0.02
0.01
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
EAS , Single Pulse Avalanche Energy (mJ)
3000
TOP
2500
15 V
BOTTOM
ID
16A
23A
36A
2000
Driver
L
VDS
1500
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
1000
500
0
25
tp
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
VDS
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
IAS
Fig. 12b - Unclamped Inductive Waveforms
V DSav , Avalanche Voltage (V)
580
560
540
520
500
A
0
10
20
30
40
I av , Avalanche Current (A)
Fig. 12d - Maximum Avalanche Energy vs. Drain Current
S21-0019-Rev. D, 18-Jan-2021
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Current regulator
Same type as D.U.T.
QG
10 V
50 kΩ
QGS
QGD
12 V
0.2 µF
0.3 µF
+
D.U.T.
VG
-
VDS
VGS
Charge
Fig. 13a - Basic Gate Charge Waveform
3 mA
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
S21-0019-Rev. D, 18-Jan-2021
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg??91258.
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91258
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Package Information
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TO-274AA (High Voltage)
VERSION 1: FACILITY CODE = Y
B
A
E
E4
A
D2
E1
A1
R
D1
D
L1
L
Detail “A”
C
b
e
A2
0.10 (0.25) M B A M
10°
b4
b2
Lead Tip
5°
Detail “A”
Scale: 2:1
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
4.70
5.30
0.185
0.209
D1
15.50
16.10
0.610
0.634
A1
1.50
2.50
0.059
0.098
D2
0.70
1.30
0.028
0.051
A2
2.25
2.65
0.089
0.104
E
15.10
16.10
0.594
0.634
13.30
13.90
0.524
0.547
b
1.30
1.60
0.051
0.063
E1
b2
1.80
2.20
0.071
0.087
e
5.45 BSC
MAX.
0.215 BSC
b4
3.00
3.25
0.118
0.128
L
13.70
14.70
0.539
0.579
c (1)
0.38
0.89
0.015
0.035
L1
1.00
1.60
0.039
0.063
D
19.80
20.80
0.780
0.819
R
2.00
3.00
0.079
0.118
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outer extremes of the plastic body
• Outline conforms to JEDEC® outline to TO-274AA
(1) Dimension measured at tip of lead
Revision: 19-Oct-2020
Document Number: 91365
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VERSION 2: FACILITY CODE = N
A
E
A
E3
B
D
D1
D2
E2
Q
A2
L1
F
F
H
H
C
G
L
G
A1
e
b
3x
0.25 M B A M
b1
C
b3
E4
E1
b’, b2, b4
C
C’
Base metal
b, b1, b3
Plating
SECTION "F-F", "G-G" AND "H-H"
SCALE: NONE
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
MAX.
A
4.83
5.21
D1
16.25
17.65
A1
2.29
2.54
D2
0.50
0.80
A2
1.91
2.16
E
15.75
16.13
b’
1.07
1.28
E1
13.10
14.15
b
1.07
1.33
E2
3.68
5.10
b1
1.91
2.41
E3
1.00
1.90
b2
1.91
2.16
E4
12.38
13.43
b3
2.87
3.38
e
b4
2.87
3.13
N
c’
0.55
0.65
L
19.81
c
0.55
0.68
L1
3.70
4.00
D
20.80
21.10
Q
5.49
6.00
5.44 BSC
3
20.32
ECN: E20-0538-Rev. C, 19-Oct-2020
DWG: 5975
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Outline conforms to JEDEC® outline to TO-274AD
• Dimensions are measured in mm, angles are in degree
• Metal surfaces are tin plated, except area of cut
Revision: 19-Oct-2020
Document Number: 91365
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Disclaimer
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