VBUS54CV-HSF-G4-08

VBUS54CV-HSF www.vishay.com Vishay Semiconductors 4-Line BUS-Port ESD Protection FEATURES • Ultra compact LLP75-6L package • 4-line USB ESD protection 6 5 4 • Low leakage current • Low load capacitance CD = 1.2 pF 20397 1 2 • ESD immunity acc. IEC 61000-4-2 ± 30 kV contact discharge ± 30 kV air discharge 3 • High surge current acc. IEC 61000-4-5 Ipp > 11 A 20453 • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu), (no Sn) 1 MARKING (example only) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 XX YY            21001 Dot = pin 1 marking XX = date code  YY = type code (see table below) DESIGN SUPPORT TOOLS click logo to get started Models Available ORDERING INFORMATION DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VBUS54CV-HSF VBUS54CV-HSF-G4-08 3000 15 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VBUS54CV-HSF LLP75-6L UC 4.2 mg UL 94 V-0 MSL level 1 (according J-STD-020) Peak temperature max. 260 °C ABSOLUTE MAXIMUM RATINGS VBUS54CV-HSF PARAMETER Peak pulse current Peak pulse power ESD immunity Operating temperature Storage temperature Rev. 1.3, 04-Jan-2019 TEST CONDITIONS Pin 1, 3, 4 or 6 to pin 2 acc. IEC 61000-4-5, tp = 8/20 μs/single shot Pin 5 to pin 2 acc. IEC 61000-4-5; tp = 8/20 μs; single shot Pin 1, 3, 4 or 6 to pin 2 acc. IEC 61000-4-5, tp = 8/20 μs/single shot Pin 5 to pin 2 acc. IEC 61000-4-5; tp = 8/20 μs; single shot Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature SYMBOL VALUE UNIT 11 A IPPM 13 242 W PPP 246 VESD ± 30 ± 30 kV TJ -40 to +125 °C TSTG -40 to +150 °C Document Number: 84145 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54CV-HSF www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VBUS54CV-HSF (pin 1, 3, 4, or 6 to pin 2) (Tamb = 25 °C, unless otherwise specified) PARAMETER Protection paths Reverse stand-off voltage TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 4 lines V Max. reverse working voltage VRWM - - 5.5 Reverse voltage at IR = 0.1 μA VR 5.5 - - V Reverse current at VRWM = 5.5 V IR - 0.01 0.1 μA Reverse breakdown voltage at IR = 1 mA VBR 7 7.9 8.6 V Reverse clamping voltage at IPP = 11 A VC - 18 22 V Forward clamping voltage at IPP =11 A VF - 6.5 8 V VR (at I/O pin) = 0 V VR (at pin 5) = 5 V; f = 1 MHz CD - 1.2 2.5 pF Difference of the line capacitances dCD - - 0.2 pF TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Capacitance Line symmetry ELECTRICAL CHARACTERISTICS (pin 5 to pin 2) (Tamb = 25 °C, unless otherwise specified) PARAMETER Max. reverse working voltage VRWM - - 5.5 V Reverse voltage at IR = 0.1 μA; pin 2 to pin 1 VR 5.5 - - V Reverse current Reverse stand-off voltage at VRWM = 5.5 V IR - 0.01 0.1 μA Reverse breakdown voltage at IR = 1 mA VBR 6.3 7.1 8 V Reverse clamping voltage at IPP = 13 A VC - 18 22 V at IPP =13 A VF - - 7 V VR (at pin 5) = 0 V; f = 1 MHz CD - 190 - pF Forward clamping voltage Capacitance APPLICATION NOTE With the VBUS54CV-HSF a double, high speed USB-port can be protected against transient voltage signals. Negative transients will be clamped close below the ground level while positive transients will be clamped close above the working range. An avalanche diode clamps the supply line (VBUS at pin 5) to ground (pin 2). The high speed data lines, D1+, D2+, D1- and D2-, are connected to pin 1, 3, 4 and 6. As long as the signal voltage on the data lines is between the ground- and the VBUS -level, the low capacitance PN-diodes offer a very high isolation to VBUS, ground and to the other data lines. But as soon as any transient signal exceeds this working range, one of the PN-diodes gets in the forward mode and clamps the transient to ground or the avalanche break through voltage level. t w VBUS i D1+ n D1U S B P o D2+ r D2t G ND 6 5 4 1 2 3 R E C E I V E R IC 20399 Rev. 1.3, 04-Jan-2019 Document Number: 84145 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54CV-HSF www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 200 120 % 100 % Discharge Current IESD f = 1 MHz 180 Rise time = 0.7 ns to 1 ns 160 140 CD (pF) 80 % 60 % 53 % P in 5 to pin 2 120 100 80 40 % 60 27 % 40 20 % 20 0 0% -10 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 21357 Time (ns) 20557 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 4 5 6 VR (V) Fig. 4 - Typical Capacitance CD vs. Reverse Voltage VR 100 8 µs to 100 % 100 % 10 80 % IF (mA) Pin 5 to pin 2 IPPM 60 % 20 µs to 50 % 40 % 1 0.1 Pin 1, 3, 4 or 6 to pin 2 0.01 20 % 0% 0 10 20 30 Time (µs) 20548 0.001 0.5 40 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 0.7 0.8 0.9 1 VF (V) Fig. 5 - Typical Forward Current IF vs. Forward current IR 9 2.5 f = 1 MHz 8 2.0 Pin 1, 3, 4 or 6 to pin 2 7 Pin 1, 3, 4 or 6 to pin 2 6 1.5 VR (V) CD (pF) 0.6 21358 VR at pin 5 = 5 V 1.0 Pin 5 to pin 2 5 4 3 2 0.5 1 0 0.01 0 0 21356 1 2 3 4 5 6 VR (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.3, 04-Jan-2019 21359 0.1 1 10 100 1000 10 000 IR (µA) Fig. 6 - Typical Reverse Voltage VR vs. Reverse Current IR Document Number: 84145 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54CV-HSF www.vishay.com Vishay Semiconductors 25 60 P in 1, 3, 4 o r 6 to pin 2 acc. IEC 61000-4-2 + 8 kV contact discharge Pin 1, 3, 4 or 6 to pin 2 40 20 VC-ESD (V) VC (V) 20 15 10 P in 5 to pin 2 VC 0 - 20 - 40 5 - 60 Measured acc. IEC 61000-4-5 (8/20µs - wave form) 0 0 21360 5 10 - 80 - 10 0 10 20 30 40 50 60 70 80 90 15 IPP (A) Fig. 7 - Typical Peak Clamping Voltage vs. Peak Pulse Current IPP 21362 Fig. 9 - Typical Clamping Performance at 8 kV Contact Discharge (acc. IEC 61000-4-2) 300 80 60 acc. IEC 61000-4-2 + 8 kV contact discharge Pin 1, 3, 4 or 6 to pin 2 100 VC-ESD (V) 20 - 100 - 20 - 200 21361 - 300 0 10 20 30 40 50 60 70 80 90 t (ns) Fig. 8 - Typical Clamping Performance at 8 kV Contact Discharge (acc. IEC 61000-4-2) Rev. 1.3, 04-Jan-2019 VC-ESD 0 0 - 40 - 10 0 acc. IEC 61000-4-2 contact discharge Pin 1, 3, 4 or 6 to pin 2 200 40 VC-ESD (V) t (ns) 21363 5 10 15 20 25 30 VESD (kV) Fig. 10 - Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Document Number: 84145 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54CV-HSF www.vishay.com Vishay Semiconductors 0.45 (0.018) 0.55 (0.022) 0.2 (0.008) 0.3 (0.012) 0.2 (0.008) 0.3 (0.012) 1 (0.039) 0.2 (0.008) 0.3 (0.012) Heat sink 0.95 (0.037) 1.05 (0.041) PACKAGE DIMENSIONS in millimeters (inches): LLP75-6L 0.5 (0.020) 0.6 (0.024) 0.54 (0.021) 0.60 (0.023) 0.05 (0.002) 0 (0.000) 0.15 (0.006) 0.25 (0.010) 1.65 (0.065) 1.55 (0.061) 1.55 (0.061) 1.65 (0.065) Pin 1 marking Foot print recommendation: 0.5 (0.020) 0.5 (0.020) 0.3 (0.012) 0.3 (0.012) Document no.:S8-V-3906.02-010 (4) Created - Date: 04. MAY 2005 Rev. 4 - Date: 21. March 2006 0.15 (0.006) 1 (0.039) 0.5 (0.020) 1 (0.039) 0.25 (0.010) 0.15 (0.006) Solder resist mask Solder pad 0.5 (0.020) 20454 Rev. 1.3, 04-Jan-2019 Document Number: 84145 5 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54CV-HSF www.vishay.com Vishay Semiconductors LLP75-6x S9 F5 Pad layout - view from top / seen at bottom side S8-V-3906.02-004 (4) 10.01.2005 Rev. 1.3, 04-Jan-2019 Pin 1 - location Document Number: 84145 6 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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