VBUS54ED-FBL-G4-08

VBUS54ED-FBL www.vishay.com Vishay Semiconductors 4-Line BUS-Port ESD Protection - Flow Through Design FEATURES • Compact LLP2510-10L package nc. 10 nc. GND nc. 9 8 7 nc. 6 • Low package height < 0.6 mm • 4-line ESD-protection • Low leakage current IR < 0.1 μA • Low load capacitance CD = 0.6 pF 22551 1 2 3 4 5 D1+ D1- GND D2+ D222552 • Ideal for high speed data line like - HDMI, DisplayPort, eSATA - USB, 1394/firewire • ESD-protection acc. IEC 61000-4-2 ± 15 kV contact discharge ± 15 kV air discharge • Soldering can be checked by standard vision inspection. No X-ray necessary 20720 MARKING (example only) YYXX Dot = pin 1 marking YY = type code (see table below) XX = date code • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) • Compliant to RoHS directive 2002/95/EC and in accordance to WEEE 2002/96/EC Note ** Please see document “Vishay Material Category Policy”: www.vishay.com/doc?99902 ORDERING INFORMATION DEVICE NAME VBUS54ED-FBL ORDERING CODE VBUS54ED-FBL-G4-08 TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) 3000 MINIMUM ORDER QUANTITY 15 000 PACKAGE DATA DEVICE NAME VBUS54ED-FBL PACKAGE NAME LLP2510-10L TYPE CODE L5 WEIGHT 3.9 mg MOLDING COMPOUND FLAMMABILITY RATING UL 94 V-0 MOISTURE SENSITIVITY LEVEL MSL level 1 (according J-STD-020) SOLDERING CONDITIONS 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS PARAMETER Peak pulse current Peak pulse power ESD immunity Operating temperature Storage temperature TEST CONDITIONS Acc. IEC 61000-4-5; tP = 8/20 μs; single shot Acc. IEC 61000-4-5; tP = 8/20 μs; single shot Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature SYMBOL IPPM PPP VESD VESD TJ TSTG VALUE 2 25 ± 15 ± 15 - 40 to + 125 - 55 to + 150 UNIT A W kV kV °C °C Rev. 1.0, 15-Aug-11 1 For technical questions, contact: ESDprotection@vishay.com Document Number: 82414 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54ED-FBL www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VBUS54ED-FBL (pin 1, 2, 4 or 5 to pin 3) PARAMETER Protection paths Reverse stand-off voltage Reverse voltage Reverse current Reverse breakdown voltage Clamping voltage Forward clamping voltage Line capacitance at IR = 0.1 μA at VR = VRWM = 5.5 V at IR = 1 mA at IPP = 1 A; acc. IEC 61000-4-5 at IPP = 2 A; acc. IEC 61000-4-5 at IF = 1 A; acc. IEC 61000-4-5 at IF = 2 A; acc. IEC 61000-4-5 at VR = 0 V; f = 1 MHz at VR = 3.3 V; f = 1 MHz TEST CONDITIONS/REMARKS Number of lines which can be protected SYMBOL Nchannel VRWM VR IR VBR VC VC VF VF CD MIN. 5.5 6.9 TYP. 6.3 0.02 7.5 9.1 10.3 1.9 2.5 0.7 0.6 MAX. 4 5.5 7.5 0.1 8.7 11 12.5 2.2 3.1 0.8 0.8 UNIT lines V V μA V V V V V pF Note • Ratings at 25 °C, ambient temperature unless otherwise specified APPLICATION NOTE The VBUS54ED-FBL is a four-line ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a very low capacitance which makes it usable for high frequency applications like USB2.0, USB3.0 or HDMI. With the VBUS54ED-FBL four high speed data lines can be protected against transient voltage signals like ESD (Electro Static Discharge). Connected to the data line (pin 1, 2 and pin 4, 5) and to ground (pin 3 and 8) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping behaviour of the VBUS54ED-FBL is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5.5 V. Pin configuration: • Pin 3 and 8 are internally shorted and have to be connected to ground • Pin 1, 2 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2• Pin 6, 7 and 9, 10 are not connected internally -----USB / HDMI Interface D1+ matched pair D1D2+ matched pair 9 8 7 6 2 3 4 5 D1- GND D2+ I/O Port Connector D2D2- nc. 10 nc. GND nc. 9 8 7 nc. 6 10 1 2 3 4 5 D1+ D1- GND D2+ D222552 1 D1+ 22553 FLOW THROUGH DESIGN Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI). At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and distances. With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the VBUS54ED-FBL is placed on top without any vias or loops. Rev. 1.0, 15-Aug-11 2 For technical questions, contact: ESDprotection@vishay.com Document Number: 82414 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54ED-FBL www.vishay.com TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 120 % Rise time = 0.7 ns to 1 ns 100 BiAs-mode 10 Vishay Semiconductors Discharge Current IESD 100 % 80 % 60 % 53 % IF (mA) 1 0.1 40 % 27 % 20 % 0% - 10 0 10 20 30 40 50 60 70 80 90 100 20557 0.01 0.001 0.5 22555 0.6 0.7 0.8 0.9 1 1.1 Time (ns) VF (V) Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 8 100 % 80 % 8 µs to 100 % 7 6 5 VR (V) IPPM 60 % 20 µs to 50 % 40 % 20 % 0% 0 10 20 30 40 4 3 2 Pin 1, 2, 4 or 5 to Pin 3 1 0 0.01 0.1 1 10 100 1000 10 000 20548 Time (µs) 22556 IR (µA) Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 0.9 f = 1 MHz 0.8 0.7 Second pin at 0 V 14 12 10 8 Pin 1, 2, 4 or 5 to Pin 3 (reverse) VC Pin 3 to Pin 1, 2, 4 or 5 (forward) 0.6 Second pin at 3.3 V C D pF 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 Pin 1, 2, 4 or 5 to Pin 3 and 8 Second pin at 5 V VC (V) 6 4 2 0 -2 - 4 Measured acc. IEC 61000-4-5 (8/20 μs - wave form) -6 0 1 2 3 22554 VR in (V) IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.0, 15-Aug-11 3 For technical questions, contact: ESDprotection@vishay.com Document Number: 82414 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54ED-FBL www.vishay.com Vishay Semiconductors 100 80 60 Acc. IEC 61000-4-2 + 8 kV contact discharge 60 50 40 Acc. IEC 61000-4-2 contact discharge VC-ESD (V) VC-ESD (V) 30 20 10 0 - 10 - 20 - 30 Clamping voltage measured after 30 ns 40 20 0 - 20 - 10 0 10 20 30 40 50 60 70 80 90 - 40 0 5 10 15 20 22558 t (ns) VESD (kV) Fig. 9 - Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Fig. 7 - Typical Clamping Performance at 8 kV Contact Discharge (acc. IEC 61000-4-2) 20 0 - 20 Acc. IEC 61000-4-2 - 8 kV contact discharge VC-ESD (V) - 40 - 60 - 80 - 100 - 120 - 10 0 10 20 30 40 50 60 70 80 90 22559 t (ns) Fig. 8 - Typical Clamping Performance at 8 kV Contact Discharge (acc. IEC 61000-4-2) Rev. 1.0, 15-Aug-11 4 For technical questions, contact: ESDprotection@vishay.com Document Number: 82414 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54ED-FBL www.vishay.com PACKAGE DIMENSIONS in millimeters: LLP2510-10L PIN 1 identification Chamfer L A A3 Package = Chip Dimensions in mm PIN 1 marking Vishay Semiconductors b e L Millimeters min. A A1 A3 D E b L e 0.50 0.00 2.45 0.95 0.15 0.30 nom. 0.55 0.15 2.50 1.00 0.20 0.35 0.50 max. 0.60 0,05 2.55 1.05 0.25 0.40 - A1 E foot print recommendation: 4 x 0.5 = 2 0.5 0.25 0.5 D 0.15 1 0.35 solder resist mask solder pad Document no.: S8-V-3906.04-027 (4) Created - Date: 08. July 2011 22587 Pin 1 - Location LLP2510 Top view S8-V-3906.04-029 (4) date: 07.07.2011 22588 pad layout - view from top seen at bottom side Rev. 1.0, 15-Aug-11 5 For technical questions, contact: ESDprotection@vishay.com Document Number: 82414 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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