VBUS54DD-HS4-G4-08

VBUS54DD-HS4 www.vishay.com Vishay Semiconductors 4-Line BUS-Port ESD Protection FEATURES • Ultra compact LLP1010-6M package 5 • Low package height < 0.4 mm 4 • 4-line USB ESD protection 6 • Low leakage current • Low load capacitance CD = 0.8 pF 1 2 3 • ESD immunity acc. IEC 61000-4-2 ± 15 kV contact discharge ± 15 kV air discharge 20897 20896 • Pin plating NiPdAu (e4) no whisker growth • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 MARKING (example only)            XY 20932 Dot = pin 1 marking X = date code Y = type code (see table below) DESIGN SUPPORT TOOLS click logo to get started Models Available ORDERING INFORMATION DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VBUS54DD-HS4 VBUS54DD-HS4-G4-08 5000 5000 PACKAGE DATA PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING LLP1010-6M D 1.07 mg UL 94 V-0 DEVICE NAME VBUS54DD-HS4 MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS MSL level 1 Peak temperature max. 260 °C (according J-STD-020) ABSOLUTE MAXIMUM RATINGS VBUS54DD-HS4 TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current Pin 1, 3, 4 or 5 to pin 2 or 6 acc. IEC 61000-4-5; tp = 8/20 µs; single shot IPPM 3 A Peak pulse power Pin 1, 3, 4 or 5 to pin 2 or 6 acc. IEC 61000-4-5; tp = 8/20 µs; single shot PPP 57 W ± 15 kV ± 15 kV TJ -40 to +125 °C TSTG -55 to +150 °C PARAMETER ESD immunity Operating temperature Storage temperature Rev. 1.5, 04-Jan-2019 Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature VESD Document Number: 83384 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54DD-HS4 www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VBUS54DD-HS4 (Pin 1, 3, 4, or 5 to pin 2 or 6) (Tamb = 25 °C, unless otherwise specified) PARAMETER Protection paths TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 4 lines VRWM - - 5.5 V at VIN = VRWM = 5.5 V IR - < 0.01 0.1 μA Reverse stand-off voltage Reverse current Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage at IR = 1 mA VBR 6.9 8 8.7 V at IPP = 3 A acc. IEC 61000-4-5 VC - 16 19 V at IF = 3 A acc. IEC 61000-4-5 VF - 3.5 4.5 V - 0.8 1 pF - 0.5 0.8 pF VIN = 0 V; any other I/O pin at 3.3 V Capacitance VIN = 2.5 V; any other I/O pin at 3.3 V CD APPLICATION NOTE With the VBUS54DD-HS4 a double, high speed USB-port or up to 4 other high speed signal or data lines can be protected against transient voltage signals. Negative transients will be clamped close below the ground level while positive transients will be clamped close above the working range. The high speed data lines, D1+, D2+, D1- and D2-, are connected to pin 1, 3, 4, and 5, pin 2 or 6 are connected to ground. As long as the signal voltage on the data lines is between the ground- and the break down level, the low input capacitance of each channel offers a very high isolation to ground and to the other data lines. But as soon as any transient signal exceeds this working range, the VBUS54DD-HS4 clamps the transient to ground or to the avalanche break down voltage level. t w i n D1+ D15 U S B P o r t R E C E I V E R VBUS 4 6 1 2 3 IC D2+ D2GND 20897-1 TYPICAL CHARACTERISTICS Tamb = 25 °C, unless otherwise specified 120 % 8 µs to 100 % 100 % Rise time = 0.7 ns to 1 ns Discharge Current IESD 100 % 80 % IPPM 60 % 20 µs to 50 % 40 % 20 % 0% 0 10 20548 20 30 40 Time (µs) Fig. 1 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 Rev. 1.5, 04-Jan-2019 80 % 60 % 53 % 40 % 27 % 20 % 0% -10 0 10 20 30 40 50 60 70 80 90 100 20557 Time (ns) Fig. 2 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Document Number: 83384 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54DD-HS4 www.vishay.com Vishay Semiconductors 20 1.0 Measured acc. IEC 61000-4-5 (8/20µs - wave form) f = 1 MHz 0.9 15 0.8 0.7 VC (V) CD (pF) 0.6 0.5 0.4 10 VC 5 Pin 1, 3, 4 or 5 to pin 2 and 6 0.3 0.2 0 Pin 1, 3, 4 or 5 to pin 2 and 6 (one of pin 1, 3, 4 or 5 connected to 3.3 V) 0.1 0 0 1 2 3 4 5 -5 6 0 VR (V) 1 2 3 4 IPP (A) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP 120 100 100 10 Acc. IEC 61000-4-2 + 8 kV contact discharge 80 VC-ESD (V) IF (mA) 1 0.1 Pin 1, 3, 4 or 5 to pin 2 and 6 60 40 20 0.01 0 Pin 2 and 6 to pin 1, 3, 4, or 5 0.001 0.5 0.6 0.7 0.8 0.9 1.0 - 20 - 10 0 10 20 30 40 50 60 70 80 90 1.1 VF (V) t (ns) Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 9 180 8 160 140 7 Pin 1, 3, 4 or 5 to pin 2 and 6 120 VC-ESD (V) VR (V) 6 5 4 3 100 Pin 1, 3, 4 or 5 to pin 2 and 6 80 60 40 2 20 1 0 0.01 Acc. IEC 61000-4-2 - 8 kV contact discharge 0 0.1 1 101 102 103 104 - 20 - 10 0 10 20 30 40 50 60 70 80 90 IR (µA) t (ns) Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) Rev. 1.5, 04-Jan-2019 Document Number: 83384 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54DD-HS4 www.vishay.com Vishay Semiconductors PACKAGE DIMENSIONS in millimeters (inches): LLP1010-6M 0.125 (0.005) ref. 0.5 (0.020) Exp. DAP 0 (0.000) 0.95 (0.037) 1.05 (0.041) Pin 1 marking 0.03 (0.001) 0.2 (0.008) 0.4 (0.016) 0.15 (0.006) 0.1 (0.004) 0.25 (0.010) 0.33 (0.013) 0.35 (0.014) Bsc 0.7 (0.028) Ref. 0.22 (0.009) Exp. DAP 1.05 (0.041) 0.95 (0.037) Foot print recommendation: 0.5 (0.020) 0.05 (0.002) 0.175 (0.007) 0.35 (0.014) 0.7 (0.028) 0.35 (0.014) 0.3 (0.012) Solder resist mask Solder pad Document no.:S8-V-3906.04-004 (4) Created - Date: 17.July.2007 Rev. 5 - Date: 11.May.2016 20899 Rev. 1.5, 04-Jan-2019 0.22 (0.009) Document Number: 83384 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54DD-HS4 www.vishay.com Vishay Semiconductors ORIENTATION IN CARRIER TAPE - LLP1010-xL Unreeling direction LLP1010-xL Pin 1 - Location Top view pad layout - view from top seen at bottom side Document no.: S8-V-3906.04-015 (4) Created - Date: 11.Jun. 2008 Rev. 4 - Date: 28. Jan. 2010 22669 Rev. 1.5, 04-Jan-2019 Document Number: 83384 5 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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