VCNL36687S
www.vishay.com
Vishay Semiconductors
Proximity Sensor With VCSEL in Single Package, I2C Interface
FEATURES
• Package type: surface-mount
• Dimensions (L x W x H in mm): 3.05 x 2 x 1.0
• Integrated modules: vertical cavity surface
emitting laser (VCSEL), proximity sensor (PS),
and signal conditioning IC
• Interrupt function
• Smallest light hole opening design
• Supply voltage range VDD: 1.65 V to 1.95 V
• Communication via I2C interface
DESCRIPTION
VCNL36687S integrates a proximity and a high power
VCSEL (vertical-cavity surface-emitting laser) into one small
package. It incorporates photodiodes, amplifiers, and
analog to digital converting circuits into a single chip by
CMOS process. PS programmable interrupt features of
individual high and low thresholds offers the best utilization
of resource and power saving on the microcontroller. With
just 20 mA pulse current, the VCNL36687S can detect the
Kodak Gray Card in a distance of 20 cm, where other
sensors need 200 mA.
The 12 bits proximity sensing function uses an intelligent
cancellation scheme, so that cross talk is eliminated
effectivitely. To accelerate the PS response time, smart
persistence prevents the misjudgment of proximity sensing
but also allows for a fast response time. Active force mode,
one time trigger by one instruction, is a feature offering more
power saving.
PS functions are easily operated via the simple command
format of I2C (SMBus compatible) interface protocol.
Operating voltage ranges from 1.65 V to 1.95 V.
VCNL36687S is packaged in a lead (Pb)-free 8 pin molding
package, which offers the best market-proven reliability
quality.
• I2C bus H-level range: 1.65 V to 3.6 V
• Floor life: 168 h, MSL 3, according to J-STD-020
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PROXIMITY FUNCTION
• Immunity to red glow (940 nm VCSEL)
• Programmable IVCSEL sink current
• Intelligent cancellation to reduce cross talk phenomenon
• Smart persistence scheme to reduce PS response time
• 12 bits PS output data
• Programmable interrupt function for PS with upper and
lower thresholds
• Adjustable persistence to prevent false triggers for PS
PIN DEFINITION
APPLICATIONS
• Proximity sensor especially for battery operated devices
8
5
1
4
• Mobile devices (e.g. smart phones, tablets) for touch
screen locking, power saving etc.
1
GND
5
2
VPP
6
VCSEL_C
INT
• VR / AR headsets to detect if the headset has been put on
or taken off
3
VDD
7
SDA
4
VCSEL_A
8
SCL
PRODUCT SUMMARY
PART
NUMBER
OPERATING
RANGE
(mm)
OPERATING
VOLTAGE RANGE
(V)
I2C BUS
VOLTAGE RANGE
(V)
VCSEL DRIVING
CURRENT (1)
(mA)
OUTPUT
CODE
ADC RESOLUTION
PROXIMITY /
AMBIENT LIGHT
200
1.65 to 1.95
1.65 to 3.6
20
12 bit, I2C
12 bit / -
VCNL36687S
Note
(1) Base on VCSEL period = 8 ms, 16 ms, 32 ms, and 64 ms
Rev. 1.5, 01-Feb-2022
Document Number: 84907
1
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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ORDERING INFORMATION
ORDERING CODE
PACKAGING
VOLUME (1)
REMARKS
VCNL36687S
Tape and reel
MOQ: 2500 pcs, 2500 pcs/reel
3.05 mm x 2.0 mm x 1.0 mm
Note
(1) MOQ: minimum order quantity
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Supply voltage
TEST CONDITION
VDD
1.65
1.95
V
Operation temperature range
Tamb
-40
+85
°C
Storage temperature range
Tstg
-40
+85
°C
BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
TEST CONDITION
SYMBOL
MIN.
TYP.
MAX.
UNIT
VDD
1.65
1.8
1.95
V
VPP
1.65
1.8
1.95
V
Excluding VCSEL driving
IDD
-
160
-
μA
Light condition = dark;
VDD = 1.8 V, Tamb = 25 °C
IDD (SD)
-
0.5
-
μA
Supply voltage
Supply current
I2C supply voltage
VPULL UP
1.65
1.8
3.6
V
I2C signal input, logic high
VDD = 1.8 V
VIH
1.26
-
-
V
I2C signal input, logic low
VDD = 1.8 V
VIL
-
-
0.73
V
-
-
4095
steps
°C
Full PS counts
12-bit resolution
Operating temperature
Tamb
-40
-
+85
VCSEL driving voltage
(2)
2.68
-
4.8
V
VCSEL driving current
(1)
7
-
20
mA
PS view angle
(3)
-
60
-
°
Notes
(1) Base on VCSEL period = 8 ms, 16 ms, 32 ms, and 64 ms
(2) Base on VCSEL current setting, VCSEL min. voltage need adjust, example as below
(3)
ILD
7 mA
11 mA
14 mA
17 mA
20 mA
VCSEL current setting, VF
2.08 V
2.30 V
2.43 V
2.55 V
2.69 V
VCSEL min. voltage, VLD (VLD = VF + 0.6 V)
2.68 V
2.90 V
3.03 V
3.15 V
3.29 V
Shows total view angle of X-axis (X-axis: +10° to -50°; Y-axis: ± 45°)
8
5
1
4
Rev. 1.5, 01-Feb-2022
Document Number: 84907
2
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL36687S
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Vishay Semiconductors
BLOCK DIAGRAM
VDD
VPP
Pin 3
Anode
Pin 2
Pin 4
PS timing
controller
PS
buffer
DSP
VCSEL
PS
PD
Cathode
Pin 5
Oscillator
INT
SCL
SDA
Current
driver
Pin 6
Pin 8
Pin 7
I2C bus logic
control
Pin 1
Pin 2
(n.c.)
GND
Rev. 1.5, 01-Feb-2022
Document Number: 84907
3
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL36687S
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Vishay Semiconductors
I2C BUS TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
STANDARD MODE
SYMBOL
MIN.
MAX.
f(I2CCLK)
10
t(BUF)
4.7
t(HDSTA)
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
Clock frequency
Bus free time between start and stop condition
Hold time after (repeated) start condition;
after this period, the first clock is generated
FAST MODE
UNIT
MIN.
MAX.
100
10
400
kHz
-
1.3
-
μs
4.0
-
0.6
-
μs
t(SUSTA)
4.7
-
0.6
-
μs
t(SUSTO)
4.0
-
0.6
-
μs
t(HDDAT)
-
3450
-
900
ns
t(SUDAT)
250
-
100
-
ns
I2C clock (SCK) low period
t(LOW)
4.7
-
1.3
-
μs
I2C clock (SCK) high period
t(HIGH)
4.0
-
0.6
-
μs
Clock / data fall time
t(f)
-
300
-
300
ns
Clock / data rise time
t(r)
-
1000
-
300
ns
t(LOW)
I2C BUS
CLOCK
(SCLK)
t(r)
t(f)
VIH
VIL
t(HDSTA)
t(HIGH)
t(SUSTA)
t(SUSTO)
t(BUF)
t(HDDAT)
I2C BUS
DATA
(SDAT)
t(SUDAT)
VIH
VIL
{
P
Stop condition
{
{
S
Start condition
{
S
Start
P
Stop
t(LOSEXT)
SCLKACK
t(LOWMEXT)
SDAACK
t(LOWMEXT)
t(LOWMEXT)
I2C BUS
CLOCK
(SCLK)
I2C BUS
DATA
(SDAT)
Fig. 1 - I2C Bus Timing Diagram
Rev. 1.5, 01-Feb-2022
Document Number: 84907
4
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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PARAMETER TIMING INFORMATION
I2C BUS
CLOCK
(SCLK)
I2C BUS
DATA
(SDAT)
SA7
SA5
SA6
SA4
SA3
W
SA1
SA2
Start by
master
SA7
SA6
SA5
SA4
SA3
SA1
SA2
SA0
ACK by
VCNL36687S
ACK by
VCNL36687S
2
I C bus slave address byte
Command code
I2C BUS
CLOCK
(SCLK)
I2C BUS
DATA
(SDAT)
SA7
SA6
SA4
SA5
SA2
SA3
SA7
SA0
SA1
SA6
SA4
SA5
SA3
SA2
SA1
SA0
Stop by
ACK by
VCNL36687S master
ACK by
VCNL36687S
Data byte low
Data byte high
Fig. 2 - I2C Bus Timing for Sending Word Command Format
I2C BUS
CLOCK
(SCLK)
I2C BUS
DATA
(SDAT)
SA7
SA6
SA5
SA4
SA3
W
SA1
SA2
Start by
master
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ACK by
VCNL36687S
ACK by
VCNL36687S
Command code
2
I C bus slave address byte
I2C BUS
CLOCK
(SCLK)
I2C BUS
DATA
(SDAT)
SA7
SA6
SA5
SA4
SA3
SA2
R
SA1
Start by
master
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ACK by
master
ACK by
VCNL36687S
Data byte low
2
I C bus slave address byte
I2C BUS
CLOCK
(SCLK)
I2C BUS
DATA
(SDAT)
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
NACK by
master
Stop by
master
Data byte high
Fig. 3 - I2C Bus Timing for Receiving Word Command Format
Rev. 1.5, 01-Feb-2022
Document Number: 84907
5
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL36687S
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TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Axis Title
Axis Title
100
100
10000
10000
1000
60
50
40
100
30
20
1000
1st line
2nd line
70
IF - Forward Current (mA)
1st line
80
1st line
2nd line
Relative Response (%)
1st line
90
10
100
10
0
400
500
600
700
800
900
1
10
1000
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Wavelength (nm)
2nd line
VF - Forward Voltage (V)
2nd line
Fig. 4 - Normalized Spectral Response
Fig. 5 - Forward Current vs. Forward Voltage
Axis0°
Title 10°
Axis Title
20°
50°
0.8
100
60°
70°
0.7
1.0
1000
0.8
1st line
2nd line
0.9
2nd line
Ie, rel. - Relative Radiant Intensity
φ - Angular Displacement
2nd line
1000
40°
1.0
10000
1.2
10000
30°
2nd line
Ie, rel. - Relative Radiant Intensity
10
0
0.6
100
0.4
0.2
80°
0
-100 -80 -60 -40 -20
10
0.6
0.4
0.2
0
1st line
10
0
20
40
60
80 100
φ - Angular Displacement (°)
Fig. 6 - VCSEL Profile
VCNL36687S offers a high detection range already with very low pulse current of ≤ 20 mA.
Axis Title
10000
1000
1000
7 mA
14 mA
20 mA
100
1st line
2nd line
Proximity Value (counts)
1st line
10 000
100
10
Media: Kodak Gray Card
8T (8 x 50 μs = 400 μs)
1
0.1
1
10
100
10
1000
Distance to Reflecting Card (mm)
2nd line
Fig. 7 - Proximity Value vs. Distance; PS_IT = 8T
For more information please
(www.vishay.com/doc?84951)
Rev. 1.5, 01-Feb-2022
study
the
application
note
“Designing
the
VCNL36687S
Into
an
Application”
Document Number: 84907
6
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL36687S
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APPLICATION INFORMATION
Pin Connection with the Host
VCNL36687S integrates proximity sensor and VCSEL all together with an I2C interface. It is easy for the baseband (CPU) to
access PS output data via I2C interface without additional software algorithms. The hardware schematic is shown in the
following diagram.
Two additional capacitors in the circuit can be used for the following purposes: (1) the 1 μF capacitor near the VDD pin is used
for power supply noise rejection, (2) the 1 μF capacitor is used to prevent the VCSEL voltage from instantly dropping when the
VCSEL is turned on, and (3) 2.2 kΩ is suitable for the pull up resistor of I2C except for the 10 kΩ applied on the INT pin.
Vpull_up
VDD
VVCSEL
1 μF
2.2 kΩ
2.2 kΩ
SCL
1 μF
2
3
VDD
8
VPP
SCL
7
SDA
SDA
Anode
10 kΩ
4
VCNL36687S
Baseband
6
GPIO
Cathode 5
INT
GND
1
Fig. 8 - Hardware Pin Connection Diagram
Digital Interface
VCNL36687S applies single slave address 0x60 (HEX) of 7-bit addressing following I2C protocol. All operations can be
controlled by the command register. The simple command structure helps users easily program the operation setting and latch
the light data from VCNL36687S. As Fig. 9 shows, VCNL36687S’s I2C command format is simple for read and write operations
between VCNL36687S and the host. The white sections indicate host activity and the gray sections indicate VCNL36687S’s
acknowledgement of the host access activity. Write word and read word protocol is suitable for accessing registers particularly
for 12-bit PS data. Interrupt can be cleared by reading data out from register: INT_Flag. All command codes should follow read
word and write word protocols.
Send word → write command to VCNL36687S
1
7
1
1
8
1
8
1
8
1
1
S
Slave address
Wr
A
Command code
A
Data byte low
A
Data byte high
A
P
Receive word → read data from VCNL36687S
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
Slave address
Wr
A
Command code
A
S
Slave address
Rd
A
Data byte low
A
Data byte high
N
P
S = start condition
P = stop condition
A = acknowledge
N = not acknowledge
Host action
VCNL36687S response
Fig. 9 - Write Word and Read Word Protocol
Rev. 1.5, 01-Feb-2022
Document Number: 84907
7
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL36687S
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Vishay Semiconductors
Function Description
For proximity sensor function, VCNL36687S supports different kinds of mechanical designs to achieve the best proximity
detection performance for any color of object with more flexibility. The basic PS function settings, such as period, persistence,
INT, and shut down are handled by the register: PS_CONF1. Period controls the PS response time. Integration time represents
the duration of the energy being received. The Interrupt is asserted when the PS detection levels over the high threshold level
setting (register: PS_THDH) or lower than low threshold (register: PS_THDL). If the Interrupt function is enabled, the host reads
the PS output data from VCNL36687S that saves host loading from periodically reading PS data. More than that, INT flag
(register: INT_Flag) indicates the behavior of INT triggered under different conditions. PS persistence (PS_PERS) sets up the PS
INT asserted conditions as long as the PS output value continually exceeds the threshold level. The intelligent cancellation level
can be set on register: PS_CANC to reduce the cross talk phenomenon.
VCNL36687S also supports easy use of proximity detection logic output mode that outputs just high / low levels saving loading
from the host. Normal operation mode or proximity detection logic output mode can be selected on the register: PS_MS.
A smart persistence is provided to get faster PS response time and prevent false trigger for PS. Descriptions of each slave
address operation are shown in Table 1.
TABLE 1 - COMMAND CODE AND REGISTER DESCRIPTION
COMMAND DATE BYTE
CODE
LOW / HIGH
L
0x03
H
L
0x04
H
L
0x05
H
L
0x06
H
L
0x07
H
L
0x08
H
L
0xF2
H
L
0xF3
H
L
0xF4
H
REGISTER
NAME
PS_CONF1
PS_CONF2
PS_CONF3
PS_CONF4
PS_THDL_L
PS_THDL_M
PS_THDH_L
PS_THDH_M
PS_CANC_L
PS_CANC_M
PS_CONF5
Reserved
PS_Data_L
PS_Data_M
Reserved
INT_Flag
ID_L
ID_M
R / W DEFAULT
VALUE
R/W
0x01
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R
0x00
R
0x00
R
0x00
R
0x00
R
0x88
R
0x05
FUNCTION DESCRIPTION
PS period, persistence, INT and smart persistence and function selection
PS IT and start selection
PS active force mode
PS VCSEL current selection
PS low interrupt threshold setting LSB byte
PS low interrupt threshold setting MSB byte
PS high interrupt threshold setting LSB byte
PS high interrupt threshold setting MSB byte
PS cancellation level setting
PS cancellation level setting
PS power on start setting
Reserved
PS LSB output data
PS MSB output data
Reserved
PS interrupt flags
Device ID LSB
Device ID MSB
Note
• All of reserved register are used for internal test. Please keep as default setting
Rev. 1.5, 01-Feb-2022
Document Number: 84907
8
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL36687S
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Command Register Format
VCNL36687S provides an 8-bit command register for PS controlling independently. The description of each command format
is shown in the following tables.
TABLE 2 - REGISTER: PS_CONF1 DESCRIPTION
REGISTER NAME
Command
COMMAND CODE: 0x03_L (0x00 DATA BYTE LOW)
Bit
Description
PS_Period
7:6
(0 : 0) = 8 ms, (0 : 1) = 16 ms, (1 : 0) = 32 ms, (1 : 1) = 64 ms
PS sample period setting
PS_PERS
5:4
(0 : 0) = 1, (0 : 1) = 2, (1 : 0) = 3, (1 : 1) = 4
PS interrupt persistence setting
PS_ INT
3:2
(0 : 0) = interrupt disable, (0 : 1) = interrupt disable, (1 : 0) = interrupt enable,
(1 : 1) = trigger by logic high / low mode
PS_SMART_PERS
1
0 = disable ; 1 = enable PS smart persistence
PS_SD
0
0 = PS power on, 1 = PS shut down, default = 1
TABLE 3 - REGISTER: PS_CONF2 DESCRIPTION
COMMAND CODE: 0x03_H (0x03 DATA BYTE HIGH)
Command
Bit
Description
PS_IT
7:6
( 0 : 0 ) = 1T, (0 : 1) = 2T, (1 : 0) = 4T, (1 : 1) = 8T
PS_MPS
5:4
(0 : 0 ) = 1, (0 : 1) = 2, (1 : 0) = 4, (1 : 1) = 8;
PS multi-pulse setting
PS_ITB
Reserved
3
2:0
0 = 25 μs, 1 = 50 μs, PS IT bank setting
Default = 0
TABLE 4 - REGISTER: PS_CONF3 DESCRIPTION
COMMAND CODE: 0x04_L (0x04 DATA BYTE LOW)
Register
Bit
Reserved
7
PS_AF
6
0 = auto mode; 1 = force mode
5
0 = no PS active force mode trigger, 1 = trigger one time cycle
VCNL36687S output one cycle data every time host writes in “1” to sensor. The state returns to “0”
automatically.
PS_FOR_Trig
Reserved
4
Reserved
3:0
Description
0
0
(0 : 0 : 0 : 0)
TABLE 5 - REGISTER: PS_CONF4 DESCRIPTION
COMMAND CODE: 0x04_H (0x04 DATA BYTE HIGH)
Register
PS_SC_EN
PS_SC_CUR
Bit
7
6:5
Description
0 = turn off sunlight cancel; 1 = turn on sunlight cancel; PS sunlight cancel function enable setting
(0 : 0) = 1 x typical sunlight cancel current, (0 : 1) = 2 x typical sunlight cancel current, (1 : 0) = 4 x typical
sunlight cancel current, (1 : 1) = 8 x typical sunlight cancel current
PS_HD
4
0 = PS output is 12 bits, 1 = PS output is 16 bits
Reserved
3
0
VCSEL_I
2:0
Rev. 1.5, 01-Feb-2022
(0 : 0 : 0) = 7 mA; (0 : 0 : 1) = 11 mA; (0 : 1 : 0) = 14 mA; (0 : 1 : 1) = 17 mA; (1 : 0 : 0) = 20 mA;
VCSEL current selection setting
Document Number: 84907
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TABLE 6 - REGISTER: PS_THDL_L AND PS_THDL_M DESCRIPTION
COMMAND CODE: 0x05_L (0x05 DATA BYTE LOW) AND 0x05_H (0x05 DATA BYTE HIGH)
Command
Bit
Description
PS_THDL_L
7:0
0x00 to 0xFF, PS interrupt low threshold setting_LSB byte
PS_THDL_M
7:0
0x00 to 0x0F, PS interrupt low threshold setting_MSB byte
TABLE 7 - REGISTER: PS_THDL_L AND PS_THDL_M DESCRIPTION
COMMAND CODE: 0x06_L (0x06 DATA BYTE LOW) AND 0x06_H (0x06 DATA BYTE HIGH)
Command
Bit
Description
PS_THDH_L
7:0
0x00 to 0xFF, PS interrupt high threshold setting_LSB byte
PS_THDH_M
7:0
0x00 to 0x0F, PS interrupt high threshold setting_MSB byte
TABLE 8 - REGISTER: PS_CANC_L AND PS_CANC_M DESCRIPTION
COMMAND CODE: 0x07_L (0x07 DATA BYTE LOW) AND 0x07_H (0x07 DATA BYTE HIGH)
Command
Bit
Description
PS_CANC_L
7:0
0x00 to 0xFF, PS cancellation level setting_LSB byte
PS_CANC_M
7:0
0x00 to 0x0F, PS MSB cancellation level setting_MSB byte
TABLE 9 - REGISTER: PS_CONF5 DESCRIPTION
COMMAND CODE: 0x08_L (0x08 DATA BYTE LOW) AND 0x08_H (0x08 DATA BYTE HIGH)
Register
Reserved _L
POR_S
Reserved_M
Bit
7:1
0
7:0
Description
Reserved
When use PS function, must write “1”
Reserved
TABLE 10 - READ OUT REGISTER DESCRIPTION
Register
PS_Data_L
Command Code
0xF2_L (0xF2 data byte low)
Bit
Description
7:0
0x00 to 0xFF, PS LSB output data
PS_Data_M
0xF2_H (0xF2 data byte high)
7:0
3 : 0 PS output code
6 : 4 reserved
7 : “0” Normal output, “1” enter sunlight protection mode
PS_Data_L= 00000000
PS_Data_M= 1000000
Reserved
0xF3_L (0xF3 data byte low)
7:0
Default = 0x00
INT_Flag
0xF3_H (0xF3 data byte high)
7
6
5
4
3
2
1
0
ID_L
0xF4_L (F4H data byte low)
7:0
88H for MP version sample
Device ID LSB byte
ID_M
0xF4_H (F4H data byte high)
7:6
5:4
3:0
(0 : 0)
(0 : 0) slave address = 0x60
Version code (0 : 1 : 0 : 1); device ID MSB byte
Reserved
Reserved
Reserved
PS_SPFLAG, PS entering protection mode
Reserved
Reserved
PS_IF_CLOSE, PS rises above PS_THDH INT trigger event
PS_IF_AWAY, PS drops below PS_THDL INT trigger event
Initialization
VCNL36687S includes default values for each register. As long as power is on, it is ready to be controlled by host via I2C bus.
Rev. 1.5, 01-Feb-2022
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Threshold Window Setting
• Programmable PS Threshold
VCNL36687S provides both high and low thresholds 12-bit data setting for PS (register: PS_THDL, PS_THDH).
• PS Persistence
The PS persistence function (PS_PERS, 1\2\3\4) helps to avoid false trigger of the PS INT. For example, if PS_PERS = 3 times,
the PS INT will not be asserted unless the PS value is greater than the PS threshold (PS_THDH) value for three periods of time
continuously
• PS Active Force Mode
An extreme power saving way to use PS is to apply PS active force (register: PS_CONF3 command: PS_AF = 1) mode.
Anytime host would like to read out just one of PS data, write in “1” at register: PS_CONF3 command: PS_FOR_Trig.
Without commands placed, there is no PS data output. VCNL36687S stays in standby mode constantly
• PS Detection Object
Any color of object is detectable by VCNL36687S
Data Access
For PS data reading, it has to apply two bytes. One byte is for LSB, and the other byte is for MSB (4 bits) as shown in Table 11.
TABLE 11 - VCNL36687S 12-BIT PS DATA FORMAT
VCNL36687S
Bit
15
Register
14
13
12
11
Bit 15: “0” normal operation,
“1” enter sunlight protection
mode, PS output =
1000000000000000(32768)
10
9
PS_DataM
8
7
6
5
4
3
2
1
0
PS_DataL
Intelligent Cancellation
VCNL36687S provides an intelligent cancellation method to reduce cross talk for the proximity sensor. The output data will be
subtracted by the input value stored in register: PS_CANC.
Interruption (INT)
VCNL36687S has PS interrupt feature operated by a single pin “INT”. The purpose of the interrupt feature is to actively inform
the host once INT has been asserted. With the interrupt function applied, the host does not need to be constantly pulling data
from the sensor, but to read data from the sensor while receiving interrupt request from the sensor.
Interruption Flag
Register: INT_Flag represents all of interrupt trigger status for PS. Any flag value changes from “0” to “1” state, the level of INT
pin will be pulles low. As long as host reads INT_Flag data, the bit will change from “1” state to “0” state after reading out, the
INT level will be returned to high afterwards.
PROXIMITY DETECTION LOGIC OUTPUT MODE
VCNL36687S provides a proximity detection logic output mode that uses INT pin (pin 6) as a proximity detection logic high /
low output (register: PS_INT = 3). When this mode is selected, the PS output (pin 6; INT/POUT) is pulled low when an object is
closing to be detected and returned to level high when the object moves away. Register: PS_THDH\L defines how sensitive PS
detection is.
PROXIMITY DETECTION HYSTERESIS
A PS detection hysteresis is important that keeps PS state in a certain range of detection distance. For example, PS INT
asserts when PS value over PS_THDH. Host switches off panel backlight and then clears INT. When PS value is less than
PS_THDL, Host switches on panel backlight. Any PS value lower than PS_THDH or higher than PS_THDL, PS INT will not be
asserted. Host does keep the same state.
Rev. 1.5, 01-Feb-2022
Document Number: 84907
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PACKAGE INFORMATION
Side View
Bottom View
2 ± 0.1
1 ± 0.05
0.85
5
1
8
SENSOR
0.775
0.775
0.575 (8x)
0.6
1.23
1.34
3.05 ± 0.1
VCSEL
4
0.775
0.4
Top View
Ø 0.94
1
0.5
1
GND
5
VCSEL_C
2
VPP
6
INT
3
VDD
7
SDA
4
VCSEL_A
8
SCL
Fig. 10 - VCNL36687S Package Dimensions
LAYOUT PAD INFORMATION
Pad Center to Center
1.350
0.775
0.625 (8 x)
0.750
0.775
PAD Center to Center
0.775
0.3
0.6
Fig. 11 - VCNL36687S PCB Layout Footprint
Rev. 1.5, 01-Feb-2022
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APPLICATION CIRCUIT BLOCK REFERENCE
Vpull_up
VDD
VVCSEL
1 μF
2.2 kΩ
2.2 kΩ
VDD
SCL
1 μF
2
3
8
VPP
SCL
7
SDA
SDA
Anode
10 kΩ
4
VCNL36687S
Baseband
GPIO
6
Cathode 5
INT
GND
1
Fig. 12 - VCNL36687S Application Circuit (normal operation with interrupt function)
RECOMMENDED STORAGE AND REBAKING CONDITIONS
PARAMETER
MIN.
MAX.
UNIT
Storage temperature
5
50
°C
Relative humidity
-
60
%
Open time
-
168
h
From the date code on the aluminized envelope (unopened)
-
12
months
Tape and reel: 60 °C
-
22
h
Tube: 60 °C
-
22
h
Total time
Rebaking
Rev. 1.5, 01-Feb-2022
CONDITIONS
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RECOMMENDED INFRARED REFLOW
Soldering conditions which are based on J-STD-020 C
IR REFLOW PROFILE CONDITION
PARAMETER
CONDITIONS
Peak temperature
TEMPERATURE
TIME
260 °C + 5 °C / - 5 °C (max.: 265 °C)
10 s
150 °C to 200 °C
60 s to 180 s
Preheat temperature range and timing
Timing within 5 °C to peak temperature
Timing maintained above temperature / time
Timing from 25 °C to peak temperature
-
10 s to 30 s
217 °C
60 s to 150 s
-
8 min (max.)
Ramp-up rate
3 °C/s (max.)
-
Ramp-down rate
6 °C/s (max.)
-
Temperature (°C)
Recommend Normal Solder Reflow is 235 °C to 265 °C
Max. Temperature
260 °C + 5 °C / - 5 °C/10 s
260
200
150
Ramp-Down Rate
6 °C/s (max.)
Ramp-Up Rate
3 °C/s (max.)
217
Soldering Zone
60 s to 150 s
Ramp-Up Rate
3 °C/s (max.)
Pre-Heating Time
t2 - t1 = 60 s to 180 s
t2
t1
Time (s)
Fig. 13 - VCNL36687S Solder Reflow Profile Chart
RECOMMENDED IRON TIP SOLDERING CONDITION AND WARNING HANDLING
1. Solder the device with the following conditions:
1.1. Soldering temperature: 400 °C (max.)
1.2. Soldering time: 3 s (max.)
2. If the temperature of the method portion rises in addition to the residual stress between the leads, the possibility that an
open or short circuit occurs due to the deformation or destruction of the resin increases
3. The following methods: VPS and wave soldering, have not been suggested for the component assembly
4. Cleaning method conditions:
4.1. Solvent: methyl alcohol, ethyl alcohol, isopropyl alcohol
4.2. Solvent temperature < 45 °C (max.)
4.3. Time: 3 min (min.)
Rev. 1.5, 01-Feb-2022
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TAPE PACKAGING INFORMATION in millimeters
Rev. 1.5, 01-Feb-2022
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Legal Disclaimer Notice
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Revision: 01-Jan-2023
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Document Number: 91000