VCUT05D1-SD0-G4-08

VCUT05D1-SD0 www.vishay.com Vishay Semiconductors Bidirectional Symmetrical (BiSy) Single Line ESD-Protection Diode in Silicon Package FEATURES • Ultra compact CLP0603 package • Low package height < 0.3 mm 0.27 • 1-line ESD-protection • Working range ± 5.5 V • Low leakage current < 0.1 μA 22543 • Low load capacitance CD < 14 pF 0.6 0.3 • ESD-protection acc. IEC 61000-4-2 ± 30 kV contact discharge ± 30 kV air discharge 22544 • Lead plating: Au (e4) MARKING (example only) 1 • Lead material: TiNiAg XY • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 22454    1 = Year code Open circle = Month code and pin 1 XY = Type code ORDERING INFORMATION DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VCUT05D1-SD0 VCUT05D1-SD0-G4-08 15 000 15 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VCUT05D1-SD0 CLP0603 5D 0.12 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals Reflow soldering according JEDEC STD-020 ABSOLUTE MAXIMUM RATINGS VCUT05D1-SD0 PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current acc. IEC 61000-4-5, 8/20 μs/single shot IPPM 6 A Peak pulse power Pin 1 to pin 2 acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 78 W ESD immunity Operating temperature Storage temperature Rev. 1.3, 19-Nov-13 Contact discharge acc. IEC61000-4-2; 10 pulses Air discharge acc. IEC61000-4-2; 10 pulses Junction temperature VESD ± 30 ± 30 kV TJ -55 to +150 °C Tstg -55 to +150 °C Document Number: 83443 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com Vishay Semiconductors CUT THE SPIKES WITH VCUT05D1-SD0 The VCUT05D1-SD0 is a Bidirectional and Symmetrical (BiSy) ESD-protection device which clamps positive and negative overvoltage transients to ground. Connected between the signal or data line and the ground the VCUT05D1-SD0 offers a high isolation (low leakage current, low capacitance) within the specified working range. Due to the short leads and small package size of the tiny CLP0603 package the line inductance is very low, so that fast transients like and ESD-strike can be clamped with minimal over- or undershoots. ELECTRICAL CHARACTERISTICS VCUT05D1-SD0  (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 1 lines Max. reverse working voltage VRWM - - 5.5 V Reverse voltage at IR = 0.1 μA VR 5.5 - - V Reverse current at VRWM = 5.5 V IR - - 0.1 μA at IR = 1 mA VBR 6.5 8 9 V at IPP = 1 A VC - 8.8 10 V at IPP = IPPM = 6 A VC - 11 13 V at VR = 0 V; f = 1 MHz CD - 13 14 pF Protection paths Reverse stand-off voltage Reverse breakdown voltage Reverse clamping voltage Capacitance at VR = 2.5 V; f = 1 MHz CD - 11 - pF Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns ITLP = 8 A VC-TLP - 9.8 - V Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns ITLP = 16 A VC-TLP - 11 - V Dynamic resistance Transmission Line Pulse (TLP); tp = 100 ns RDYN - 0.15 -  TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 120 % Rise time = 0.7 ns to 1 ns 8 µs to 100 % 100 % 80 % 80 % 60 % IPPM Discharge Current IESD 100 % 60 % 53 % 20 µs to 50 % 40 % 40 % 27 % 20 % 20 % 0% - 10 0 10 20 30 40 50 60 70 80 90 100 20557 Time (ns) Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Rev. 1.3, 19-Nov-13 0% 0 20548 10 20 30 40 Time (µs) Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 Document Number: 83443 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com 20 Vishay Semiconductors 10 f = 1 MHz Ta = 25 °C Ta = +150 °C 18 0 16 -5 12 VC-ESD (V) CD (pF) 14 10 8 6 - 15 - 20 - 25 4 - 35 2 - 40 0 1 2 3 4 5 - 45 - 10 0 6 VR (V) 22695 40 9 35 8 30 VC-ESD (V) 5 Acc. IEC 61000-4-2 + 8 kV contact discharge 25 Ta = -50 °C Ta = 25 °C Ta = 150 °C 6 t (ns) Fig. 6 - Typical Clamping Performance at 8 kV Contact Discharge acc. IEC 61000-4-2 10 7 10 20 30 40 50 60 70 80 90 22569 Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR VR in V - 10 - 30 0 4 20 15 10 3 5 2 0 1 -5 0 0.01 0.1 1 10 100 1000 10 000 100 000 IR in µA 22696 14 - 10 - 10 0 t (ns) Fig. 7 - Typical Clamping Performance at 8 kV Contact Discharge acc. IEC 61000-4-2 60 Ta = at 25 °C Ta = at 150 °C 12 10 20 30 40 50 60 70 80 90 22570 Fig. 4 - Typical Reverse Voltage VR vs. Reverse Current IR 10 8 6 ITLP in A VC in (V) Acc. IEC 61000-4-2 - 8 kV contact discharge 5 VC Pin 1-2 or Pin 2-1 Transmission Line Pulse (TLP) tp = 100 ns 50 (Average between 55 ns and 95 ns) 40 V C-TLP = 0.15 Ω x ITLP + 8.6 V (RDYN = 0.15 Ω) 30 20 4 10 2 Measured acc. to IEC 61000-4-5 (8/20 μs - wave form) 0 0 22697 1 2 3 4 5 6 0 IPP in (A) Fig. 5 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Rev. 1.3, 19-Nov-13 0 7 22731 5 10 15 20 VC-TLP in V Fig. 8 - Typical Clamping Voltage at 100 ns Transmission Line Pulse (TLP) Document Number: 83443 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com Vishay Semiconductors PACKAGE DIMENSIONS in millimeters (mils): CLP0603-2L Package = Chip dimensions in mm e1 b L D A A1 e Millimeters nom. max. min. nom. max. 0.24 0.27 0.30 9.44 10.63 11.81 b 0.22 0.25 0.28 8.66 9.84 11.02 D 0.27 0.30 0.33 10.62 11.81 12.99 E 0.57 0.60 0.63 22.44 23.62 24.80 A E mils min. A1 0.02 e 0.79 0.40 e1 15.75 0.25 L 0.12 0.15 9.84 0.18 4.72 5.91 7.09 foot print recommendation: Soldering mask opening 0.05 0.75 0.3 0.05 solder pad 0.28 0.28 22606 2 terminal leadless package (CLP0603-2L) Document no.: S8-V-3906.04-023 (4) Created - Date: 22. Nov. 2010 Rev.3 - Date: 14. Sept. 2011 Rev. 1.3, 19-Nov-13 Document Number: 83443 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com Vishay Semiconductors CARRIER TAPE in millimeters: CLP0603 A-A 0.67±0.03 max . 2° Ø 0.2 ± 0.05 0.2 ± 0.02 + 0.3 3.5 ± 0.05 4 ± 0.1 8 - 0.1 A Ø 1.55 ± 0.05 Section 1.75 ± 0.1 2 ± 0.05 B B A B-B 0.33 ± 0.03 Section 5° 0.37± 0.03 Cummulative tolerances of 10 sprocket holes is +/-0.2mm 22591 Document no. S8-V-3906.04-0025 (4) Created - Date: 22. Nov. 2010 ORIENTATION IN CARRIER CLP0603 Unreeling direction DETAIL A 50:1 Pin 1 A CLP0603 Top view 22607 Orientation in Carrier Tape (CLP0603) S8-V-3906.04-026 (4) 22.10.2010 Rev. 1.3, 19-Nov-13 Document Number: 83443 5 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com Vishay Semiconductors APPLICATION NOTE 1. PCB FOOTPRINT DESIGN Verified by internal tests, Vishay recommends the soldering pad and solder mask opening design as shown in fig. 1. We recommend using a non-solder mask defined (NSMD) design, as shown below. The reason is that with a NSMD design, the size of the actual solder pad is more accurate (tolerances for copper etchings are smaller compared to a solder mask defined process). 0.3 0.55 0.3 0.05 0.75 0.05 0.2 0.28 0.28 soldering mask opening solder pad Fig. 1 - Recommended Soldering Pad Design 2. PCB SOLDERING PAD METALLIZATION There are several common pad metallization/finishes, including OSP (Organic Solderability Protectant), HASL (Hot Air Solder Level), and ENiAu. Because of the CLP0603’s extremely small size, Vishay only recommends using the electroless Ni/immersion gold over copper pad plating. 3. SCREEN PRINT PROCESS The solder paste is applied to the PCB by using a screen print process. The recommended stencil thickness for the CLP0603 package is 80 μm (the absolute maximum is 100 μm). The recommended dimensions for the stencil openings are 12 mil (300 μm) by 8 mil (200 μm) for both pads. The side wall of the stencil openings should be tapered approximately 5 degrees. An electro-polished finish will support a better release of the paste.     Rev. 1.3, 19-Nov-13 Fig. 2 - Maximum Stencil Openings for a Stencil Thickness of 80 μm Note • A wider stencil opening will result in a better solder paste release from the stencil. So the best quality can be obtained by using the optimum between the stencil quality, thickness, and opening.  If a tilting of the package is observed, the amount of solder paste should be reduced slightly. Please also take into consideration the direct relation between the amount of solder paste and the package shear strength. 4. SOLDER PASTE TYPE Type 4 solder pastes (or smaller powder sizes) are recommended. In our evaluation we used the Cookson Electronics’ Alpha OM-338 CSP (96.5 % Sn/3 % Ag/0.5 % Cu) solder paste. 5. REFLOW SOLDERING PROCESS A standard surface-mount reflow soldering process can be used (reference: JPC/JEDEC J-STD-020D). However, for an optimum process, recommendations from the solder paste supplier should be considered. Variations in chemistry and viscosity of the fluxer may require small adjustments to the soldering profile.              Document Number: 83443 6 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com Vishay Semiconductors Supplier TP ≥ TC User TP ≤ TC TC TC - 5 °C Supplier tP User tP TP tp Max. Ramp Up Rate = 3 °C/s Max. Ramp Down Rate = 6 °C/s TL Temperature TSmax. TC - 5 °C tL Preheat Area TSmin. tS 25 Time 25 °C to Peak Time TABLE 1 - CLASSIFICATION REFLOW PROFILES PROFILE FEATURE SnPb EUTECTIC ASSEMBLY LEAD (Pb)-FREE ASSEMBLY 150 °C PREHEAT AND SOAK Temperature min. (TSmin.) 100 °C Temperature max. (TSmax.) 150 °C 200 °C Time (TSmin. to TSmax.) (tS) 60 s to 120 s 60 s to 120 s Average ramp-up rate (TSmax. to Tp) Liquidous temperature (TL) Time to liquidous (tL) Peak package temperature (Tp) (1) Time (tp) (2) with 5 °C of the specified classification temperature (TC) 3 °C/s maximum 183 °C 217 °C 60 s to 150 s 60 s to 150 s See classification temperature in table 3 See classification temperature in table 4 20 s (2) Average ramp-down rate (Tp to TSmax.) Time 25 °C to peak temperature 30 s (2) 6 °C/s maximum 6 min maximum 8 min maximum Notes (1) Tolerance for peak profile temperature (T ) is defined as a supplier minimum and user maximum p (2) Tolerance for time at peak profile temperature (T ) is defined as a supplier minimum and user maximum p Notes 1. All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g. live-bug). If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e. dead-bug). Tp shall be within ± 2 °C of the live-bug Tp and still meet the TC requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body temperatures refer to JEP140 for the recommended thermocouple use. 2. Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly profiles should be developed based on specific process needs and board designs and should not exceed the parameters in table 1. For example, if TC is 260 °C and time tp is 30 s, this means the following for the supplier and the user: - For a supplier: The peak temperature must be at least 260 °C. The time above 255 °C must be at least 30 s. - For a user: The peak temperature must not exceed 260 °C. The time above 255 °C must not exceed 30 s. 3. All components in the test load shall meet the classification profile requirements. 4. SMD packages classified to a given moisture sensitivity level by using procedures or criteria defined within any previous version of J-STD-020, JESD22-A112 (rescinded), IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in classification level or a higher peak classification temperature is desired. Rev. 1.3, 19-Nov-13 Document Number: 83443 7 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT05D1-SD0 www.vishay.com Vishay Semiconductors TABLE 2 - SnPb EUTECTIC PROCESS - CLASSIFICATION TEMPERATURES (TC) VOLUME mm3 < 350 VOLUME mm3  350 < 2.5 mm 235 °C 220 °C  2.5 mm 220 °C 220 °C PACKAGE THICKNESS TABLE 3 - LEAD (Pb)-FREE PROCESS - CLASSIFICATION TEMPERATURES (TC) VOLUME mm3 < 350 PACKAGE THICKNESS VOLUME mm3 350 to 2000 VOLUME mm3 > 2000 < 1.6 mm 260 °C 260 °C 260 °C 1.6 mm to 2.5 mm 260 °C 250 °C 245 °C > 2.5 mm 250 °C 245 °C 245 °C Notes 5. At the direction of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the values specified in tables 2 and 3. The use of a higher Tp does not change the classification temperature (TC). 6. Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks. 7. The maximum component temperature reached during reflow depends on package thickness and volume. The use on convection reflow processes reduces the thermal gradients between packages. However thermal gradients due to differences in thermal mass of SMD packages may still exist. 8. Moisture sensitivity levels of components intended for use in a lead (Pb)-free assembly process shall be evaluated using the lead (Pb)-free classification temperatures and profiles defined in table 1 and 3, whether or not lead (Pb)-free. 9. SMD packages classified to a given moisture sensitivity level by using procedures or criteria defined within any previous version of J-STD-020, JESD22-A112 (rescinded), IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in classification level or a higher peak classification temperature is desired. 6. SOLDERING QUALITY INISPECTION An X-ray inspection system is required to find defects such as shorts between pads, open contacts, and voids within the solder. In addition, a visual inspection by microscope or camera (of appropriate magnification) can be used to inspect the sides of the solder joints for acceptable shape and molten solder. 7. SHEAR TEST COMPARISON The data below shows a comparison of shear strength after a reflow soldering process. Typical shear strength VISHAY COMPETITOR 1 COMPETITOR 2 COMPETITOR 3 500 g 350 g 600 g 440 g 8. REWORK PROCEDURE For rework, the CLP0603 package must be removed from the PCB if there is any issue with the solder joints. Standard SMT rework systems are recommended for this. Due to the small size of the package, the rework system should be equipped with a proper magnification aid. Rev. 1.3, 19-Nov-13 9. INTERCHANGEABILITY OF THE CLP WITH A PLASTIC PACKAGE OF THE SAME SIZE Based on our studies, the CLP is 100 % compatible with plastic packages of the same size. Document Number: 83443 8 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000