SI1441EDH

New Product Si1441EDH Vishay Siliconix P-Channel 20 V (D-S) MOSFET PRODUCT SUMMARY VDS (V) - 20 RDS(on) () 0.041 at VGS = - 4.5 V 0.054 at VGS = - 2.5 V 0.100 at VGS = - 1.8 V ID (A)a -4 -4 -4 12.5 nC Qg (Typ.) FEATURES • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • Typical ESD Performance 1500 V • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC SOT-363 SC-70 (6-LEADS) D 1 6 D APPLICATIONS • Load Switch for Portable Devices - Cellular Phone - DSC - Portable Game Console - MP3 - GPS Marking Code G R S D 2 5 D G 3 4 S Part # code BQX XXX Lot Traceability and Date code D Top View Ordering Information: Si1441EDH-T1-GE3 (Lead (Pb)-free and Halogen-free) P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage TC = 25 °C Continuous Drain Current (TJ = 150 °C) TC = 70 °C TA = 25 °C TA = 70 °C Pulsed Drain Current (t = 300 µs) Continuous Source-Drain Diode Current TC = 25 °C TA = 25 °C TC = 25 °C Maximum Power Dissipation TC = 70 °C TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) TJ, Tstg PD IDM IS ID Symbol VDS VGS Limit - 20 ± 10 - 4a -4 - 4a, b, c - 4a, b, c - 25 - 2.3 - 1.3b, c 2.8 1.8 1.6b, c 1.0b, c - 55 to 150 260 °C W A Unit V THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambientb, d Maximum Junction-to-Foot (Drain) Notes: a. Package limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 125 °C/W. Document Number: 66823 S10-1827-Rev. A, 09-Aug-10 www.vishay.com 1 t5s Steady State Symbol RthJA RthJF Typical 60 34 Maximum 80 45 Unit °C/W New Product Si1441EDH Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulse Diode Forward Current Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Reverse Recovery Fall Time Reverse Recovery Rise Time IS ISM VSD trr Qrr ta tb IF = - 4 A, dI/dt = 100 A/µs, TJ = 25 °C IS = - 4 A, VGS = 0 V - 0.85 18 8 18 10 TC = 25 °C - 2.3 - 25 - 1.2 36 16 A V ns nC ns Qg Qgs Qgd Rg td(on) tr td(off) tf td(on) tr td(off) tf VDD = - 10 V, RL = 1.4  ID  - 4 A, VGEN = - 10 V, Rg = 1  VDD = - 10 V, RL = 1.4  ID  - 4 A, VGEN = - 4.5 V, Rg = 1  f = 1 MHz 0.08 VDS = - 10 V, VGS = - 8 V, ID = - 5 A VDS = - 10 V, VGS = - 4.5 V, ID = - 5 A 22 12.5 1.8 3.3 0.43 150 300 1620 560 50 90 2500 600 0.86 225 450 2430 840 100 180 3750 900 ns k 33 19 nC VDS VDS/TJ VGS(th)/TJ VGS(th) IGSS IDSS ID(on) RDS(on) gfs VGS = 0 V, ID = - 250 µA ID = - 250 µA VDS = VGS, ID = - 250 µA VDS = 0 V, VGS = ± 10 V VDS = 0 V, VGS = ± 4.5 V VDS = - 20 V, VGS = 0 V VDS = - 20 V, VGS = 0 V, TJ = 55 °C VDS - 5 V, VGS = - 10 V VGS = - 4.5 V, ID = - 5 A VGS = - 2.5 V, ID = - 4.4 A VGS = - 1.8 V, ID = - 1 A VDS = - 10 V, ID = - 5 A - 15 0.034 0.045 0.067 16 0.041 0.054 0.100 S  - 0.4 - 20 - 11 2.6 -1 ±8 ±1 -1 - 10 A µA V mV/°C V Symbol Test Conditions Min. Typ. Max. Unit Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 66823 S10-1827-Rev. A, 09-Aug-10 New Product Si1441EDH Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.1 10-4 0.08 IGSS - Gate Current (mA) IGSS - Gate Current (A) 10-5 TJ = 150 °C 10-6 0.06 10-7 TJ = 25 °C 0.04 10-8 0.02 10-9 0 0 3 6 9 12 15 10-10 0 3 6 9 12 15 VGS - Gate-Source Voltage (V) VGS - Gate-Source Voltage (V) Gate Current vs. Gate-Source Voltage 25 V GS = 5 V thru 3 V V GS = 2.5 V 20 ID - Drain Current (A) ID - Drain Current (A) Gate Current vs. Gate-Source Voltage 5 4 15 V GS = 2 V 10 3 T C = 25 °C 2 T C = 125 °C 1 T C = - 55 °C 5 V GS = 1.5 V 0 0 0.5 1.0 1.5 2.0 2.5 0 0 0.5 1.0 1.5 2.0 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics 0.10 V GS = 1.8 V 8 Transfer Characteristics ID = 5 A RDS(on) - On-Resistance (Ω) 0.08 V GS = 2.5 V 0.06 V GS = 4.5 V 0.04 VGS - Gate-to-Source Voltage (V) 6 V DS = 5 V V DS = 10 V 4 V DS = 16 V 2 0.02 0 0 5 10 15 20 25 0 0 5 10 15 20 25 ID - Drain Current (A) Qg - Total Gate Charge (nC) On-Resistance vs. Drain Current Gate Charge Document Number: 66823 S10-1827-Rev. A, 09-Aug-10 www.vishay.com 3 New Product Si1441EDH Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.5 V GS = - 4.5 V; ID = - 5 A 100 RDS(on) - On-Resistance IS - Source Current (A) 1.3 (Normalized) 10 T J = 150 °C V GS = - 2.5 V; ID = - 4.4 A 1.1 1 T J = 25 °C 0.9 0.7 - 50 0.1 - 25 0 25 50 75 100 125 150 0 0.5 1.0 VSD - Source-to-Drain Voltage (V) TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature 0.10 ID = - 5 A RDS(on) - On-Resistance (Ω) Source-Drain Diode Forward Voltage 0.90 0.08 0.75 ID = - 250 μA 0.06 T J = 125 °C VGS(th) (V) 0.60 0.04 T J = 25 °C 0.45 0.02 1 2 3 4 5 0.30 - 50 - 25 0 25 50 75 100 125 150 VGS - Gate-to-Source Voltage (V) TJ - Temperature (°C) On-Resistance vs. Gate-to-Source Voltage 30 100 Single Pulse Power, Junction-to-Ambient Limited by RDS(on) * 24 10 18 ID - Drain Current (A) 100 μs Power (W) 1 1 ms 10 ms 100 ms 1 s, 10 s DC BVDSS Limited 12 0.1 6 TA = 25 °C Single Pulse 0.01 0.1 0 0.001 0.01 0.1 Time (s) 1 10 Threshold Voltage 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient www.vishay.com 4 Document Number: 66823 S10-1827-Rev. A, 09-Aug-10 New Product Si1441EDH Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 8 6 ID - Drain Current (A) Package Limited 4 2 0 0 25 50 75 100 125 150 TC - Case Temperature (°C) Current Derating* 4 1.2 3 Power (W) Power (W) 0.9 2 0.6 1 0.3 0 0 25 50 75 100 125 150 0.0 0 25 50 75 100 125 150 TC - Case Temperature (°C) TA - Ambient Temperature (°C) Power Derating, Junction-to-Foot Power Derating, Junction-to-Ambient * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 66823 S10-1827-Rev. A, 09-Aug-10 www.vishay.com 5 New Product Si1441EDH Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 0.1 0.05 0.02 Notes: PDM t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 125 °C/W Single Pulse 0.01 10-4 10 -3 3. TJM - TA = PDMZthJA (t) 4. Surface Mounted 10 -2 10 -1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66823. www.vishay.com 6 Document Number: 66823 S10-1827-Rev. A, 09-Aug-10 Package Information Vishay Siliconix SC 70: 6 LEADS MILLIMETERS 6 5 4 E1 E 1 2 3 -Be e1 D -Ac A2 A L A1 b INCHES Min 0.035 – 0.031 0.006 0.004 0.071 0.071 0.045 Dim A A1 A2 b c D E E1 e e1 L Min 0.90 – 0.80 0.15 0.10 1.80 1.80 1.15 Nom – – – – – 2.00 2.10 1.25 0.65BSC Max 1.10 0.10 1.00 0.30 0.25 2.20 2.40 1.35 Nom – – – – – 0.079 0.083 0.049 0.026BSC Max 0.043 0.004 0.039 0.012 0.010 0.087 0.094 0.053 1.20 0.10 1.30 0.20 7_Nom 1.40 0.30 0.047 0.004 0.051 0.008 7_Nom 0.055 0.012 ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5550 Document Number: 71154 06-Jul-01 www.vishay.com 1 AN815 Vishay Siliconix Single-Channel LITTLE FOOTR SC-70 6-Pin MOSFET Copper Leadframe Version Recommended Pad Pattern and Thermal Performance INTRODUCTION The new single 6-pin SC-70 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with Alloy 42 leadframes. These devices are intended for small to medium load applications where a miniaturized package is required. Devices in this package come in a range of on-resistance values, in n-channel and p-channel versions. This technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the single-channel version. EVALUATION BOARDS SINGLE SC70-6 The evaluation board (EVB) measures 0.6 inches by 0.5 inches. The copper pad traces are the same as in Figure 2. The board allows examination from the outer pins to 6-pin DIP connections, permitting test sockets to be used in evaluation testing. See Figure 3. 52 (mil) BASIC PAD PATTERNS 6 5 4 See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the basic pad layout and dimensions. These pad patterns are sufficient for the low to medium power applications for which this package is intended. Increasing the drain pad pattern yields a reduction in thermal resistance and is a preferred footprint. The availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the PCB and external environment. 96 (mil) 71 (mil) 1 13 (mil) 2 3 26 (mil) 0, 0 (mil) 18 (mil) 26 (mil) PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification.The pin-out of this device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. SOT-363 SC-70 (6-LEADS) D 1 6 5 D 16 (mil) FIGURE 2. SC-70 (6 leads) Single D 2 D The thermal performance of the single 6-pin SC-70 has been measured on the EVB, comparing both the copper and Alloy 42 leadframes. This test was first conducted on the traditional Alloy 42 leadframe and was then repeated using the 1-inch2 PCB with dual-side copper coating. G 3 4 S Top View FIGURE 1. For package dimensions see outline drawing SC-70 (6-Leads) (http://www.vishay.com/doc?71154) Document Number: 71334 12-Dec-03 www.vishay.com 1 AN815 Vishay Siliconix Front of Board SC70-6 Back of Board SC70-6 vishay.com FIGURE 3. THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (Package Performance) The junction to foot thermal resistance is a useful method of comparing different packages thermal performance. A helpful way of presenting the thermal performance of the 6-Pin SC-70 copper leadframe device is to compare it to the traditional Alloy 42 version. Thermal performance for the 6-pin SC-70 measured as junction-to-foot thermal resistance, where the “foot” is the drain lead of the device at the bottom where it meets the PCB. The junction-to-foot thermal resistance is typically 40_C/W in the copper leadframe and 163_C/W in the Alloy 42 leadframe — a four-fold improvement. This improved performance is obtained by the enhanced thermal conductivity of copper over Alloy 42. COOPER LEADFRAME Room Ambient 25 _C PD + T J(max) * T A Rq JA Elevated Ambient 60 _C PD + T J(max) * T A Rq JA o o P D + 150 Co* 25 C 124 C W o o P D + 150 Co* 60 C 124 C W P D + 1.01 W P D + 726 mW As can be seen from the calculations above, the compact 6-pin SC-70 copper leadframe LITTLE FOOT power MOSFET can handle up to 1 W under the stated conditions. Testing To further aid comparison of copper and Alloy 42 leadframes, Figure 5 illustrates single-channel 6-pin SC-70 thermal performance on two different board sizes and two different pad patterns. The measured steady-state values of RqJA for the two leadframes are as follows: Power Dissipation The typical RqJA for the single 6-pin SC-70 with copper leadframe is 103_C/W steady-state, compared with 212_C/W for the Alloy 42 version. The figures are based on the 1-inch2 FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the two different leadframes at varying ambient temperatures. LITTLE FOOT 6-PIN SC-70 Alloy 42 1) Minimum recommended pad pattern on the EVB board V (see Figure 3. 2) Industry standard PCB with maximum copper both sides. 1-inch2 329.7_C/W 211.8_C/W Copper 208.5_C/W 103.5_C/W ALLOY 42 LEADFRAME Room Ambient 25 _C PD + T J(max) * T A Rq JA Elevated Ambient 60 _C PD + T J(max) * T A Rq JA The results indicate that designers can reduce thermal resistance (RqJA) by 36% simply by using the copper leadframe device rather than the Alloy 42 version. In this example, a 121_C/W reduction was achieved without an increase in board area. If increasing in board size is feasible, a further 105_C/W reduction could be obtained by utilizing a 1-inch2 square PCB area. The copper leadframe versions have the following suffix: Single: Si14xxEDH Dual: Si19xxEDH Complementary: Si15xxEDH Document Number: 71334 12-Dec-03 o o P D + 150 Co* 25 C 212 C W o o P D + 150 Co* 25 C 212 C W P D + 590 mW www.vishay.com P D + 425 mW 2 AN815 Vishay Siliconix 400 250 320 Thermal Resistance (C/W) Thermal Resistance (C/W) 200 240 Alloy 42 150 Alloy 42 160 Copper 100 80 50 Copper 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs) 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs) FIGURE 4. Leadframe Comparison on EVB FIGURE 5. Leadframe Comparison on Alloy 42 1-inch2 PCB Document Number: 71334 12-Dec-03 www.vishay.com 3 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead 0.067 (1.702) (2.438) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE www.vishay.com 18 (1.143) 0.096 0.045 (0.648) 0.026 Document Number: 72602 Revision: 21-Jan-08 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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