CXD3423GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description The CXD3423GA is a timing generator and CCD signal processor IC for the ICX284, ICX432/434 CCD image sensor. Features • Timing generator functions • Horizontal drive frequency 18 to 24.3MHz (Base oscillation frequency 36 to 48.6MHz) • Supports frame readout/draft (sextuple speed)/ AF (Auto focus drive) (ICX432 mode) • Supports frame readout/draft (quadruple speed)/ AF (Auto focus drive) (ICX434 mode) • High-speed/low-speed shutter function • Horizontal and vertical drivers for CCD image sensor • CCD signal processor functions • Correlated double sampling • Programmable gain amplifier (PGA) allows gain adjustment over a wide range (–6 to +42dB) • 12-bit A/D converter • Chip Scale Package (CSP): CSP allows vast reduction in the CCD camera block footprint Applications Digital still cameras Applicable CCD Image Sensors ICX284 (Type 1/2.7, 2020K pixels) ICX432 (Type 1/2.7, 3240K pixels) ICX434 (Type 1/3.2, 2020K pixels) 96 pin LFLGA (Plastic)
Absolute Maximum Ratings • Supply voltage VDDa, VDDb, VDDc, VDDd VSS – 0.3 to +7.0 V VDDe, VDDf, VDDg VSS – 0.3 to +4.0 V VL –10.0 to VSS V VH VL – 0.3 to +26.0 V • Input voltage (analog) VIN VSS – 0.3 to VDD + 0.3 V • Input voltage (digital) VI VSS – 0.3 to VDD + 0.3 V • Output voltage VO1 VSS – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V VO3 VL – 0.3 to VH + 0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +125 °C Recommended Operating Conditions • Supply voltage VDDa, VDDb, VDDc, VDDd, VDDe, VDDf, VDDg 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75
V V V V °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02301A2X-PS
CXD3423GA
Block Diagram
TEST3 TEST4 TEST5 DVDD1 DVDD2 AVDD3 AVDD4 DVSS3 DVSS1 DVSS2 AVSS3 AVSS4 AVSS5 SCK2 SEN2 SSI2
C3
C2
C7 D8 D7
C1
B8 B6 B9 A6 C5
A3 A4 B4
A5 C4
B5
E2 F2 F3
E3 F1
C4 C8 AVDD5 A9 AVSS6 A8 C7 B7 C8 A7 C9 C6 CCDIN C9 AVDD1 E9 AVDD2 E8 AVSS1 D9 AVSS2 E7 XSHPI F9 XSHDI F8 PBLKI F7 XSHP G9 XSHD G8 PBLK G7 CDS PGA ADC Latch DAC Serial Port Register A2 D0 (LSB)
A1 D1 B3 B2 B1 D2 D3 D4
C3 D5 C2 D6 C1 D7 D3 D8 D2 D9 D1 D10 E1 D11 (MSB)
Preblanking
Dummy Pixel Auto Zero
Black Level Auto Zero
G1 G2 G3
ADCLKI CLPOBI CLPDMI
H1 VDD4 H8 VDD2 K7 RG K8 VSS2 K9 VDD3 H9 H1 J8 H2 J9 VSS3 J7 ID/EXP N9 WEN/FLD M9 L2 VH L5 VM M3 VL M6 Selector SSG L8 V Driver Serial Port Register Latch 1/2 Selector Pulse Generator H2 H3 J3 L1 K1 J1 J2 K2
ADCLK CLPOB CLPDM VSS4 OSCI OSCO CKI CKO MCKO
N8 SNCSL SSI1
M1 SCK1 N1 SEN1
SSGSL
H7
TEST1
L3 M8
RST TEST2
L4 M5 N5 M4 L6 N6 N4 N7 M7
V5B/V3B V2/NC V3A/V1A V3B/V1B V5A/V3A V1/NC V4/V2 V6/V4 SUB
N2 M2
HD VD
L9
VDD1
K3 L7
VDD5 VSS1
N3
VSS5
–2–
CXD3423GA
Pin Configuration (Top View)
A
D1
D0
SCK2
SSI2
TEST3
AVSS4
C8
AVSS6
AVDD5
B
D4
D3
D2
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
C
D7
D6
D5
TEST4
AVSS5
C9
C3
C4
CCDIN
D
D10
D9
D8
C1
C2
AVSS1
E
D11
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
F
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
G
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
H
ADCLK
CLPOB
CLPDM
TEST1
VDD4
VDD3
J
CKI
CKO
VSS4
VSS3
H1
H2
K
OSCO
MCKO
VDD5
VDD2
RG
VSS2
L
OSCI
SSI1
TEST2
V4 (V2)
VH
V3A (V1A)
VSS1
SSGSL
VDD1
M
SCK1
VD
VM
V2 (NC)
V5B (V3B)
VL
SUB
RST
WEN/FLD
N
SEN1
HD
VSS5
V5A (V3A)
V1 (NC)
V3B (V1B)
V6 (V4)
SNCSL
ID/EXP
1
2
3
4
5
6
7
8
9
Note) The symbol in parenthesis is for ICX434 mode.
–3–
CXD3423GA
Pin Description Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 D8 D9 E1 E2 E3 E7 Symbol D1 D0 SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D4 D3 D2 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D7 D6 D5 TEST4 AVSS5 C9 C3 C4 CCDIN D10 D9 D8 C1 C2 AVSS1 D11 DVDD1 DVSS1 AVSS2 I/O O O I I I — — — — O O O I I — — — — O O O I — — — — I O O O — — — O — — — ADC output. ADC output (LSB). CCD signal processor block serial interface clock input. (Schmitt trigger) CCD signal processor block serial interface data input. (Schmitt trigger) CCD signal processor block test input 3. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. CCD signal processor block analog GND. CCD signal processor block analog power supply. ADC output. ADC output. ADC output. CCD signal processor block serial interface enable input. (Schmitt trigger) CCD signal processor block test input 5. Connect to DVDD. CCD signal processor block analog power supply. Capacitor connection. CCD signal processor block analog power supply. CCD signal processor block analog GND. ADC output. ADC output. ADC output. CCD signal processor block test input 4. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. Capacitor connection. Capacitor connection. CCD output signal input. ADC output. ADC output. ADC output. Capacitor connection. Capacitor connection. CCD signal processor block analog GND. ADC output (MSB). CCD signal processor block digital power supply. (Power supply for ADC) CCD signal processor block digital GND. (GND for ADC) CCD signal processor block analog GND. –4– Description
CXD3423GA
Pin No. E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 J9 K1 K2 K3 K7 K8 K9 L1 L2
Symbol AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM TEST1 VDD4 VDD3 CKI CKO VSS4 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI SSI1
I/O — — — — — I I I I I I O O O O O O I — — I O — — O O O O — — O — I I
Description CCD signal processor block analog power supply. CCD signal processor block analog power supply. CCD signal processor block digital GND. CCD signal processor block digital GND. CCD signal processor block digital power supply. Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger) CCD data level sample-and-hold pulse input. (Schmitt trigger) CCD precharge level sample-and-hold pulse input. (Schmitt trigger) Clock input for analog/digital conversion. (Schmitt trigger) CCD optical black signal clamp pulse input. (Schmitt trigger) CCD dummy signal clamp pulse input. (Schmitt trigger) Pulse output for horizontal and vertical blanking period pulse cleaning. CCD data level sample-and-hold pulse output. CCD precharge level sample-and-hold pulse output. Clock output for analog/digital conversion. Logical phase adjustment possible using the serial interface data. CCD optical black signal clamp pulse output. Horizontal and vertical OB pattern charge possible using the serial interface data. CCD dummy signal clamp pulse output. Timing generator block test input 1. Normally fix to GND. (With pull-down resistor) Timing generator block digital power supply. (Power supply for CDS block) Timing generator block digital power supply. (Power supply for H1/H2) Inverter input. Inverter output. Timing generator block digital GND. Timing generator block digital GND. CCD horizontal register clock output. CCD horizontal register clock output. Inverter output for oscillation. When not used, leave open or connect a capacitor. System clock output for signal processor IC. Timing generator block digital power supply. (Power supply for common logic block) Timing generator block digital power supply. (Power supply for RG) CCD reset gate pulse output. Timing generator block digital GND. Inverter input for oscillation. When not used, fix to low. Timing generator block serial interface data input. Schmitt trigger input.
–5–
CXD3423GA
Pin No. L3 L4 L5 L6 L7 L8 L9 M1 M2 M3 M4 M5 M6 M7 M8
Symbol TEST2 V4 (V2) VH V3A (V1A) VSS1 SSGSL VDD1 SCK1 VD VM V2 (NC) V5B (V3B) VL SUB RST
I/O I O — O — I — I I/O — O O — O I
Description Timing generator block test input 2. Normally fix to GND. (With pull-down resistor) CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. Timing generator block 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. Timing generator block digital GND. Internal SSG enable. High: Internal SSG valid, Low: External sync valid (With pull-down resistor) Timing generator block digital power supply. (Power supply for common logic block) Timing generator block serial interface clock input. Schmitt trigger input. Vertical sync signal input/output. Timing generator block GND. (GND for vertical driver) CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. Timing generator block –7.5V power supply. (Power supply for vertical driver) CCD electric shutter pulse. Timing generator block reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input. Memory write timing pulse output/field discrimination pulse output. Switching possible using the serial interface data. (Default: WEN output) Timing generator block serial interface strobe input. Schmitt trigger input. Horizontal sync signal input/output. Timing generator block digital GND. CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode. Control input used to switch sync system. High: CKI sync, Low: MCKO sync (With pull-down resistor) Vertical direction line identification pulse output/Exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID output)
M9 N1 N2 N3 N4 N5 N6 N7 N8 N9
WEN/FLD SEN1 HD VSS5 V5A (V3A) V1 (NC) V3B (V1B) V6 (V4) SNCSL ID/EXP
O I I/O — O O O O I O
–6–
CXD3423GA
Electrical Characteristics Timing Generator Block Electrical Characteristics DC Characteristics Item Pins Symbol VDDa VDDb VDDc VDDd VI+ VI– 0.7VDDd 0.3VDDd 0.8VDDd 0.2VDDd Feed current where IOH = –1.2mA VDDd – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –14.0mA VDDb – 0.8 Pull-in current where IOL = 9.6mA Feed current where IOH = –3.3mA VDDa – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –3.3mA VDDc – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –6.9mA VDDd – 0.8 Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA VDDd – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA VDDd – 0.8 Pull-in current where IOL = 4.8mA V1, V2, V3A/B, V4, V5A/B, V6 = –8.25V V1, V2, V3A/B, V4, V5A/B, V6 = –0.25V V1, V3A/B, V5A/B = 0.25V V1, V3A/B, V5A/B = 14.75V SUB = –8.25V SUB = 14.75V 5.4 –4.0 5.0 –7.2 10.0 –5.0 0.4 0.4 0.4 0.4 0.4 0.4 0.4 (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd 0.2VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 3.6 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
Supply voltage 1 VDD2 Supply voltage 2 VDD3 Supply voltage 3 VDD4 Supply voltage 4 VDD1, VDD5 Input voltage 1∗1 Input voltage 2∗2 RST, SSI1, SCK1, SEN1
TEST1, TEST2, VIH1 SNCSL, SSGSL VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3
Input/output voltage
VD, HD
Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6
H1, H2 RG
XSHP, XSHD, VOH4 PBLK, CLPOB, CLPDM, VOL4 ADCLK CKO MCKO ID/EXP, WEN/FLD VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL
Output current 1
V1, V2, V3A, V3B, V4, V5A, V5B, V6
IOM1 IOM2 IOH IOSL
Output current 2
SUB
IOSH
∗1 This input pin is a schmitt trigger input. ∗2 These input pins are with pull-down resistor in the IC. Note) The above table indicates the condition for 3.3V drive. –7–
CXD3423GA
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI OSCO OSCI, OSCO OSCI, OSCO Symbol LVth VIH VIL VOH VOL RFB f Conditions
(Within the recommended operating conditions) Min. 0.7VDDd 0.3VDDd Typ. VDDd/2 Max. Unit V V V V 0.4 500k 20 2M 5M 50 V Ω MHz
Feed current where IOH = –3.6mA Pull-in current where IOL = 2.4mA VIN = VDDd or VSS
VDDd – 0.8
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Symbol TTLM TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = –7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –8–
CXD3423GA
Switching Waveforms
TTMH 90% TTHM VH 90%
V1 (V3A, V3B, V5A, V5B)
TTLM
10% 90%
10% 90%
TTML
VM
10%
10%
VL
TTLM 90% V2 (V4, V6) 10% 90%
TTML VM
10%
VL
TTLH 90% 90%
TTHL
VH
SUB
10%
10% VL
Waveform Noise
VM VCMH VCML
VCLH VCLL VL
–9–
Measurement Circuit
Serial interface data CKI
VD C6 C4 C5 C5 C6
HD
+3.3V
+15.0V N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7 H2 RG H1 VSS5 VSS4 CKI VSS2 VSS3 VDD5 CKO VDD2 SSI1 OSCI VDD3 VDD4 VSS4 XSHP MCKO OSCO TEST1 XSHD CLPDMI G3 CLPOBI G2 ADCLK H1 XSHPI F9 XSHDI F8 PBLKI F7 DVDD2 F3 DVSS3 F2 ADCLKI G1 AVDD1 E9 AVSS1 D9 AVSS2 E7 CXD3423GA DVSS2 F1 DVSS1 E3 DVDD1 E2 AVDD2 E8 C2 D8 C1 D7 D8 D3 D9 D2 D10 D1 CCDIN C9 C4 C8 C3 C7 D1 SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D4 D3 D2 SEN2 TEST5 AVDD4 C7 AVSS3 AVDD3 D7 D6 D5 TEST4 D0 AVSS5 C9 A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6 PBLK
–7.5V
L4 V4 L5 VH M6 VL N7 V6 L8 SSGSL L9 VDD1 M1 SCK1 M2 VD M3 VM M4 V2 M5 V5B L6 V3A L3 TEST2 M8 RST M9 WEN/FLD N1 SEN1 N2 HD N3 VM N4 V5A N6 V3B M7 SUB L7 VSS1 N8 SNCSL N9 ID/EXP N5 V1 C3
R1
C2
C2
R1
C1 C2
R1
C1
C2
C2 C2
C1 C2
– 10 –
C2 R2 560pF 10Ω C3 820pF C4 8pF C5
C2
C2
C2
C2
C1
R1
C2
C2
C1
R1
C1
C2
C2 R2
R1
CXD3423GA
C1 R1
3300pF 30Ω
180pF
C6
CLPDM
CLPOB
E1 D11
10pF
CXD3423GA
AC Characteristics AC characteristics between the serial interface clocks
0.8VDDd SSI1 SCK1 SEN1 SEN1 ts2 0.2VDDd 0.8VDDd ts1 0.2VDDd ts3 0.8VDDd th1
(Within the recommended operating conditions) Symbol ts1 th1 ts2 ts3 Definition SSI1 setup time, activated by the rising edge of SCK1 SSI1 hold time, activated by the rising edge of SCK1 SCK1 setup time, activated by the rising edge of SEN1 SEN1 setup time, activated by the rising edge of SCK1 Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode VD HD
V1, V3A/B, V5A/B Enlarged view HD V1, V3A/B, V5A/B ts1 SEN1 0.8VDDd 0.2VDDd th1
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period during which V1, V3A/B and V5A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol ts1 th1 Definition SEN1 setup time, activated by the falling edge of HD SEN1 hold time, activated by the falling edge of HD – 11 – Min. 0 123 Typ. Max. Unit ns µs
CXD3423GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode VD HD Enlarged view
VD
0.2VDDd
HD ts1 SEN1 0.8VDDd 0.2VDDd th1
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol ts1 th1 Definition SEN1 setup time, activated by the falling edge of VD SEN1 hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns
Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3423GA at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3423GA and controlled at the rising edge of SEN1. See "Description of Operation".
SEN1
0.8VDDd
Output signal tpdPULSE
(Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns
tpdPULSE Output signal delay, activated by the rising edge of SEN1
– 12 –
CXD3423GA
RST loading characteristics
RST
0.8VDDd 0.2VDDd tw1
(Within the recommended operating conditions) Symbol tw1 RST pulse width Definition Min. 35 Typ. Max. Unit ns
VD and HD loading characteristics
VD, HD
0.2VDDd ts1 th1
0.2VDDd
MCKO
0.8VDDd
MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol ts1 th1 Definition VD and HD setup time, activated by the rising edge of MCKO VD and HD hold time, activated by the rising edge of MCKO Min. 13 0 Typ. Max. Unit ns ns
Output variation characteristics
MCKO WEN/FLD, ID/EXP
0.8VDDd
tpd1
WEN/FLD and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 20 Typ. Max. 60 Unit ns
– 13 –
CXD3423GA
CCD Signal Processor Block Electrical Characteristics DC Characteristics Item Pins Symbol VDDe VDDf (Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Conditions Min. 3.0 3.0 Typ. Max. Unit 3.3 3.3 3.6 3.6 V V
Supply voltage 1 DVDD1 Supply voltage 2 DVDD2 AVDD1, AVDD2, Supply voltage 3 AVDD3, AVDD4, AVDD5 Analog input capacitance CCDIN
VDDg
3.0
3.3
3.6
V
CIN
15 1.8
pF V
Input voltage
SCK2, SSI2, VI+ SEN2, TEST3, TEST4, XSHDI, XSHPI, ADCLKI, VI– CLPOBI, CLPDMI, PBLKI ADCLKI D0 to D11 VOH VOL Feed current where IOH = –2.0mA VDDe – 0.9 Pull-in current where IOL = 2.0mA
1.1
V
A/D clock duty Output voltage
50 0.4
% V V
Analog Characteristics Item CCDIN input voltage amplitude PGA maximum gain PGA minimum gain ADC resolution ADC maximum conversion rate ADC integral non-linearity error ADC differential non-linearity error Signal-to-noise ratio CCDIN input voltage clamp level CCD optical black signal clamp level Fc max EL ED SNR CLP OB Pins VIN Gmax Gmin
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Conditions PGA gain = 0dB, output full scale PGA gain setting data = "3FFh" PGA gain setting data = "000h" 24.3 PGA gain = 0dB PGA gain = 0dB PGA gain = 0dB OBLVL = "8h" PGA gain = 0dB ±2.0 ±1.0 77 1.5 130 Min. 900 42 –6 12 Typ. Max. Unit 1100 mV dB dB bit MHz LSB LSB dB V LSB
– 14 –
CXD3423GA
AC Characteristics AC characteristics between the serial interface clocks
0.8VDD SSI2 SCK2 SEN2 SEN2 ts2 0.2VDD 0.8VDD ts1 0.2VDD ts3 0.8VDD th1
∗ The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise of SEN2. (Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol tp1 ts1 th1 ts2 ts3 SCK2 clock period SSI2 setup time, activated by the rise of SCK2 SSI2 hold time, activated by the rise of SCK2 SCK2 setup time, activated by the rise of SEN2 SEN2 setup time, activated by the rise of SCK2 Definition Min. 100 30 30 30 30 Typ. Max. Unit ns ns ns ns ns
– 15 –
CXD3423GA
CDS/ADC Timing Chart
N CCDIN
N+1
N+2
N+3
XSHPI
XSHDI tw1
ADCLKI DL
D0 to D11
N – 10
N–9
N–8
N–7
∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0". (Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol tw1 DL ADCLKI clock period ADCLKI clock duty Data latency Definition Min. 41 50 9 Typ. Max. Unit ns % clocks
Preblanking Timing Chart
PBLKI 11 Clocks
ADCLKI
11 Clocks D0 to D11 All "0"
– 16 –
CXD3423GA
Description of Operation Pulses output from the CXD3423GA's timing generator block are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on page 19 and thereafter. Pin Status Table Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 Symbol D1 D0 SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D4 D3 D2 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D7 D6 D5 TEST4 AVSS5 C9 C3 C4 CCDIN D10 D9 D8 C1 CAM SLP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — STB RST Pin No. D8 D9 E1 E2 E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 – 17 – Symbol C2 AVSS1 D11 DVDD1 DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM TEST1 VDD4 VDD3 CKI CKO VSS4 VSS3 H1 ACT L ACT ACT ACT ACT — — L ACT ACT ACT ACT ACT ACT ACT L L L L L L — — — ACT L ACT ACT CAM SLP — — — — — — — — — — — — — — — — — L L L L L L H ACT ACT ACT H H STB RST
CXD3423GA
Pin No. J9 K1 K2 K3 K7 K8 K9 L1 L2 L3 L4 L5 L6 L7 L8 L9 M1
Symbol H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI SSI1 TEST2 V4 (V2) VH V3A (V1A) VSS1 SSGSL VDD1 SCK1
CAM ACT ACT ACT
SLP L ACT ACT — —
STB L ACT L
RST ACT ACT ACT
Pin No. M2 M3 M4 M5 M6
Symbol VD∗1 VM V2 (NC) V5B (V3B) VL SUB RST WEN/FLD SEN1 HD∗1 VSS5 V5A (V3A) V1 (NC) V3B (V1B) V6 (V4) SNCSL ID/EXP
CAM ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT
SLP L — VM VH — VH ACT L ACT L — VH VH VH VH ACT L
STB L VM VH VH ACT L ACT L VH VH VH VH ACT L
RST H VM VL VL L L DIS H VL VM VM VL ACT L
ACT ACT ACT ACT ACT ACT ACT
L — ACT ACT — VM — VH — ACT — ACT
L ACT ACT VM VH ACT ACT
ACT ACT DIS VM VM ACT DIS
M7 M8 M9 N1 N2 N3 N4 N5 N6 N7 N8 N9
∗1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin L5), VM (Pin M3) and VL (Pin M6), respectively, in the controlled status.
– 18 –
CXD3423GA
Timing Generator Block Serial Interface Control The CXD3423GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V3A/B and V5A/B, etc. take the ternary value. Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the rising edge of SEN1.
SSI1 SCK1 SEN1
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
There are two categories of timing generator block serial interface data: CXD3423GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below.
– 19 –
CXD3423GA
Control Data Data Symbol D00 to D07 D08 D09 to D11 CHIP CTG — Chip enable Category switching — Drive mode switching — Internal SSG function switching∗1 CCD switching∗1 — Electronic shutter mode switching∗2 HTSG control switching∗2 — WEN/FLD output switching Wide CLPOB generation switching ID/EXP output switching CLPOB waveform pattern switching ADCLK logic phase adjustment Standby control — FL — Function Data = 0 Data = 1 RST All 0 0 — All 0 0 0 0 0 0 0 0 All 0 0 0 0 All 0 All 0 All 0 — All 0
10000001 → Enabled Other values → Disabled See D08 CTG.
D12, MODE D13 D14, D15 D16 D17 D18, D19 D20 D21 D22 to D30 D31 D32 D33 — NTPL CCD — SMD HTSG — FLD FGOB EXP
See D12 , D13 MODE. — NTSC ICX432 — OFF OFF — WEN OFF ID — PAL ICX284/434 — ON ON — FLD ON EXP
D34, PTOB D35 D36, LDAD D37 D38, STB D39 D40 to D47 —
See D34 , D35 PTOB. See D36 , D37 LDAD. See D38 , D39 STB. —
∗1 See D12 , D13 MODE. ∗2 See D20 SMD.
– 20 –
CXD3423GA
Shutter Data Data Symbol D00 to D07 CHIP Chip enable Category switching — Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification — Function Data = 0 Data = 1 RST All 0 0 0 All 0 All 0 All 0 All 0
10000001 → Enabled Other values → Disabled See D08 CTG. — See D10 to D19 SVD.
D08 CTG D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 — SVD
SHD
See D20 to D31 SHD.
SPL
See D32 to D41 SPL.
—
—
– 21 –
CXD3423GA
Detailed Description of Each Data Shared data: D08 CTG [Category] Of the data provided to the CXD3423GA by the timing generator block serial interface, the CXD3423GA loads D10 and subsequent data to each data register as shown in the table below according to D08 . D08 0 1 Description of operation Loading to control data register Loading to shutter data register
Note that the CXD3423GA can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied.
Control data: D12 , D13 MODE [Drive mode] The CXD3423GA drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD3423GA and reflected at the falling edge of VD. D13 0 0 1 1 D12 0 1 0 1 Description of operation Draft mode (default) Frame mode AF mode∗1 Test mode
∗1 The test mode results in ICX284/434 mode. Draft mode is the pulse elimination drive mode. This is a high frame rate drive mode that can be used for purposes such as monitoring and moving pictures. AF mode is the drive mode for applications with an even higher frame rate, and is used for auto focus (AF). Frame mode is the drive mode in which the data for all lines of the ICX284/432/434 are read.
Control data: D16 NTPL [SSG function switching] The CXD3423GA internal SSG output pattern can be switched as follows. However, the drive mode bits are loaded to the CXD3423GA and reflected at the falling edge of VD. The default is "NTSC". D16 0 1 Description of operation NTSC equivalent pattern output (internal SSG) PAL equivalent pattern output (internal SSG)
– 22 –
CXD3423GA
Control data: D17 CCD [Used CCD switching] This specifies the CCD image sensor to be used. However, like the drive mode bits, the CCD switching bits are loaded to the CXD3423GA and reflected at the falling edge of VD. The default is "ICX432". D17 0 1 Description of operation ICX432 ICX284/434
Control data: D32 FGOB [Wide CLPOB generation] This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual operation. The default is "OFF". D32 0 1 Description of operation Wide CLPOB generation OFF Wide CLPOB generation ON
Control data: D34 , D35 PTOB [CLPOB waveform pattern] This indicates the CLPOB waveform pattern. The default is "Normal". D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Shifted rearward) (Shifted forward) (Wide)
Control data: D36 , D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment (°) 0 90 180 270
Control data: D38 , D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD3423GA and control is applied immediately at the rising edge of SEN1. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode
See the Pin Status Table for the pin status in each mode. – 23 –
CXD3423GA
Control data/shutter data: [Electronic shutter] The CXD3423GA realizes various electronic shutter functions by using control data D20 SMD and D21 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D20 SMD. D20 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 X D30 D29 D28 D27 0 ↓ 1 0 1 1 D26 D25 D24 D23 1 ↓ C 0 0 0 0 1 LSB D22 D21 D20 ↓ 3 1 → SHD is expressed as 1C3h .
[Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3423GA functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD × (1V period) + {(number of HD per 1V) – (SHD + 1)} × (1H period) + (distance from SUB to SG during the readout period) Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). – 24 –
CXD3423GA
VD
SHD
SVD
V1A SUB WEN EXP SMD SVD SHD Exposure time 01 002h 10Fh 01 000h 050h
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL 000 VD SHD V1A SUB WEN EXP SMD SPL SVD SHD 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVD 002
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. – 25 –
CXD3423GA
[HTSG control mode] This mode controls the ternary level outputs of V1, V3A/B, V5A/B (readout pulse block) using D21 HTSG. D21 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode
VD
V1A SUB VCK WEN EXP HTSG SMD 0 1 1 0 0 1
Exposure time
[EXP pulse] The ID/EXP pin (Pin N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. In principle, the transition points are the last SUB pulse falling edge and the readout pulse falling edge, that is to say from the time the charge is completely discharged until transfer ends. However, when the readout pulse timing differs within the same readout portion such as in draft mode, the average value is used. Then, when there is no SUB pulse in the next field, the readout pulse falling edge is defined as the start position, but in this case the transition points overlap and disappear, so a tentative start position is defined. This is shown below. SG↓ [ICX432] Frame mode Draft/AF mode Frame mode Draft mode 1460 1682 A: 1071 B: 1175 1123 Tentative start position 1480 1784 1091 1195 1175
[ICX284/ 434]
See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
– 26 –
Chart-A1 Vertical Direction Timing Chart
Frame mode
A Field B Field C Field
MODE
Applicable CCD image sensor • ICX432
VD
43 564 588 1 43 564 588 1 43
565
588 1
HD
SUB [A]
High-speed sweep block High-speed sweep block
[D]
High-speed sweep block
[B]
[C]
V1
V2
V3A
V3B
V4
1
4
7
2
5
8
3
6 1 3 6 9
2
5
1546
1549
8
1547
1550
1236
1545
CCD OUT
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to (high, low, low) in the horizontal periods of each readout portion (A, B, C). ∗ WEN/FLD of this chart shows WEN. ∗ The shaded portion of CLPOB shows the range over which the wide CLPOB can be set by the serial interface data. ∗ VD of this chart is indicated in NTSC equivalent pattern 587H (1H: 2760ck) + 1500ck units. For PAL equivalent pattern, it is 704H + 960ck units.
1548
4
– 27 –
V5A
V5B
V6
CXD3423GA
Chart-A2 Vertical Direction Timing Chart
Draft mode
• ICX432
MODE
Applicable CCD image sensor
VD
3 263 270 1 3
263
270 1
HD
SUB [E]
[E]
V1
V2
V3A
V3B
V4
V5A
6
5
6
10
17
22
29
30
5
10
17
22 4 1 8 13 20
29 25
4
CCD OUT
1 8 13 20 25 28 1549
1532 1534
1537 1541 1544 1546
1549
1525 1527
1532 1534
1537 1541
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to low in the horizontal periods of each readout portion (E). ∗ WEN/FLD of this chart shows WEN. ∗ The shaded portion of CLPOB shows the range over which the wide CLPOB can be set by the serial interface data. ∗ VD of this chart is indicated in NTSC equivalent pattern 269H (1H: 3004ck) + 2734ck units. For PAL equivalent pattern, it is 323H + 1708ck units.
1544 1546
28
30
– 28 –
V5B
V6
CXD3423GA
Chart-A3 Vertical Direction Timing Chart
AF mode
• ICX432
MODE
Applicable CCD image sensor
VD
135 1 3 27 123 135 1 3 27
123
HD
SUB [E]
Frame shift block High-speed sweep block Frame shift block
[G]
High-speed sweep block
[F]
[G]
[E]
[F]
V1
V2
V3A
V3B
V4
V5A
6
4
481 485
488 490
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
1525 1527
4
CCD OUT
6
– 29 –
V5B
V6
CXD3423GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to high in the horizontal periods of each readout portion (E). ∗ WEN/FLD of this chart shows WEN. ∗ The shaded portion of CLPOB shows the range over which the wide CLPOB can be set by the serial interface data. ∗ VD of this chart is indicated in NTSC equivalent pattern 134H (1H: 3004ck) + 2869ck units. For PAL equivalent pattern, it is 161H + 2356ck units. In addition, for PAL equivalent pattern, the high-speed sweep block starts from 150H.
Chart-A4 Horizontal Direction Timing Chart
Frame mode
200 300 400 500 600 700 800 900 1000
MODE
Applicable CCD image sensor • ICX432
(2760) 0
100
HD
MCKO
672 676 680
5
52
644
H1
H2
182 308
V1
266 392
V2
350 476
V3A/B
434 560
V4
518
140
V5A/B
224 602
– 30 –
670 674 646 670
V6
52
135
SUB
52
PBLK
20
44
CLPOB
50
CLPOB (wide)
CLPDM
140
ID/EXP
140
WEN/FLD
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-A1. ∗ CLPOB also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-A1.
CXD3423GA
These timings can be switched by the serial interface data.
Chart-A5 Horizontal Direction Timing Chart
Draft/AF mode
200 300 400 500 600 700 800 900 1000
MODE
Applicable CCD image sensor • ICX432
(3004) 0
100
HD
MCKO
916 920 924
5
52
888
H1
H2
171 264 543 636
V1
233 326 605 698
V2
295 388 667 760
V3A/B
357 450 729 822
V4
419 512 791
140
V5A/B
202 481 574 853
– 31 –
V6
52
135
SUB
914
52
PBLK
20
44
CLPOB
918
50
CLPOB (wide)
890 914
CLPDM
140
ID/EXP
140
WEN/FLD
CXD3423GA
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-A2 and A3. ∗ CLPOB also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-A2 and A3. These timings can be switched by the serial interface data.
MODE
Applicable CCD image sensor • ICX432
Chart-A6 Horizontal Direction Timing Chart (High-speed sweep: D)
Frame mode
(2760) 0 200 300 400 100 200
100
(2760) 0
HD
MCKO
5 52
5
52
H1
H2
176 248 284 356 392 1952 1988 2060 182
140
V1
158 194 266 302 374 410 1970 2006
V2
176 212 284 320 392 428 1988 2024
V3A/B
194 230 302 338 410 446 2006 2042
V4
212 248 320 356 428 1952 2024 140
140
– 32 –
158 230 266 338 374 446 1970 2042
V5A/B
224
V6 #1 #2 #3 #1039 #1040
52 135
52
135
SUB
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
CXD3423GA
MODE
Applicable CCD image sensor • ICX432
Chart-A7 Horizontal Direction Timing Chart (Frame shift: F)
AF mode
(3004) 0 200 300 400 500 600 700 800 900 1000
100
HD
MCKO
916 920 924
5
52
888
H1
H2
171 264 543 636 915 1008
V1
233 326 605 698 977
V2
295 388 667 760 1039
V3A/B
357 450 729 822
V4
419 512 791 884
140
– 33 –
202 481 574
V5A/B
853 946
V6 #1 #2
52
135
SUB
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
CXD3423GA
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ Frame shift of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 24H 1096ck (#78).
MODE
Applicable CCD image sensor • ICX432
Chart-A8 Horizontal Direction Timing Chart (High-speed sweep: G)
AF mode
(3004) 0 200 300 400 500 600 700 800 900 1000
100
HD
MCKO
916 920 924
5
52
888
H1
H2
188 296 332 440 476 584 620 728 764 872 908 1016 1052
152
V1
176 212 320 356 464 500 608 644 752 788 896 932 1040
V2
200 236 344 380 488 524 632 668 776 812 920 956
V3A/B
224 260 368 404 512 548 656 692 800 836 944 980
V4
248 284 392 428 536 572 680 716 824 860 968 1004
140
– 34 –
164 272 308 416 452 560 596 704
V5A/B
740 848 884 992 1028
V6 #1 #2 #3
52
135
SUB
PBLK
CLPOB
CLPDM
ID/EXP
140
WEN/FLD
CXD3423GA
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ High-speed sweep of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 133H 2932ck (#114).
Chart-A9aHorizontal Direction Timing Chart
Frame mode
1254 1296 1338 1380 1420 1460 1502 1546
(2760) 0
MODE
Applicable CCD image sensor • ICX432
140
182
224
266
308
350
392
434
476
518
560
HD [A]
A Field
V1
V2
V3A/B
V4
V5A/B
– 35 –
[B]
V6
B Field
V1
V2
V3A/B
V4
V5A/B
V6
602
(2760) 0
CXD3423GA
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
Chart-A9b Horizontal Direction Timing Chart
Frame mode
1086 1128 1170 1212 1254 1296 1338 1380 1420 1460
(2760) 0
MODE
Applicable CCD image sensor • ICX432
140
182
224
266
308
350
392
434
476
518
560
HD [C]
C Field
V1
V2
V3A/B
V4
V5A/B
V6
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
602
(2760) 0
– 36 –
CXD3423GA
Chart-A10Horizontal Direction Timing Chart
Draft/AF mode
• ICX432
MODE
Applicable CCD image sensor
1407
1438
1469
1500
1540
1580
1611
1642
1673
1704
1744
1784
1815
1846
1877
1908
140
171
202
233
264
295
326
357
388
419
450
481
512
543
574
605
636
667
698
HD
[E]
V1
V2
V3A
V3B
– 37 –
V4
V5A
V5B
V6
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
729
(3004) 0
(3004) 0
CXD3423GA
Chart-A11Vertical Direction Sequence Chart
Draft → Frame → Draft
• ICX432
MODE
Applicable CCD image sensor
VD
V1
V2
V3A
V3B
V4
V5A
– 38 –
C Close B 000 1 050h 000h 0 010 C (1st) C (2nd) 010 0 000h
V5B
V6 D
SUB
A
B
Mechanical shutter
Open C (3rd) 010 0 000h 000 1 050h D 000 1 050h
CCD OUT
A
MODE
000
000
SMD
1
1
SHR
050h
050h
CXD3423GA
∗ This chart is a driving timing chart example of electronic shutter normal operation. ∗ Data exposed at B includes a blooming component. For details, see the CCD image sensor data sheet. ∗ The CXD3423GA does not generate the pulse to control mechanical shutter operation. ∗ The drive mode and the electronic shutter data are not switched at the same timing.
Chart-B1 Vertical Direction Timing Chart
Frame mode
• ICX434
MODE
Applicable CCD image sensor
A Field
B Field
VD
25 31 650 1 24 31
650 1
HD
SUB [A] [C]
High-speed sweep block
[C] High-speed sweep block
[B]
V1A
V1B
V2
V3A
1
3
5
2
7
9
4
6
8
1
3
5
7
9
10
2
4
6
11
13
15
17
19
21
23
25
27
8
10
1225
1227
1229
1231
1233
1228
1230
1232
1234
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
1236
1235
CCD OUT
12
– 39 –
V3B
V4
CXD3423GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to (high, low) in the horizontal periods of each readout portion (A, B). ∗ WEN/FLD of this chart shows WEN. ∗ VD of this chart is indicated in NTSC equivalent pattern 650H (1H: 1848ck) units. For PAL equivalent pattern, it is 779H + 408ck units. ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
Chart-B2 Vertical Direction Timing Chart
Draft mode
• ICX434
MODE
Applicable CCD image sensor
VD
12 16 325 1 12 16
325 1
HD
SUB [D] [D]
V1A
V1B
V2
V3A
4
9
4
2
7
9
2
10
15
18
23
26
31
34
39
42
47
50
55
58
63
7
10
15
18
23
26
31
1207
1210
1215
1218
1223
1226
1231
1234
1202
1207
1210
1215
1218
1223
1226
1231
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
1234
CCD OUT
34
– 40 –
V3B
V4
CXD3423GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to high in the horizontal periods of each readout portion (D). ∗ WEN/FLD of this chart shows WEN. ∗ VD of this chart is indicated in NTSC equivalent pattern 325H (1H: 1848ck) units. For PAL equivalent pattern, it is 389H + 1128ck units. ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
Chart-B3 Horizontal Direction Timing Chart
Frame mode
50 100 150 200 250
MODE
Applicable CCD image sensor • ICX434
(1848) 0
HD
MCKO
56 188
H1
H2
72 120
V1A/B
104 152
V2
56 136
V3A/B
88 168
V4
88 152
– 41 –
56 45 51 104 104
SUB
214
PBLK
19
CLPOB
216
CLPOB (wide)
190 214
CLPDM
ID/EXP
WEN/FLD
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-B1. ∗ CLPOB also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-B1.
CXD3423GA
These timings can be switched by the serial interface data. ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
Chart-B4 Horizontal Direction Timing Chart
Draft mode
50 100 150 200 250
MODE
Applicable CCD image sensor • ICX434
(1848) 0
HD
MCKO
56 188
H1
H2
56 88 120 152
V1A/B
72 104 136 168
V2
56 88 120 152
V3A/B
72 104 136 168
V4
88 152
– 42 –
56 45 51 104 104
SUB
214
PBLK
19
CLPOB
216
CLPOB (wide)
190 214
CLPDM
ID/EXP
WEN/FLD
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-B2. ∗ CLPOB also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-B2.
CXD3423GA
These timings can be switched by the serial interface data. ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
MODE
Applicable CCD image sensor • ICX434
Chart-B5 Horizontal Direction Timing Chart (High-speed sweep: C)
Frame mode
100 150 200 250 50
(1848) 0
HD
MCKO
56 188
H1
H2
56 84 112 140 168 196 224 252
V1A/B
70 98 126 154 182 210 238 266
V2
56 84 112 140 168 196 224 252
V3A/B
70 98 126 154 182 210 238 266
V4 #1
88 152
– 43 –
#2
#3
#4
SUB
PBLK
CLPOB
CLPDM
ID/EXP
WEN/FLD
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs). ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-B1. ∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H 1848ck (#758). ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
CXD3423GA
Chart-B6 Horizontal Direction Timing Chart
Frame mode
1027 1029 1071 1091 1131 1133 1175
MODE
Applicable CCD image sensor • ICX434
(1848) 0 56 72 88 104 120 136 152 168
(1848) 0
56 72 88 104 120 136 152 168 184 200 216
HD [A]
A Field
V1A
V1B
V2
V3A
V3B
V4 [B]
– 44 –
Logical alignment
B Field
V1A
V1B
V2
V3A
V3B
V4
CXD3423GA
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs). ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
Chart-B7 Horizontal Direction Timing Chart
Draft mode
• ICX434
MODE
Applicable CCD image sensor
1027 1029
1071
1091
1111
1131 1133
56 72 88 104 120 136 152 168
1175
(1848) 0 56 72 88 104 120 136 152 168
(1848) 0
HD [D]
V1A
V1B
V2
V3A
V3B
– 45 –
V4
∗ HD of this chart indicates the actual CXD3423GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximates (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs). ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
CXD3423GA
Chart-B8 Vertical Direction Sequence Chart
Draft → Frame → Draft
• ICX434
MODE
Applicable CCD image sensor
VD
V1A
V1B
V2
V3A
– 46 –
C D E B Close 000 000 1 050h 050h 1 000 1 050h 010 0 050h C D E
V3B
V4 F
SUB
A
B
CCD OUT
A
E Open 010 0 050h 000 1 050h
F
Mechanical shutter
MODE
000
000
000 1 050h
SMD
1
1
SHR
050h
050h
CXD3423GA
∗ This chart is a driving timing chart example of electronic shutter normal operation. ∗ Data exposed at D includes a blooming component. For details, see the CCD image sensor data sheet. ∗ The CXD3423GA does not generate the pulse to control mechanical shutter operation. ∗ The drive mode and the electronic shutter data are not switched at the same timing. ∗ This chart shows the pin configuration for the ICX434. (See page 3.)
Chart-Z
• ICX432/ICX434
High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
HD
HD'
CKI
CKO
ADCLK 56/52 188/644/888
1
MCKO
H1
– 47 –
H2
RG
XSHP
XSHD
∗ HD' indicates the HD which is the actual CXD3423GA load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data.
CXD3423GA
CXD3423GA
CCD Signal Processor Block Serial Interface Control The CXD3423GA's CCD signal processor block basically loads the CCD signal processor block serial interface data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the operation 6 ADCLKI clocks after that. CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode.
SSI2 SCK2 SEN2 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
There are five categories of CCD signal processor block serial interface data: standby control data, PGA gain setting data, OB clamp level setting data, input pulse polarity setting data, and output delay adjustment data. Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for each category and wait until the setting value has been reflected to operation 6 ADCKLI clocks after that, then transmit the next category. When the power supply is set to ON, be sure to initialize for transmitting all category data. The details of each data are described below. Standby Control Data Data D00 D01 to D03 D04 to D14 D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to "0". D01 to D03 CTG Data = 1
FIXED STB
— Standby control
Set to "all 0". Normal operation mode Standby mode
PGA Gain Setting Data Data D00 D01 to D03 Symbol TEST CTG Test code Category switching — PGA gain setting data Function Data = 0 Set to "0". D01 to D03 CTG Set to "all 0". See D06 to D15 GAIN. Data = 1
D04, FIXED D05 D06 to D15 GAIN
– 48 –
CXD3423GA
OB Clamp Level Setting Data Data D00 D01 to D03 D04 to D11 D12 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to "0". D01 to D03 CTG Data = 1
FIXED
—
Set to "all 0".
OBLVL
OB clamp level setting data
See D12 to D15 OBLVL.
Input Pulse Polarity Setting Data Data D00 D01 to D03 D04 to D12 D13 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to "0". D01 to D03 CTG Data = 1
FIXED
—
Set to "all 0".
POL
Input pulse polarity setting data
Set to "all 0".
Output Delay Adjustment Data Data D00 D01 to D03 D04 to D13 Symbol TEST CTG Test code Category switching Function Data = 0 Set to "0". D01 to D03 CTG Data = 1
FIXED
— Output delay adjustment data
Set to "all 0". See D14 and D15 ODL.
D14, ODL D15
– 49 –
CXD3423GA
Detailed Description of Each Data Shared data: D01 to D03 CTG [Category] Of the data provided to the CXD3423GA by the CCD signal processor block serial interface, the CXD3423GA loads D04 and subsequent data to each data register as shown in the table below according to the combination of D01 to D03 . D01 0 0 0 0 1 1 1 D02 0 0 1 1 0 0 1 D03 0 1 0 1 0 1 x Description of operation Loading to standby control data register Loading to PGA gain setting data register Loading to OB clamp level setting data register Loading to input pulse polarity setting data register Loading to output delay adjustment data register Access prohibited Access prohibited
Standby control data: D15 STB [Standby] The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor block is in standby mode, only the serial interface is valid. D15 0 1 Description of operation Normal operating mode Standby mode
PGA gain setting data: D06 to D15 GAIN [PGA gain] The CXD3423GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by using PGA gain setting data D06 to D15 GAIN. The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN. MSB D06 D07 D08 D09 0 ↓ 1 1 1 1 ↓ C D10 D11 D12 D13 0 0 0 0 ↓ 3 D14 1 LSB D15 1 → GAIN is expressed as 1C3h .
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting values are –6dB, 0dB, +20dB, +34dB and +42dB.
– 50 –
CXD3423GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp level] The CXD3423GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal processor block control data D12 to D15 OBLVL. The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL. MSB D12 D13 D14 0 1 ↓ 6 1 LSB D15 0 → OBLVL is expressed as 6h .
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values are 2LSB, 18LSB, 130LSB and 242LSB.
Output delay adjustment data: D14 and D15 ODL [Output delay] The CXD3423GA can adjust the output delay time of 12-bit digital output against rising of ADCLK by using output delay adjustment data D14 and D15 ODL. D14 0 0 1 1 D15 0 1 0 1 Description of operation Output delay is not added. Output delay addition 5ns (Typ.) Output delay addition 10ns (Typ.) Output delay addition 13ns (Typ.)
Note: In the case that the output delay is not added, the delay time is about 2 to 10ns.
– 51 –
Application Circuit Block Diagram
XSHPI XSHDI PBLKI CLPDMI CLPOBI XSHP
XSHD PBLK
CLPDM CLPOB ADCLK
ADCLKI
C7 0.1µF
C8 0.1µF
B7 A2 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 C1 D3 D2 D8 D9 D1 D10 E1 J2 K2 M2 N2 N9 M9 M8 N8 L8 D11 (MSB) CKO MCKO VD HD ID/EXP WEN/FLD RST SNCSL SSGSL Signal Processor Block A7
CCD ICX284/ICX432/ICX434 C9 D7 B3 D8 B2 B1 C3 C8 C2 C7 A1 C1 C2 C3 C4
CCDOUT
1µF CCDIN
F9 F8 F7 G3 G2
G9 G8 G7 H3 H2 H1
G1
C9 0.1µF
C6
1µF
390pF
390pF
240pF
H1 J8 J9 K8 N4 M5 M4 L6 N6 L4 M7 N5 N7 J1 K1 L1 H7 L3 A5 C4 B5 H2 RG V5A V5B V2 V3A V3B V4 SUB V1 V6 TG/CDS/PGA/ADC CXD3423GA
SSI1
SEN1
SCK1
SSI2
SEN2 OSCI
CKI
SCK2
OSCO
TEST1
TEST2
TEST3
TEST4
This is the block diagram indicating the connection relations between this IC and each circuit block, and not the actual circuit diagram. Regarding the concrete connection circuit example with the CCD image sensor, see the data sheet of the CCD image sensor.
CXD3423GA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
TEST5
– 52 –
L2 N1 M1 A4 B4 A3
Controller
CXD3423GA
Notes on Operation 1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins and CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either before or at the same time as the VH pin power supply is started up.
+15.0V
t1
20% 0V 20%
t2 t2 ≥ t1 –7.5V
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by initializing the serial data. 3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5 pins. Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. The difference in potential between the timing generator block VDD4, pin supply voltage 3 VDDc and the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2 VDDf and 3 VDDg should be 0.1V or less. 5. The timing generator block and CCD signal processor block ground pins should use a shared ground which is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4, VSS5 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5 and AVSS6 should be 0.1V or less. 6. Do not perform serial communication with the CCD signal processor block during the effective image period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which are used by the CCD signal processor block, use of the dedicated ports is recommended. When using these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the effects on picture quality before use. – 53 –
CXD3423GA
Package Outline
Unit: mm
0.2
SA 8.0
96PIN LFLGA
X
12.0
0.10MAX
SB
x4
(0.3)
(0.3)
0.5 A
0.8
96 -φ0.45 ± 0.05 φ0.08 M S A B
DETAIL X
N M L K J H G F E D C B A
0.9
B
0.9
0.5 (0.3)
12 3 4 5 6 7 8 9 0.8 0.5
LFLGA-96P-02
(0.3) 0.5
1.2
0.8
3 – φ0.50
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE
SONY CODE EIAJ CODE JEDEC CODE
TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.3g
P-LFLGA96-12X8-0.8
S
0.15
0.2
0.2
S
0.10 S
Sony Corporation
PIN 1 INDEX
1.3 MAX
– 54 –
工商网监
湘ICP备2023018690号
