FXL3SD206UMX

FXL3SD206 — Level Shifting Voltage Translator March 2009 FXL3SD206 Level Shifting Voltage Translator Two-Port SDIO MUX/DEMUX with Three Configurable Power Supplies for SDIO Device Port Expansion Features Bi-Directional Interface between Two Levels: 1.65 to 3.6V Fully Configurable: Inputs and Outputs Track VDD Flexible and Programmable VDD of B and C Ports Non-Preferential Power-up; either VDD Can Power Up First Output Remains in 3-State until Active VDD Level is Reached Output Switches to 3-state if either VDD is at GND Power-off Protection Bus-Hold on Data Input Eliminates the Need for SDIO Pull-up Resistors 2:1 MUX/DEMUX of SDIO Devices in 24-Terminal Micro-MLP Package (2.5mm x 3.4mm) Direction Control is Automatic Power Switching Time (VDD_HI to VDD_LO or Reverse) is Less than 1.7µs 60Mbps Throughput ESD Protection Exceeds: 12KV HBM (A, B, and C port I/O to GND) (per JESD22-A114) 1KV CDM (per ESD STM5.3) Description FXL3SD206 is a voltage translator with multiplexing and de-multiplexing functions for SDIO devices. It is designed for voltage translation over a wide range of input and output levels, from 1.65V to 3.6V. The multiplexing/de-multiplexing function of this device allows expansion of a host SDIO interface to two SDIO peripheral devices. When selected, each SDIO peripheral can communicate with the host through the same host interface. An alternative application allows two host devices to interface with a single SDIO peripheral. Port A is intended to connect to a host device and the voltage level tracks the VDDA. Ports B and C are intended to connect to peripheral devices. Peripheral I/O voltage levels track either VDD_HI or VDD_LO as determined by the VDD_SEL pin. During normal operation, VDD_HI must be greater than or equal to VDD_LO. The CH_SEL, VDD_SEL, and OE pins are referenced to VDD_CON. Channel communication from either Port A to Port B or Port A to Port C is controlled by the CH_SEL pin. The selected channel remains in 3-state until the VDD of each side reaches an active level and the OE pin reaches a valid high. Internal power-down circuitry places the selected channel of the device in 3-state if either side VDD removed. The direction of data is controlled automatically by the device. No direction control pin is required. The device senses input signals on any port automatically and transfers the data to the corresponding output. Applications SDIO Devices Cell Phone, PDA, Digital Camera, Portable GPS Ordering Information Part Number FXL3SD206UMX Operating Temperature Range -40 to +85°C Eco Status Green Package 24-Pin, Micro-MLP, Quad, .6mm Thick, 2.5mm x 3.4mm Body Packing Method Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com FXL3SD206 — Level Shifting Voltage Translator Application Diagrams Power Management IC VDDA VDD_CON VDD_HI VDD Select Card Select HOST VDD_SEL CH_SEL In MUX Out In VDD_LO VDD_HI SD Card 1CLK CMD_B CMD B 1D0~D3 VDD_LO SDIO Device W iFi LAN / Bluetooth / Memory Module CMD Output Enable CMD_ A OE Out DEMUX In Out 2CLK CMD_C CMD C 2D0~D3 CLK D0~D3 CLK_A D0_A~D3_A CLK_BC D0_BC~D3_BC Figure 1. Single Host to Two SDIO Application Diagram Power Management IC VDDA VDD_CON VDD SEL OE CH SEL VDD_LO VDD_HI VDD Select Output Enable Card Select SD Memory Or SDIO Device CMD CMD A 1CLK In MUX Out In VDD_HI CMD B CMD B 1D0~D3 Application Processor Out In DEMUX Out 2CLK CMD C VDD_LO Baseband Processor CMD C 2D0~D3 CLK D0~D3 CLK_A D0_A~D3_A CLK_BC D0_BC~D3_BC Figure 2. Dual Host to Single SDIO Application © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 2 FXL3SD206 — Level Shifting Voltage Translator Pin Configuration 18 19 13 12 24 1 6 7 Figure 3. Pin Configuration (Top Through View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name D0_A D1_A D2_A D3_A CLK_A ---CMD_A ---GND CMD_C ---CMD_B CLK_BC D3_BC D2_BC D1_BC D0_BC VDD_LO VDD_HI VDD_CON VDDA VDD_SEL CH_SEL OE Type Data Data Data Data Data NC Data NC Power Data NC Data Data Data Data Data Data Power Power Power Power Control Control Control Description Data Pin of A Port Data Pin of A Port Data Pin of A Port Data Pin of A Port Clock Pin of A Port No Connect Command Pin of A Port No Connect Ground Command Pin of C Port No Connect Command Pin of B Port Clock Pin of B or C Port Data Pin of B or C Port Data Pin of B or C Port Data Pin of B or C Port Data Pin of B or C Port B or C Port, Low Power Supply B or C Port, High Power Supply Control Pin Power Supply A-Port Power Supply Power Supply Select Pin of B and C Ports Channel Select Pin Output Enable Pin © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 3 FXL3SD206 — Level Shifting Voltage Translator Function Diagram Figure 4. Function Diagram Function Table OE LOW HIGH HIGH HIGH HIGH CH_SEL Don’t Care HIGH HIGH LOW LOW VDD_SEL Don’t Care HIGH LOW HIGH LOW 3-State Output Normal operation; Port A to Port B channel selected; Port B tracks VDD_HI level Normal operation; Port A to Port B channel selected; Port B tracks VDD_LO level Normal operation; Port A to Port C channel selected; Port C tracks VDD_HI level Normal operation; Port A to Port C channel selected; Port C tracks VDD_LO level Note: 1. VDD_CON: This is a power supply pin that is used by the three control pins (VDD_SEL, CH_SEL, and OE). In single host mode, VDD_CON should be tied to the same supply as the VDDA pin. In dual host mode, VDD_CON should be tied to the same supply as either the VDD_HI or the VDD_LO pin, depending upon which host is used to drive the control pins. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 4 FXL3SD206 — Level Shifting Voltage Translator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VI Parameter Supply Voltage DC Input Voltage Conditions VDDA, VDD_HI, VDD_LO, VDD_CON Data Ports A, B, and C Control Inputs (OE, CH_SEL, VDD_SEL) Output 3-State Output Active (Port A) Output Active (Port B or C) Output Active (Port B or C) VI