FXL3SD206UMX

FXL3SD206 Level Shifting Voltage Translator Two-Port SDIO MUX/DEMUX with Three Configurable Power Supplies for SDIO Device Port Expansion Features ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Description Bi-Directional Interface between Two Levels: 1.65 to 3.6V Fully Configurable: Inputs and Outputs Track VDD Flexible and Programmable VDD of B and C Ports Non-Preferential Power-up; either VDD Can Power Up First Output Remains in 3-State until Active VDD Level is Reached Output Switches to 3-state if either VDD is at GND Power-off Protection Bus-Hold on Data Input Eliminates the Need for SDIO Pull-up Resistors 2:1 MUX/DEMUX of SDIO Devices in 24-Terminal Micro-MLP Package (2.5mm x 3.4mm) Direction Control is Automatic Power Switching Time (VDD_HI to VDD_LO or Reverse) is Less than 1.7µs 60Mbps Throughput ESD Protection Exceeds: ‚ 12KV HBM (A, B, and C port I/O to GND) (per JESD22-A114) ‚ 1KV CDM (per ESD STM5.3) Applications ƒ ƒ SDIO Devices Cell Phone, PDA, Digital Camera, Portable GPS FXL3SD206 is a voltage translator with multiplexing and de-multiplexing functions for SDIO devices. It is designed for voltage translation over a wide range of input and output levels, from 1.65V to 3.6V. The multiplexing/de-multiplexing function of this device allows expansion of a host SDIO interface to two SDIO peripheral devices. When selected, each SDIO peripheral can communicate with the host through the same host interface. An alternative application allows two host devices to interface with a single SDIO peripheral. FXL3SD206 — Level Shifting Voltage Translator March 2009 Port A is intended to connect to a host device and the voltage level tracks the VDDA. Ports B and C are intended to connect to peripheral devices. Peripheral I/O voltage levels track either VDD_HI or VDD_LO as determined by the VDD_SEL pin. During normal operation, VDD_HI must be greater than or equal to VDD_LO. The CH_SEL, VDD_SEL, and OE pins are referenced to VDD_CON. Channel communication from either Port A to Port B or Port A to Port C is controlled by the CH_SEL pin. The selected channel remains in 3-state until the VDD of each side reaches an active level and the OE pin reaches a valid high. Internal power-down circuitry places the selected channel of the device in 3-state if either side VDD removed. The direction of data is controlled automatically by the device. No direction control pin is required. The device senses input signals on any port automatically and transfers the data to the corresponding output. Ordering Information Part Number Operating Temperature Range Eco Status FXL3SD206UMX -40 to +85°C Green Package 24-Pin, Micro-MLP, Quad, .6mm Thick, 2.5mm x 3.4mm Body Packing Method Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com Power Management IC VDDA VDD_CON VDD_LO VDD_HI VDD_HI SD Card VDD Select Card Select VDD_SEL 1CLK CH_SEL HOST In MUX CMD B CMD_B 1D0~D3 Out CMD Output Enable In CMD_ A Out DEMUX In OE D0~D3 CMD C 2D0~D3 CMD_C Out CLK_A CLK 2CLK VDD_LO SDIO Device WiFi LAN / Bluetooth / Memory Module CLK_BC D0_A~D3_A FXL3SD206 — Level Shifting Voltage Translator Application Diagrams D0_BC~D3_BC Figure 1. Single Host to Two SDIO Application Diagram Power Management IC VDD_LO VDDA VDD_CON VDD SEL OE CH SEL VDD Select Output Enable Card Select 1CLK SD Memory Or VDD_HI In MUX CMD CMD B Out CMD B 1D0~D3 VDD_HI Application Processor In CMD A SDIO Device 2CLK Out In DEMUX Out CLK CLK_A D0~D3 D0_A~D3_A CMD C CMD C 2D0~D3 VDD_LO Baseband Processor CLK_BC D0_BC~D3_BC Figure 2. Dual Host to Single SDIO Application © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 2 13 18 19 12 24 7 1 6 Figure 3. Pin Configuration (Top Through View) Pin Definitions Pin # Name Type Description 1 D0_A Data Data Pin of A Port 2 D1_A Data Data Pin of A Port 3 D2_A Data Data Pin of A Port 4 D3_A Data Data Pin of A Port 5 CLK_A Data Clock Pin of A Port 6 ---- NC 7 CMD_A Data 8 ---- NC 9 GND Power 10 CMD_C Data 11 ---- NC 12 CMD_B Data Command Pin of B Port 13 CLK_BC Data Clock Pin of B or C Port 14 D3_BC Data Data Pin of B or C Port 15 D2_BC Data Data Pin of B or C Port 16 D1_BC Data Data Pin of B or C Port Data Pin of B or C Port No Connect Command Pin of A Port No Connect Ground Command Pin of C Port No Connect 17 D0_BC Data 18 VDD_LO Power B or C Port, Low Power Supply 19 VDD_HI Power B or C Port, High Power Supply 20 VDD_CON Power Control Pin Power Supply 21 VDDA Power A-Port Power Supply 22 VDD_SEL Control Power Supply Select Pin of B and C Ports 23 CH_SEL Control Channel Select Pin 24 OE Control Output Enable Pin © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 FXL3SD206 — Level Shifting Voltage Translator Pin Configuration www.fairchildsemi.com 3 FXL3SD206 — Level Shifting Voltage Translator Function Diagram Figure 4. Function Diagram Function Table OE CH_SEL VDD_SEL Output LOW Don’t Care Don’t Care HIGH HIGH HIGH Normal operation; Port A to Port B channel selected; Port B tracks VDD_HI level HIGH HIGH LOW Normal operation; Port A to Port B channel selected; Port B tracks VDD_LO level HIGH LOW HIGH Normal operation; Port A to Port C channel selected; Port C tracks VDD_HI level HIGH LOW LOW Normal operation; Port A to Port C channel selected; Port C tracks VDD_LO level 3-State Note: 1. VDD_CON: This is a power supply pin that is used by the three control pins (VDD_SEL, CH_SEL, and OE). In single host mode, VDD_CON should be tied to the same supply as the VDDA pin. In dual host mode, VDD_CON should be tied to the same supply as either the VDD_HI or the VDD_LO pin, depending upon which host is used to drive the control pins. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VI VO Parameter Supply Voltage DC Input Voltage Output Voltage (2) IIK DC Input Diode Current IOK DC Output Diode Current IOH/IOL IDD TSTG Conditions VDDA, VDD_HI, VDD_LO, VDD_CON Min. Max. Unit -0.5 4.6 V Data Ports A, B, and C -0.5 4.6 V Control Inputs (OE, CH_SEL, VDD_SEL) -0.5 4.6 V Output 3-State -0.5 4.6 Output Active (Port A) -0.5 VDDA+0.5 Output Active (Port B or C) -0.5 VDD_HI+0.5 Output Active (Port B or C) -0.5 VDD_LO+0.5 VI