SI4539

Si4539DY January 2001 Si4539DY Dual N & P-Channel Enhancement Mode Field Effect Transistor General Description These dual N- and P -Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features N-Channel 7.0 A,30 V, RDS(ON)=0.028 Ω @ VGS=10 V RDS(ON)=0.040 Ω @ VGS= 4.5 V. P-Channel -5.0 A,-30 V,RDS(ON)=0.052 Ω @ VGS=-10 V RDS(ON)=0.080Ω @ VGS=-4.5 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual (N & P-Channel) MOSFET in surface mount package. SOT-23 TM SuperSOT -6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D2 D1 D1 D2 5 4 3 2 1 39 45 S2 G2 6 7 8 SO-8 pin 1 S1 G1 Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed PD T A = 25°C unless otherwise noted N-Channel 30 20 (Note 1a) P-Channel -30 -20 -5 -20 2 Units V V A 7 20 Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) W 1.6 1 0.9 -55 to 150 °C TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 40 °C/W °C/W © 2001 Fairchild Semiconductor International Si4539DY Rev. A Si4539DY Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Type Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA ID = 250 µA, Referenced to 25 oC ID = -250 µA, Referenced to 25 oC IDSS IGSSF IGSSR VGS(th) Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V VDS = -24 V, VGS = 0 V Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS = 0 V VDS = VGS, ID = 250 µA VDS = VGS, ID = -250 µA ID = 250 µA, Referenced to 25 C ID = -250 µA, Referenced to 25 C RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 7.0 A VGS = 4.5 V, ID = 6.0 A VGS = -10 V, ID = -5.0 A VGS = -4.5 V, ID = - 4.0 A ID(on) gFS On-State Drain Current VGS = 10 V, VDS = 5 V VGS = -10 V, VDS = -5 V Forward Transconductance VDS = 5 V, I D = -7 A VDS = -5 V, I D = -5 A DYNAMIC CHARACTERISTICS Ciss Coss Crss Input Capacitance VDS = 15 V, VGS = 0 V, f = 1.0 MHz N-Ch P-Ch N-Ch VDS = -15 V, VGS = 0 V, f = 1.0 MHz P-Ch N-Ch P-Ch 650 730 345 400 90 90 pF pF pF N-Ch P-Ch N-Ch P-Ch 20 -20 15 8 S S P-Ch o o N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch All All 30 -30 30 -25 1 -1 100 -100 V V mV/oC ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient µA µA nA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage N-Ch P-Ch N-Ch P-Ch N-Ch 1 -1 1.7 -1.5 -4.4 3.2 0.024 0.035 0.044 0.068 0.028 0.04 0.052 0.08 A 3 -3 V V mV/oC ∆VGS(th)/∆TJ Gate Threshold Voltage Temp. Coefficient Ω Input Capacitance Reverse Transfer Capacitance Si4539DY Rev. A Si4539DY Electrical Characteristics (continued) SWITCHING CHARACTERISTICS Symbol tD(on) Parameter Turn - On Delay Time (Note 2) Conditions VDS = 10 V, I D = 1 A VGS = 10 V , RGEN = 6 Ω Type N-Ch P-Ch N-Ch P-Ch Min Typ 8 11 14 10 23 90 9 55 18 19 3.2 3.5 4.3 3.6 Max 16 20 25 18 37 125 18 80 26 27 Units ns tr tD(off) Turn - On Rise Time ns Turn - Off Delay Time VDS = -10 V, I D = -1 A VGS = -10 V , RGEN = 6 Ω N-Ch P-Ch N-Ch P-Ch ns tf Qg Qgs Qgd Turn - Off Fall Time ns Total Gate Charge VDS = 10 V, I D = 7 A, VGS = 10 V N-Ch P-Ch N-Ch nC Gate-Source Charge VDS = -10 V, I D = -5 A, Gate-Drain Charge VGS = -10 V nC P-Ch N-Ch P-Ch nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Maximum Continuous Drain-Source Diode Forward Current N-Ch P-Ch 1.3 -1.3 0.75 -0.75 1.2 -1.2 A A V V Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A VGS = 0 V, IS = -1.3 A (Note 2) (Note 2) N-Ch P-Ch a. 78OC/W on a 0.5 in2 pad of 2oz copper. b. 125OC/W on a 0.02 in2 pad of 2oz copper. c. 135OC/W on a 0.003 in2 pad of 2oz copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.. Si4539DY Rev. A Si4539DY Typical Electrical Characteristics: N-Channel 30 ID , DRAIN-SOURCE CURRENT (A) 2.4 5.5V R DS(ON) , NORMALIZED 24 4.5V DRAIN-SOURCE ON-RESISTANCE VGS = 10V 2 18 4.0V VGS = 4.0V 1.6 4.5 V 5.0V 6.0 V 7.0V 10V 12 3.5V 6 1.2 3.0V 0 0 1 2 3 4 5 0.8 0 6 12 18 24 30 VDS , DRAIN-SOURCE VOLTAGE (V) I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 DRAIN-SOURCE ON-RESISTANCE 0.15 I D = 7A 1.6 1.4 1.2 1 0.8 0.6 -50 I D = 3A R DS(ON) , ON-RESISTANCE (OHM) V GS = 10V 0.12 R DS(ON) , NORMALIZED 0.09 0.06 TA = 125°C 0.03 TA = 25°C 0 2 4 6 8 10 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) J 125 150 V GS , GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. V DS = 10V ID , DRAIN CURRENT (A) 25 20 15 10 I S , REVERSE DRAIN CURRENT (A) 30 20 VGS = 0V TJ = 125°C 1 25°C 0.1 -55°C 0.01 T = 125°C J 5 25°C -55°C 0.001 0 0.0001 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. Si4539DY Rev. A Si4539DY Typical Electrical Characteristics: N-Channel (continued) 10 V GS , GATE-SOURCE VOLTAGE (V) 2000 I D = 7A 8 VDS = 5V CAPACITANCE (pF) 1200 10V 15V 800 Css i Coss 6 400 4 200 2 100 f = 1 MHz VGS = 0 V 0.2 0.5 1 2 5 Crss 0 0 2 4 6 8 10 12 Q g , GATE CHARGE (nC) 50 0.1 10 30 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 50 30 I D , DRAIN CURRENT (A) 10 5 2 1 0.5 MIT ) LI (ON DS R 100 1m s 10m s 10 0m s 1s 30 us 25 20 15 10 5 0 0.01 SINGLE PULSE RθJA =135 °C/W TA = 25°C 0.1 0.05 VGS =10V SINGLE PULSE R θJA= 135° C/W T A = 25°C A 0.2 0.5 V DS 10s DC POWER (W) 0.01 0.1 0.1 0.5 10 50 100 300 1 2 5 10 30 50 SINGLE PULSE TIME (SEC) , DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. Si4539DY Rev. A Si4539DY Typical Electrical Characteristics: P-Channel -I D , DRAIN-SOURCE CURRENT (A) DRAIN-SOURCE ON-RESISTANCE 30 2.4 R DS(ON), NORMALIZED 24 VGS = -10V -7.0V -5.5V - 5.0V -4.5V -4.0V 2 VGS = - 3.5V -4.0 V 18 1.6 -4.5 V -5.0 V 1.2 12 -3.5V -3.0V -6.0V -8.0V -10V 6 0 0.8 0 1 2 3 4 5 6 - VDS , DRAIN-SOURCE VOLTAGE (V) 0 5 10 - ID , DRAIN CURRENT (A) 15 20 Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 DRAIN-SOURCE ON-RESISTANCE 1.6 1.4 1.2 1 0.8 0.6 -50 0.2 V GS = 10V R DS(ON) , ON-RESISTANCE (OHM) I D = 5A I D = -2.0A 0.15 R DS(ON) , NORMALIZED 0.1 125°C 0.05 25°C 0 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) J 125 150 0 2 4 6 8 10 -VGS , GATE TO SOURCE VOLTAGE (V) Figure 13. On-Resistance Variation with Temperature. Figure 14. On-Resistance Variation with Gate-to-Source Voltage. V DS = -5V - ID , DRAIN CURRENT (A) 40 -IS , REVERSE DRAIN CURRENT (A) 50 60 10 1 0.1 T = -55°C J VGS = 0V 25°C 125°C TJ = 125°C 25°C -55°C 30 20 0.01 0.001 0.0001 10 0 0 2 -V GS 4 6 8 , GATE TO SOURCE VOLTAGE (V) 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 15. Transfer Characteristics. Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature. Si4539DY Rev. A Si4539DY Typical Electrical Characteristics: P-Channel (continued) 10 -VGS , GATE-SOURCE VOLTAGE (V) 2000 I D = -5A 8 CAPACITANCE (pF) VDS = -5V -10V -15V 1000 Ciss 500 6 Coss 4 200 C ss r 100 2 f = 1 MHz VGS = 0 V 0.3 1 3 10 30 0 0 2 4 6 8 10 12 Q g , GATE CHARGE (nC) 50 0.1 -VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 17. Gate Charge Characteristics. Figure 18. Capacitance Characteristics. 100 30 100 -ID, DRAIN CURRENT (A) 10 T IMI )L (ON DS R 1m 10m us POWER (W) 25 20 15 10 5 0 0.01 s SINGLE PULSE RθJA =135 °C/W TA = 25°C s 10 1 0m 0.1 VGS = -10V SINGLE PULSE R θJA = 135°C/W TA A = 25°C 0.2 0.5 1 2 1s 10s DC s 0.01 0.1 0.1 0.5 10 50 100 300 5 10 20 50 SINGLE PULSE TIME (SEC) -VDS , DRAIN-SOURCE VOLTAGE (V) Figure 19. Maximum Safe Operating Area. Figure 20. Single Pulse Maximum Power Dissipation. Si4539DY Rev. A Si4539DY Typical Thermal Characteristics: N & P-Channel (continued) 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 0.001 0.01 0.1 t1 , TIME (sec) 1 10 D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE R θJA (t) = r(t) * R θJA R θJA =135°C/W t1 t2 TJ - TA = P * R JA (t) θ Duty Cycle, D = t1 /t2 100 300 Figure 21. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1. Transient thermalresponse will change depending on the circuit board design. Si4539DY Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  DISCLAIMER FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. G