ESD8106MUTAG

ESD8106 Product Preview Transient Voltage Suppressors Low Capacitance ESD Protection for USB 3.0 Interface http://onsemi.com The ESD8106 transient voltage suppressor is specifically designed to protect USB 3.0 interfaces by integrating two Superspeed pairs, D+ and D− lines into a single protection product. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines. MARKING DIAGRAM 14 1 XXM G UDFN14 CASE 517CQ XX = Specific Device Code M = Date Code G = Pb−Free Package Features • Low Capacitance (0.35 pF Max, I/O to GND) • Protection for the Following IEC Standards: • • ORDERING INFORMATION IEC 61000−4−2 Level 4 UL Flammability Rating of 94 V−0 These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • USB 3.0 Device ESD8106MUTAG Package Shipping UDFN14 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD ESD ±15 ±15 kV kV IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. See Application Note AND8308/D for further description of survivability specs. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. P1 1 Publication Order Number: ESD8106/D ESD8106 Pin 8 Pin 9 Pin 11 Pin 12 Pin 13 Pin 14 Pins 5, 10 Note: Common GND – Only minimum of 1 GND connection required = Figure 1. Pin Schematic ESD8106 I/O I/O I/O I/O GND I/O I/O Figure 2. Pin Configuration Note: Pins 5, 10 are connected internally as a common ground. Pins 1, 2, 3, 4, 6, and 7 are not internally connected but should be connected to the opposite pin with PCB trace in order to maintain a flow through routing scheme. http://onsemi.com 2 ESD8106 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IPP Parameter IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VRWM RDYN Working Peak Reverse Voltage IR VCL VBR VRWM Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT VCL RDYN Test Current RDYN V IR IT Dynamic Resistance *See Application Note AND8308/D for detailed explanations of datasheet parameters. IPP Uni−Directional TVS ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions IT = 1 mA, I/O Pin to GND 4.0 IR VRWM = 3.3 V, I/O Pin to GND Clamping Voltage (Note 1) VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 2) See Figures 7 through 10 VC IPP = 8 A IPP = −8 A Junction Capacitance CJ Max Unit 3.3 V 1.0 mA 5.0 V See Figures 3 and 4 V 8.5 −4.5 V IEC 61000−4−2 Level 2 equivalent (±4 kV Contact, ±4 kV Air) IPP = 16 A IPP = −16 A RDYN Typ I/O Pin to GND Reverse Leakage Current Dynamic Resistance Min 11.4 −8.0 IEC 61000−4−2 Level 4 equivalent (±8 kV Contact, ±15 kV Air) I/O Pin to GND GND to I/O Pin 0.36 0.44 VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 1 MHz between I/O Pins VR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins and GND 0.30 0.15 0.37 W 0.35 0.20 0.45 pF 90 10 80 0 70 −10 60 −20 VOLTAGE (V) VOLTAGE (V) 1. For test procedure see Figures 5 and 6 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 50 40 30 20 −30 −40 −50 −60 10 −70 0 −80 −10 −20 0 20 40 60 80 100 120 −90 −20 140 0 20 40 60 80 100 120 TIME (ns) TIME (ns) Figure 3. IEC61000−4−2 +8 kV Contact Clamping Voltage Figure 4. IEC61000−4−2 −8 kV Contact Clamping Voltage http://onsemi.com 3 140 ESD8106 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 6. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger http://onsemi.com 4 ESD8106 20 −20 10 EQUIVALENT VIEC (kV) 8 −14 14 TLP CURRENT (A) −16 EQUIVALENT VIEC (kV) TLP CURRENT (A) 8 16 6 12 −12 6 −10 10 4 8 6 2 4 −8 4 −6 −4 2 −2 2 0 0 10 −18 18 2 4 6 8 10 12 14 VC, VOLTAGE (V) 16 18 0 0 20 0 2 Figure 7. Positive TLP I−V Curve NOTE: 4 6 8 10 12 14 VC, VOLTAGE (V) 16 0 20 18 Figure 8. Negative TLP I−V Curve TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 9. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 10 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 9. Simplified Schematic of a Typical TLP System Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms http://onsemi.com 5 ESD8106 TBD TBD Without ESD With ESD8106 Figure 11. USB 3.0 Eye Diagram with and without ESD8106. 5.0 Gb/s, 400 mVPP Interface Data Rate (Gb/s) Fundamental Frequency (GHz) 3rd Harmonic Frequency (GHz) USB 3.0 5 2.5 (m1) 7.5 (m2) Figure 12. ESD8106 Insertion Loss http://onsemi.com 6 ESD8106 Insertion Loss (dB) m1 = 0.128 m2 = 0.659 ESD8106 USB 3.0 Type A Connector StdA_SSTX+ Vbus ESD8106 StdA_SSTX− D− GND_DRAIN D+ StdA_SSRX+ GND StdA_SSRX− Figure 13. USB 3.0 Layout Diagram http://onsemi.com 7 ESD8106 • Make sure to use differential design methodology and PCB Layout Guidelines Steps must be taken for proper placement and signal trace routing of the ESD protection device in order to ensure the maximum ESD survivability and signal integrity for the application. Such steps are listed below. • Place the ESD protection device as close as possible to the I/O connector to reduce the ESD path to ground and improve the protection performance. ♦ In USB 3.0 applications, the ESD protection device should be placed between the AC coupling capacitors and the I/O connector on the TX differential lanes as shown in Figure 14. impedance matching of all high speed signal traces. ♦ Use curved traces when possible to avoid unwanted reflections. ♦ Keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ♦ Place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. Figure 14. USB 3.0 Connection Diagram http://onsemi.com 8 ESD8106 ESD Protection Device Technology ON Semiconductor’s portfolio contains three main technologies for low capacitance ESD protection device which are highlighted below and in Figure 15. • ESD7000 series: Zener diode based technology. This technology has a higher breakdown voltage (VBR) limiting it to protecting chipsets with larger geometries. • ESD8000 series: Silicon controlled rectifier (SCR) type technology. The key advatange for this technology is a low holding voltage (VH) which produces a deeper snapback that results in lower voltage over high • currents as shown in the TLP results in Figure 16. This technology provides optimized protection for chipsets with small geometries against thermal failures resulting in chipset damage (also known as “hard failures”). ESD8100 series: Low voltage punch through (LVPT) technology. The key advatange for this technology is a very low turn-on voltage as shown in Figure 17. This technology provides optimized protection for chipsets with small geometries against recoverable failures due to voltage peaks (also known as “soft failures”). Figure 15. ON Semiconductor’s Low-cap ESD Technology Portfolio 10 20 18 TLP Current (A) 14 6 12 10 4 8 ESD8004 6 ESD8106 4 2 ESD7004 2 0 0 2 4 6 8 10 12 14 16 18 Vc (V) Figure 16. High Current, TLP, IV Characteristic of Each Technology http://onsemi.com 9 0 20 Equivalent VIEC (kV) 8 16 ESD8106 1.00E−01 1.00E−02 ESD8004 1.00E−03 ESD8106 1.00E−04 ESD7004 I (A) 1.00E−05 1.00E−06 1.00E−07 1.00E−08 1.00E−09 1.00E−10 1.00E−11 0 1 2 3 4 5 6 7 V (V) Figure 17. Low Current, DC, IV Characteristic of Each Technology http://onsemi.com 10 8 ESD8106 PACKAGE DIMENSIONS UDFN14, 3.5x1.35, 0.5P CASE 517CQ ISSUE O PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C É É L1 E DETAIL A OPTIONAL TERMINAL CONSTRUCTIONS TOP VIEW A DETAIL B 0.10 C 14X (A3) A1 C SIDE VIEW 2X 1 L2 b2 7 14X MOLD CMPD DETAIL B SEATING PLANE OPTIONAL CONSTRUCTION 8 e BOTTOM VIEW 12X 14X 0.62 0.25 b 0.10 C A B 0.05 C MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 0.35 0.45 3.50 BSC 1.35 BSC 0.50 BSC 0.30 0.50 0.00 0.15 0.20 REF RECOMMENDED SOLDERING FOOTPRINT* L 11X 14 DIM A A1 A3 b b2 D E e L L1 L2 ÉÉÉ ÉÉÉ ÇÇÇ EXPOSED Cu 0.08 C DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 MM FROM THE TERMINAL TIP. L L A B D 1.55 NOTE 3 1 3X 0.45 0.50 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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