ESD7016MUTAG

ESD7016, SZESD7016 ESD Protection Diode Low Capacitance, USB 3.0 The ESD7016 surge protection is specifically designed to protect USB3.0 interfaces by integrating two Superspeed pairs, D+, D−, and Vbus lines into a single protection product. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines. • Low Capacitance (0.15 pF Typical, I/O to GND) • Protection for the Following IEC Standards: • MARKING DIAGRAM UDFN8 CASE 517CB 6M MG G 1 Features • • www.onsemi.com IEC 61000−4−2 (Level 4) Low ESD Clamping Voltage SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable This is a Pb−Free Device 6M = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN CONFIGURATION AND SCHEMATIC I/O 1 Typical Applications I/O 2 • USB 3.0 N/C Vbus or Ground I/O 3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) I/O 4 Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C I/O 5 Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C I/O 6 ESD ESD ±15 ±15 kV kV IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. N/C ORDERING INFORMATION Device Package Shipping ESD7016MUTAG UDFN8 (Pb−Free) 3000 / Tape & Reel SZESD7016MUTAG UDFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2013 October, 2017 − Rev. 4 1 Publication Order Number: ESD7016/D ESD7016, SZESD7016 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions VRWM Breakdown Voltage Min Typ Max Unit 5.0 V I/O Pin to GND VBR IT = 1 mA, I/O Pin to GND 5.5 V Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 1.0 mA Clamping Voltage (Note 1) VC IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) 10 V Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 3) See Figures 6 through 9 VC IPP = ±8 A IPP = ±16 A 14.6 20.5 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.15 Junction Capacitance Difference DCJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.03 See Figures 1 and 2 V 0.20 pF pF 1. Surge current waveform per Figure 5. 2. For test procedure see Figures 3 and 4 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 80 0 70 −10 60 −20 VOLTAGE (V) VOLTAGE (V) 90 50 40 30 20 −30 −40 −50 −60 −70 10 −80 0 −90 −10 −20 0 20 40 60 80 100 120 −100 −20 140 0 20 40 60 80 100 120 TIME (ns) TIME (ns) Figure 1. IEC61000−4−2 +8 KV Contact Clamping Voltage Figure 2. IEC61000−4−2 −8 KV Contact Clamping Voltage www.onsemi.com 2 140 ESD7016, SZESD7016 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Device ESD Gun Under Oscilloscope Test 50 W 50 W Cable Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D and AND8308/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 x 20 ms Pulse Waveform www.onsemi.com 3 80 22 −22 20 −20 18 −18 16 −16 CURRENT (A) CURRENT (A) ESD7016, SZESD7016 14 12 10 8 −14 −12 −10 −8 6 −6 4 −4 2 −2 0 0 2 4 6 8 0 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24 26 VOLTAGE (V) VOLTAGE (V) Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 8. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 9 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 8. Simplified Schematic of a Typical TLP System Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4 ESD7016, SZESD7016 Without ESD7016 With ESD7016 Figure 10. USB3.0 Eye Diagram with and without ESD7016, 5 Gb/s S21 INSERTION LOSS (dB) 4 2 ESD7016 IO−GND 0 −2 −4 −6 −8 −10 1.E+06 1.E+07 1.E+08 1.E+09 FREQUENCY (Hz) Figure 11. ESD7016 Insertion Loss www.onsemi.com 5 1.E+10 ESD7016, SZESD7016 I/O Pin 1 I/O Pin 2 I/O Pin 4 I/O Pin 5 I/O Pin 7 I/O Pin 8 Pinout Option 1: 2 Ground connections between high speed pairs to minimize crosstalk. USB 3.0 Type A Connector StdA_SSTX+ Vbus StdA_SSTX− D− GND Pin 3 GND_DRAIN GND Pin 6 D+ StdA_SSRX+ = GND StdA_SSRX− I/O Pin 1 I/O Pin 2 VBUS Pin 3 I/O Pin 4 I/O Pin 5 I/O Pin 7 I/O Pin 8 Pinout Option 2: Single ground connection and Vbus protection for fully integrated solution. USB 3.0 Type A Connector StdA_SSTX+ Vbus StdA_SSTX− Vbus D− GND_DRAIN GND Pin 6 D+ StdA_SSRX+ = GND StdA_SSRX− Figure 12. USB3.0 Type A Connector Layout Diagrams www.onsemi.com 6 ESD7016, SZESD7016 USB 3.0 Micro B Connector Vbus ESD9X D− D+ ID GND ESD7016 N/C ID N/C MicB_SSTX− MicB_SSTX+ GND_DRAIN MicB_SSRX− MicB_SSRX+ Figure 13. USB3.0 Micro B Connector Layout Diagram www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN8, 3.3x1.0, 0.4P CASE 517CB ISSUE O 1 SCALE 4:1 PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ 0.10 C 2X L1 DETAIL A E ALTERNATE CONSTRUCTIONS ÉÉÉ ÇÇÇ TOP VIEW EXPOSED Cu A DETAIL B 0.05 C (A3) MOLD CMPD DETAIL B 0.05 C A1 SIDE VIEW 8X DETAIL A 1 e/2 e 7X b 0.10 M C A B 0.05 M C NOTE 3 G2 BOTTOM VIEW 0.10 M C A B 0.05 M C 1.66 2X DIM A A1 A3 b D D2 E E2 e G2 L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 3.30 BSC 0.25 0.45 1.00 BSC 0.45 0.55 0.40 BSC 1.19 BSC 0.20 0.30 −−− 0.15 0.30 0.40 GENERIC MARKING DIAGRAM* XX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) RECOMMENDED SOLDERING FOOTPRINT* *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 2X 0.65 0.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. XX MG G L D2 2X E2 ALTERNATE CONSTRUCTION SEATING PLANE C 8 L2 2X L L A B D DATE 27 SEP 2011 1.20 0.50 8X 0.25 7X 0.40 PITCH 0.40 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON59259E UDFN8, 3.3X1.0, 0.4P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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