ESD8704MUTAG

ESD8704 ESD Protection Diode Low Capacitance Array for High Speed Data Lines The ESD8704 is designed to protect high speed data lines from ESD. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3.0/3.1. www.onsemi.com MARKING DIAGRAM UDFN10 CASE 517BB Features • Low Capacitance (0.5 pF Max, I/O to GND) • Protection for the Following IEC Standards: IEC 61000−4−2 (Level 4) • Low ESD Clamping Voltage • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS 7DMG G 7D = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) Compliant PIN CONFIGURATION AND SCHEMATIC Typical Applications • USB 3.0/3.1 • eSATA • DisplayPort N/C N/C 10 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD ESD ±30 ±30 kV kV IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. GND N/C N/C 9 8 7 6 1 2 3 4 5 I/O I/O GND I/O I/O I/O Pin 1 I/O Pin 2 I/O Pin 4 I/O Pin 5 Pins 3, 8 Note: Common GND − Only Minimum of 1 GND connection required = ORDERING INFORMATION October, 2015 − Rev. 0 Package Shipping ESD8704MUTAG UDFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2015 Device 1 Publication Order Number: ESD8704/D ESD8704 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol VRWM IR VBR IPP Parameter Working Peak Voltage RDYN Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT V VC VRWMVHOLD Test Current IR IT VHOLD Holding Reverse Voltage IHOLD IHOLD Holding Reverse Current RDYN Dynamic Resistance IT VC RDYN IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VC = VHOLD + (IPP * RDYN) −IPP VC = VHOLD + (IPP * RDYN) ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions Min Typ I/O Pin to GND IT = 1 mA, I/O Pin to GND 5.0 VRWM = 3.3 V, I/O Pin to GND Max Unit 3.3 V 6.0 V 1.0 mA Reverse Leakage Current IR Holding Reverse Voltage VHOLD I/O Pin to GND 1.9 V Holding Reverse Current IHOLD I/O Pin to GND 20 mA Clamping Voltage VC IEC61000−4−2, ±8 KV Contact Clamping Voltage TLP VC IPP = 8 A IPP = −8 A 4.7 −4.0 IPP = 16 A IPP = −16 A 6.6 −6.7 I/O Pin to GND GND to I/O Pin 0.30 0.38 VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 2.5 GHz between I/O Pins and GND VR = 0 V, f = 5.0 GHz between I/O Pins and GND VR = 0 V, f = 1 MHz, between I/O Pins 0.30 0.30 0.31 0.15 Dynamic Resistance RDYN Junction Capacitance CJ V V W 0.50 0.40 0.40 0.25 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 10 80 0 70 −10 60 −20 VOLTAGE (V) VOLTAGE (V) 90 50 40 30 20 −40 −50 −60 −70 10 −80 0 −10 −20 −30 −90 0 20 40 60 80 100 120 −100 −20 140 TIME (ns) 0 20 40 60 80 100 120 TIME (ns) Figure 1. IEC61000−4−2 +8 kV Contact ESD Clamping Voltage Figure 2. IEC61000−4−2 −8 kV Contact Clamping Voltage www.onsemi.com 2 140 ESD8704 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8307/D − Characterization of ESD Clamping Performance. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 3 20 −20 16 −16 TLP CURRENT (A) TLP CURRENT (A) ESD8704 12 8 −12 −8 −4 4 0 0 0 NOTE: 1 2 3 4 5 6 7 8 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 9 10 11 12 13 14 VC, VOLTAGE (V) VC, VOLTAGE (V) Figure 5. Positive TLP I−V Curve Figure 6. Negative TLP I−V Curve TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 7. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 8 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 7. Simplified Schematic of a Typical TLP System Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4 1.0 1.0 0.9 0.9 0.8 0.8 CJ, CAPACITANCE (pF) CJ, CAPACITANCE (pF) ESD8704 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 VR, REVERSE VOLTAGE (V) 3 0.0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 FREQUENCY (GHz) 3.5 Figure 9. Junction Capacitance vs. Reverse Voltage Figure 10. Junction Capacitance vs. Frequency 5 Gbps Eye Diagram Without ESD8704 5 Gbps Eye Diagram With ESD8704 Figure 11. USB3.0 Eye Diagram with and without ESD8704. 5 Gb/s 10 Gbps Eye Diagram Without ESD8704 10 Gbps Eye Diagram With ESD8704 Figure 12. USB3.1 Eye Diagram with and without ESD8704. 10 Gb/s See application note AND9075/D for further description of eye diagram testing methodology. www.onsemi.com 5 ESD8704 Figure 13. ESD8704 Insertion Loss Interface Data Rate (Gb/s) Fundamental Frequency (GHz) 3rd Harmonic Frequency (GHz) USB 3.0 5 2.5 (m1) 7.5 (m3) USB 3.1 10 5.0 (m2) 15 (m4) www.onsemi.com 6 ESD8704 Insertion Loss (dB) m1 = −0.09 m3 = −0.89 m2 = −0.36 m4 = −9.68 ESD8704 USB 3.0/3.1 Type A Connector StdA_SSTX+ Vbus StdA_SSTX− ESD8704 D− ESD7L5.0 GND_DRAIN D+ StdA_SSRX+ GND StdA_SSRX− Figure 14. USB 3.0/3.1 Standard Layout Diagram PCB Layout Guidelines Steps must be taken for proper placement and signal trace routing of the ESD protection device in order to ensure the maximum ESD survivability and signal integrity for the application. Such steps are listed below. • Place the ESD protection device as close as possible to the I/O connector to reduce the ESD path to ground and improve the protection performance. ♦ In USB 3.0 applications, the ESD protection device should be placed between the AC coupling capacitors and the I/O connector on the TX differential lanes as shown in Figure 15. In this configuration, no DC current can flow through the ESD protection device preventing any potential • latch-up condition. For more information on latchup considerations, see below description on Page 8. Make sure to use differential design methodology and impedance matching of all high speed signal traces. ♦ Use curved traces when possible to avoid unwanted reflections. ♦ Keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ♦ Place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. Figure 15. USB 3.0/3.1 Connection Diagram www.onsemi.com 7 ESD8704 Latch-Up Considerations therefore latch-up free. Please note that for USB 3.0 applications, ESD8704 latch-up free considerations are explained in more detail in the above PCB layout guidelines. In the non-latch up free load line case, the IV characteristic of the snapback protection device intersects the load-line in two points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this case, the potential for latch-up exists if the system settles at (VOPB, IOPB) after a transient. Because of this, ESD8704 should not be used for HDMI applications – ESD8104 or ESD8040 have been designed to be acceptable for HDMI applications without latch-up. Please refer to Application Note AND9116/D for a more in-depth explanation of latch-up considerations using ESD8000 series devices. ON Semiconductor’s 8000 series of ESD protection devices utilize a snap-back, SCR type structure. By using this technology, the potential for a latch-up condition was taken into account by performing load line analyses of common high speed serial interfaces. Example load lines for latch-up free applications and applications with the potential for latch-up are shown below with a generic IV characteristic of a snapback, SCR type structured device overlaid on each. In the latch-up free load line case, the IV characteristic of the snapback protection device intersects the load-line in one unique point (VOP, IOP). This is the only stable operating point of the circuit and the system is I I ISSMAX IOPB ISSMAX IOP VOP IOPA V VDD VOPB ESD8704 Latch−up free: USB 2.0 LS/FS, USB 2.0 HS, USB 3.0/3.1 SS, DisplayPort VOPA VDD V ESD8704 Potential Latch−up: HDMI 1.4/1.3a TMDS Figure 16. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS Application VBR (min) (V) IH (min) (mA) VH (min) (V) ON Semiconductor ESD8000 Series Recommended PN HDMI 1.4/1.3a TMDS 3.465 54.78 1.0 ESD8104, ESD8040 USB 2.0 LS/FS 3.301 1.76 1.0 ESD8704 USB 2.0 HS 0.482 N/A 1.0 ESD8704 USB 3.0/3.1 SS 2.800 N/A 1.0 ESD8704, ESD8006 DisplayPort 3.600 25.00 1.0 ESD8704, ESD8006 www.onsemi.com 8 ESD8704 PACKAGE DIMENSIONS UDFN10 2.5x1, 0.5P CASE 517BB ISSUE O L D 0.10 C 2X 2X A B ÍÍÍ ÍÍÍ PIN ONE REFERENCE 0.10 C L1 DETAIL A OPTIONAL CONSTRUCTIONS E TOP VIEW A3 A 0.10 C A1 0.08 C A1 C SIDE VIEW 2X DETAIL A 10 A3 DETAIL B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. DIM A A1 A3 b b2 D E e L L1 MILLIMETERS MIN MAX 0.55 0.45 0.00 0.05 0.13 REF 0.15 0.25 0.45 0.35 2.50 BSC 1.00 BSC 0.50 BSC 0.30 0.40 --0.05 OPTIONAL CONSTRUCTION SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* b2 1 ÇÇÇ ÇÇÇ ÉÉÉ ÉÉÉ MOLD CMPD EXPOSED Cu DETAIL B 10X L 10X L 10X 5 2X 0.50 6 0.45 1.30 e 8X b 0.10 C A BOTTOM VIEW 0.05 C PACKAGE OUTLINE B NOTE 3 0.50 PITCH 8X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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