ESD9L3.3ST5G

ESD9L3.3ST5G Transient Voltage Suppressors ESD Protection Diodes with Ultra−Low Capacitance The ESD9L is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications. Specification Features: http://onsemi.com 1 PIN 1. CATHODE 2. ANODE 2 • Ultra Low Capacitance 0.5 pF • Low Clamping Voltage • Small Body Outline Dimensions: • • • • • • 2 1 SOD−923 CASE 514AB 0.039″ x 0.024″ (1.00 mm x 0.60 mm) Low Body Height: 0.016″ (0.4 mm) Stand−off Voltage: 3.3 V Low Leakage Response Time is Typically < 1.0 ns IEC61000−4−2 Level 4 ESD Protection This is a Pb−Free Device MARKING DIAGRAM 1 6M 2 Mechanical Characteristics: CASE: Void-free, transfer-molded, thermosetting plastic Epoxy Meets UL 94 V−0 LEAD FINISH: 100% Matte Sn (Tin) MOUNTING POSITION: Any QUALIFIED MAX REFLOW TEMPERATURE: 260°C 6 = Specific Device Code M = Date Code *Date Code orientation and/or position may vary depending upon manufacturing location. Device Meets MSL 1 Requirements MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) ORDERING INFORMATION Device Symbol Value ±10 ±15 °PD° Tstg TJ TL 150 −55 to +150 −55 to +125 260 Unit kV mW °C °C °C ESD9L3.3ST5G Package SOD−923 (Pb−Free) Shipping† 8000/Tape & Reel Contact Air Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Storage Temperature Range Junction Temperature Range Lead Solder Temperature − Maximum (10 Second Duration) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. DEVICE MARKING INFORMATION See specific marking information in the device marking column of the Electrical Characteristics tables starting on page 2 of this data sheet. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 3 1 Publication Order Number: ESD9L3.3S/D ESD9L3.3ST5G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Max. Capacitance @ VR = 0 and f = 1.0 MHz IPP VC VBR VRWM IR VF IT V IF I Uni−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.0 V Max. @ IF = 10 mA for all types) VRWM (V) Device ESD9L3.3ST5G Device Marking 6* Max 3.3 IR (mA) @ VRWM Max 1.0 VBR (V) @ IT (Note 2) Min 4.8 IT mA 1.0 C (pF) Typ 0.5 Max 0.9 VC (V) @ IPP = 1 A Max 9.0 VC Per IEC61000−4−2 (Note 3) Figures 1 and 2 See Below *Rotated 180°. 2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C. 3. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 ESD9L3.3ST5G IEC 61000−4−2 Spec. Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000−4−2 Waveform Ipeak 100% 90% Level 1 2 3 4 Figure 3. IEC61000−4−2 Spec ESD Gun TVS Oscilloscope 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger 100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms Figure 5. 8 X 20 ms Pulse Waveform 40 t, TIME (ms) 60 80 http://onsemi.com 3 ESD9L3.3ST5G PACKAGE DIMENSIONS SOD−923 CASE 514AB−01 ISSUE B D −X− −Y− E 1 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b c D E HE L MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.15 0.20 0.25 0.07 0.12 0.17 0.75 0.80 0.85 0.55 0.60 0.65 0.95 1.00 1.05 0.05 0.10 0.15 MIN 0.013 0.006 0.003 0.030 0.022 0.037 0.002 INCHES NOM 0.015 0.008 0.005 0.031 0.024 0.039 0.004 MAX 0.016 0.010 0.007 0.033 0.026 0.041 0.006 b 2X 0.08 (0.0032) X Y A c L HE SOLDERING FOOTPRINT* 0.90 0.40 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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