FDMA530PZ

MOSFET - Power, Single P-Channel, POWERTRENCH) −30 V, −6.8 A, 35 mW FDMA530PZ General Description This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications . It features a MOSFET with low on−state resistance. The WDFN6 (MicroFET 2 × 2) package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. Features • Max rDS(on) = 35 mW at VGS = − 10 V, ID = − 6.8 A • Max rDS(on) = 65 mW at VGS = − 4.5 V, ID = − 5.0 A • Low Profile − 0.8 mm Maximum − in the New Package WDFN6 www.onsemi.com Bottom Drain Contact D 1 6 D D 2 5 D G 3 4 S (MicroFET 2 × 2 mm) • HBM ESD Protection Level > 3k V Typical (Note 3) • Free from Halogenated Compounds and Antimony Oxides • RoHS Compliant Pin 1 D D G Drain Source MOSFET MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Symbol Parameter Ratings Unit VDS Drain to Source Voltage −30 V VGS Gate to Source Voltage ±25 V Drain Current Continuous (Note 1a) −6.8 A Pulsed −24 (Note 1a) 2.4 (Note 1b) 0.9 ID PD TJ, TSTG Power Dissipation Operating Junction and Storage Temperature Range D MARKING DIAGRAM &Z&2&K 530 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. &Z &2 &K 530 THERMAL CHARACTERITICS Symbol RqJA Parameter Thermal Resistance, Junction to Ambient Ratings Unit (Note 1a) 52 °C/W (Note 1b) 145 S WDFN6 (MicroFET 2 x 2) CASE 511CZ W −55 to +150 D = Assembly Plant Code = Date Code = Lot Code = Specific Device Code ORDERING INFORMATION Device Marking Device Package Shipping{ 530 FDMA530PZ WDFN6 (MicroFET 2x2) 3000 Units/ Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 September, 2019 − Rev. 4 1 Publication Order Number: FDMA530PZ/D FDMA530PZ ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit OFF CHARACTERISTICS BVDSS Drain to Source Breakdown Voltage ID = −250 mA, VGS = 0 V −30 V DBVDSS DTJ Breakdown Voltage Temperature Coefficient ID = −250 mA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = −24 V, VGS = 0 V −1 mA IGSS Gate to Source Leakage Current VGS = ±25 V, VDS = 0 V ±10 mA −3 V −23 mV/°C ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = −250 mA DVGS(th) DTJ Gate to Source Threshold Voltage Temperature Coefficient ID = −250 mA, referenced to 25°C 5.4 Static Drain to Source on Resistance VGS = −10 V, ID = −6.8 A 30 35 VGS = −4.5 V, ID = −5.0 A 52 65 VGS = −10 V, ID = −6.8 A, TJ = 125°C 43 63 VDS = −10 V, ID = −6.8 A 17 VDS = −15 V, VGS = 0 V, f = 1 MHz 805 1070 155 210 130 195 18 38 W 6 12 ns 21 34 43 69 rDS(on) gFS Forward Transconductance −1 −2.1 mV/°C mW S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance 1 pF SWITCHING CHARACTERISTICS td(on) tr td(off) tf Turn−On Delay Time Rise Time VDD = −15 V, ID = −6.8 A, VGS = −10 V, RGEN = 6 W Turn−Off Delay Time 31 50 Qg Fall Time Total Gate Charge VGS = −10 V 16 24 Qg Total Gate Charge VGS = −5 V 9 11 Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge VDD = −15 V ID = −6.8 A nC 3.1 4.5 DRAIN−SOURCE DIODE CHARACTERISTICS IS VSD Maximum Continuous Drain−Source Diode Forward Current Source to Drain Diode Forward Voltage VGS = 0 V, IS = −2 A trr Reverse Recovery Time Qrr Reverse Recovery Charge IF = −6.8 A, di/dt = 100 A/mS −2 A −0.8 −1.2 V 24 36 ns 19 29 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. b. 145 °C/W when mounted on a minimum pad of 2 oz copper a. 52 °C/W when mounted on a 1 in2 pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%. 3. The diode connected between the gate and the source serves only as protection against ESD. No gate overvoltage rating is implied. www.onsemi.com 2 FDMA530PZ TYPICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) 24 3.5 20 VGS = −10 V NORMALIZED DRAIN TO SOURCE ON−RESISTANCE −ID, DRAIN CURRENT (A) VGS = −4.5 V VGS = −4.0 V VGS = −5.0 V 16 12 VGS = −3.5 V 8 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 4 0 0 1 2 3 4 VGS = −4.5 V 2.5 VGS = −5.0 V 2.0 1.5 VGS = −10 V 1.0 0.5 5 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 0 4 −VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO SOURCE ON−RESISTANCE (mW) NORMALIZED DRAIN TO SOURCE ON−RESISTANCE 200 ID = −3.4 A ID = −6.8 A VGS = −10 V 1.6 1.4 1.2 1.0 −25 0 25 50 75 100 125 TJ = 125°C TJ = 25°C 2 −IS, REVERSE DRAIN CURRENT (A) 12 TJ = −55°C 6 TJ = 25°C 3 4 5 4 6 8 10 Figure 4. On−Resistance vs. Gate to Source Voltage VDD = −5 V 2 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX −VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 1 24 50 0 150 24 0 20 100 Figure 3. Normalized On−Resistance vs. Junction Temperature TJ = 125°C 16 150 TJ, JUNCTION TEMPERATURE (5C) 18 12 Figure 2. Normalized On−Resistance vs. Drain Current and Gate Voltage 1.8 −ID, DRAIN CURRENT (A) 8 −ID, DRAIN CURRENT (A) Figure 1. On−Region Characteristics 0.8 −50 VGS = −4.0 V VGS = −3.5 V 3.0 6 30 10 1 VGS = 0 V TJ = 125°C 0.1 TJ = 25°C 0.01 TJ = −55°C 0.001 0.0001 0.0 0.4 0.8 1.2 −VGS, GATE TO SOURCE VOLTAGE (V) −VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs. Source Current www.onsemi.com 3 1.6 FDMA530PZ 10 2000 ID = −6.8 A VDD = −15 V 6 VDD = −20 V 4 2 0 Ciss 1000 VDD = −10 V 8 CPACITANCE (pF) −VGS, GATE TO SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued) Coss 100 0 3 6 9 12 15 50 0.1 18 1 Qg, GATE CHARGE (nC) −ID, DRAIN CURRENT (A) 1E−5 TJ = 125°C 1E−6 TJ = 25°C 1E−8 rDS(on) LIMIT 10 100 us 1 ms 1 10 ms VGS = −4.5 V SINGLE PULSE 100 ms 1s 10 s DC 0.1 RqJA = 145°C/W TA = 25°C 0 5 10 15 20 25 30 0.01 0.1 35 10 100 −VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 9. Gate Leakage Current vs. Gate to Source Voltage Figure 10. Forward Bias Safe Operating Area 150 2 SINGLE PULSE 1 RqJA = 145°C/W 120 TA = 25°C 90 60 30 0 10−4 1 −VDS, DRAIN TO SOURCE VOLTAGE (V) NORMALIZED THERMAL IMPEDANCE, ZqJA P(PK), PEAK TRANSIENT POWER (W) −Ig, GATE LEAKAGE CURRENT (A) 60 1E−4 1E−9 20 Figure 8. Capacitance vs. Drain to Source Voltage VGS = 0 V 1E−7 10 −VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics 1E−3 Crss f = 1 Mhz VGS = 0 V 10−3 10−2 10−1 100 101 102 0.1 DUTY CYCLE − DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 t, PULSE WIDTH (s) t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM × ZqJA × RqJA + TA 0.01 10−3 103 PDM 10−2 10−1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) Figure 11. Single Pulse Maximum Power Dissipation Figure 12. Transient Thermal Response Curve POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN6 2x2, 0.65P CASE 511CZ ISSUE O 0.05 C 2.0 DATE 31 JUL 2016 1.70 A B 2X (0.20) 1.00 No Traces allowed in 4 6 this Area 2.0 0.05 TOP VIEW PIN#1 IDENT 1.05 2.30 0.47(6X) C 2X 1 3 0.40(6X) 0.65 0.10 RECOMMENDED LAND PATTERN OPT 1 0.75±0.05 C 0.20±0.05 1.70 0.08 C SIDE VIEW 0.025±0.025 C 0.45 (0.20) 1.00 6 SEATING PLANE 4 2.00±0.05 (0.15) 1.05 (0.50) 0.30±0.05 0.90±0.05 PIN #1 IDENT 2.30 (0.20)4X 1 0.47(6X) 3 0.28±0.05 1 0.56±0.05 (6X) 0.65 3 0.40(7X) RECOMMENDED LAND PATTERN OPT 2 1.00±0.05 2.00±0.05 (0.50) 0.66 NOTES: 6 4 0.30±0.05 (6X) 0.65 1.30 0.10 C 0.05 C BOTTOM VIEW A B A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO−229 REGISTRATION B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. DOCUMENT NUMBER: DESCRIPTION: 98AON13614G WDFN6 2X2, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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