STD24N06LT4G-VF01

NTD24N06L, STD24N06L MOSFET – Power, N-Channel, Logic Level, DPAK 24 A, 60 V Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com 24 AMPERES, 60 VOLTS RDS(on) = 0.036 W (Typ) Features D • S Prefix for Automotive and Other Applications Requiring Unique • Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant N−Channel G Typical Applications • • • • S Power Supplies Converters Power Motor Controls Bridge Circuits 4 1 2 Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−repetitive (tpv10 ms) Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 1.0 mH, IL(pk) = 18 A, VDS = 60 Vdc) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds Vdc VGS VGS "15 "20 ID ID 24 10 72 Adc PD 62.5 0.42 1.88 1.36 W W/°C W W TJ, Tstg −55 to +175 °C EAS 162 mJ RqJC RqJA RqJA 2.4 80 110 TL 260 IDM 4 Drain Apk °C/W °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 sq. in. pad size. © Semiconductor Components Industries, LLC, 2014 May, 2019 − Rev. 4 MARKING DIAGRAM & PIN ASSIGNMENT AYWW 24 N6LG Rating 3 DPAK CASE 369C (Surface Mount) STYLE 2 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 1 2 1 3 Drain Gate Source A Y WW 24N6L G = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information on page 3 of this data sheet. Publication Order Number: NTD24N06L/D NTD24N06L, STD24N06L 2. When surface mounted to an FR4 board using minimum recommended pad size. http://onsemi.com 2 NTD24N06L, STD24N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Min Typ Max Unit 60 − 71.9 69.6 − − − − − − 1.0 10 − − ±100 1.0 − 1.7 5.0 2.0 − − − 36 36 45 − − − − 0.9 0.9 0.78 1.2 − − gFS − 19 − mhos Ciss − 814 1140 pF Coss − 258 360 Crss − 80 115 td(on) − 9.4 20 200 OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 5.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 12 Adc) RDS(on) Static Drain−to−Source On−Resistance (Note 3) (VGS = 5.0 Vdc, ID = 20 Adc) (VGS = 5.0 Vdc, ID = 24 Adc) (VGS = 5.0 Vdc, ID = 12 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 12 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDD = 30 Vdc, ID = 24 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 3) (VDS = 48 Vdc, ID = 24 Adc, VGS = 5.0 Vdc) (Note 3) ns tr − 97 td(off) − 23 50 tf − 52 100 QT − 16 32 Q1 − 3.4 − Q2 − 11 − VSD − − − 0.93 0.95 0.86 1.1 − − Vdc trr − 49 − ns ta − 30 − tb − 20 − QRR − 0.084 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage Reverse Recovery Time (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 24 Adc, VGS = 0 Vdc) (IS = 24 Adc, VGS = 0 Vdc, TJ = 150°C) (IS = 24 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. ORDERING INFORMATION Package Shipping† NTD24N06LT4G DPAK (Pb−Free) 2500 / Tape & Reel STD24N06LT4G* DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. http://onsemi.com 3 NTD24N06L, STD24N06L 50 ID, DRAIN CURRENT (AMPS) 6V 4V 20 3.5 V 10 3V 0 0.1 1 2 TJ = 100°C 20 10 3.2 2.4 4 4.8 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 5 V TJ = 100°C TJ = 25°C TJ = −55°C 0.02 0 10 20 30 40 50 0.1 VGS = 10 V 0.08 0.06 TJ = 100°C 0.04 TJ = 25°C 0.02 TJ = −55°C 0 0 10 20 30 40 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 10000 ID = 12 A VGS = 5 V IDSS, LEAKAGE (nA) 1.8 TJ = −55°C VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.04 2 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.06 0 TJ = 25°C 40 0 1.6 4 3 0.08 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 8V 30 0 VDS ≥ 10 V 4.5 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 40 50 5V VGS = 10 V 1.6 50 VGS = 0 V TJ = 150°C 1000 1.4 1.2 1 100 TJ = 100°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 1 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 60 NTD24N06L, STD24N06L POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 2800 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 2400 2000 Ciss 1600 1200 Crss Ciss 800 Coss 400 0 Crss 10 5 VGS 0 VDS 5 10 15 20 25 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 1000 6 QT 5 Q1 4 Q2 VGS t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTD24N06L, STD24N06L 3 2 1 0 100 tr tf td(off) 10 td(on) VDS = 30 V ID = 24 A VGS = 5 V ID = 24 A TJ = 25°C 0 4 8 12 16 QG, TOTAL GATE CHARGE (nC) 1 20 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 24 VGS = 0 V TJ = 25°C 20 16 12 8 4 0 0.6 0.68 0.76 0.84 0.92 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 6 NTD24N06L, STD24N06L I D, DRAIN CURRENT (AMPS) 100 VGS = 15 V SINGLE PULSE TC = 25°C 10 10 ms 100 ms 1 ms 10 ms 1 0.1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 180 140 120 100 80 60 40 20 0 Figure 11. Maximum Rated Forward Biased Safe Operating Area 1.0 ID = 18 A 160 25 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 7 1.0E+00 1.0E+01 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E C A b3 B c2 4 L3 Z D 1 2 H DETAIL A 3 L4 NOTE 7 c SIDE VIEW b2 e b 0.005 (0.13) TOP VIEW BOTTOM VIEW C M Z H L2 GAUGE PLANE C L SEATING PLANE BOTTOM VIEW A1 L1 DETAIL A Z ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. 2.58 0.102 1.60 0.063 IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. 6.17 0.243 SCALE 3:1 AYWW XXX XXXXXG XXXXXX A L Y WW G 3.00 0.118 5.80 0.228 XXXXXXG ALYWW mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: 98AON10527D ON SEMICONDUCTOR STANDARD REF TO JEDEC TO−252 http://onsemi.com DPAK SINGLE GAUGE SURFACE 1 MOUNT © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON10527D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001 A ADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008 B ADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009 C ADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009 D RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A. CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010 E ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAMBALIZA. 06 FEB 2014 F ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K. MUSTAFA. 21 JUL 2015 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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