87002AG-02LF

1:2, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator 87002-02 DATA SHEET General Description Features The 87002-02 is a highly versatile 1:2 Differential-toLVCMOS/LVTTL Clock Generator. The 87002-02 has a differential clock input. The CLK, nCLK pair can accept most standard differential input levels. Internal bias on the nCLK input allows the CLK input to accept LVCMOS/LVTTL. The 87002-02 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • • Two LVCMOS/LVTTL outputs, 7 typical output impedance • Internal bias on nCLK to support LVCMOS/LVTTL levels on CLK input • • • • Output frequency range: 15.625MHz to 250MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • • • • • • • • • Fully integrated PLL Block Diagram PLL_SEL Input frequency range: 15.625MHz to 250MHz VCO range: 250MHz to 500MHz External feedback for “zero delay” clock regeneration with configurable frequencies Cycle-to-cycle jitter: 45ps (maximum) Output skew: 35ps (maximum) Static phase offset: -10ps ± 150ps (3.3V ± 5%) Full 3.3V or 2.5V operating supply 5V tolerant inputs 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Industrial temperature information available upon request Pin Assignment Pullup ÷2, ÷4, ÷8, ÷16 ÷32, ÷64, ÷128 CLK Pulldown nCLK Pullup/Pulldown 0 Q0 1 Q1 GND Q0 VDDO SEL0 SEL1 SEL2 SEL3 VDD CLK nCLK PLL FB_IN Pulldown CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 GND VDDO nc MR FB_IN PLL_SEL VDDA GND 87002-02 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View SEL0 Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR Pulldown 87002-02 Rev C 7/13/15 1 ©2015 Integrated Device Technology, Inc. 87002-02 DATA SHEET Table 1. Pin Descriptions Number Name 1, 11, 18 GND Power Type Power supply ground. Description 2, 19 Q0, Q1 Output Single-ended clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. 3, 17, 20 VDDO Power Output supply pins. 4, 5, 6, 7 SEL0, SEL1, SEL2, SEL3 Input 8 VDD Power 9 CLK Input Pulldown Non-inverting differential clock input. 10 nCLK Input Pullup/ Pulldown Inverting differential clock input. VDD/2 default when left floating. 12 VDDA Power 13 PLL_SEL Input Pullup 14 FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks with “Zero Delay.” Connect to one of the outputs. LVCMOS/LVTTL interface levels. 15 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 16 nc Unused Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Core supply pin. Analog supply pin. PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock (PLL Bypass). When HIGH, selects PLL (PLL enabled). LVCMOS/LVTTL interface levels. No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k CPD Power Dissipation Capacitance (per output) ROUT Output Impedance VDD, VDDA, VDDO = 3.465V 23 pF VDD, VDDA, VDDO = 2.625V 17 pF 12  1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 5 2 7 Rev C 7/13/15 87002-02 DATA SHEET Function Tables Table 3A. PLL Enable Function Table Outputs PLL_SEL = 1 PLL Enable Mode Inputs SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q0, Q1 0 0 0 0 125 - 250 ÷1 0 0 0 1 62.5 - 125 ÷1 0 0 1 0 31.25 - 62.5 ÷1 0 0 1 1 15.625 - 31.25 ÷1 0 1 0 0 125 - 250 ÷2 0 1 0 1 62.5 - 125 ÷2 0 1 1 0 31.25 - 62.5 ÷2 0 1 1 1 125 - 250 ÷4 1 0 0 0 62.5 - 125 ÷4 1 0 0 1 125 - 250 ÷8 1 0 1 0 62.5 - 125 x2 1 0 1 1 31.25 - 62.5 x2 1 1 0 0 15.625 - 31.25 x2 1 1 0 1 31.25 - 62.5 x4 1 1 1 0 15.625 - 31.25 x4 1 1 1 1 15.625 - 31.25 x8 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 3 Rev C 7/13/15 87002-02 DATA SHEET Table 3B. PLL Bypass Function Table Outputs PLL_SEL = 0 PLL Bypass Mode Inputs SEL3 SEL2 SEL1 SEL0 Q0, Q1 0 0 0 0 ÷8 0 0 0 1 ÷8 0 0 1 0 ÷8 0 0 1 1 ÷16 0 1 0 0 ÷16 0 1 0 1 ÷16 0 1 1 0 ÷32 0 1 1 1 ÷32 1 0 0 0 ÷64 1 0 0 1 ÷128 1 0 1 0 ÷4 1 0 1 1 ÷4 1 1 0 0 ÷8 1 1 0 1 ÷2 1 1 1 0 ÷4 1 1 1 1 ÷2 Rev C 7/13/15 4 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 6 mA Table 4B. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 96 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 6 mA 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 5 Rev C 7/13/15 87002-02 DATA SHEET Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Test Conditions Minimum VDD = 3.3V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V FB_IN, SEL[0:3], MR VDD = VIN = 3.465V or 2.625V 150 µA PLL_SEL VDD = VIN = 3.465V or 2.625V 5 µA FB_IN, SEL[0:3], MR VDD = 3.465V or 2.625V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -150 µA VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V Input Low Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams. Table 4D. Differential DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK VDD = VIN = 3.465V or 2.625V 150 µA nCLK VDD = VIN = 3.465V or 2.625V 150 µA CLK VDD = 3.465V or 2.625V, VIN = 0V -5 µA nCLK VDD = 3.465V or 2.625V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Rev C 7/13/15 6 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 15.625 250 MHz PLL_SEL = 0V, f  250MHz, Qx ÷ 2 4.8 5.8 ns PLL_SEL = 3.3V, fREF  167MHz, Qx ÷ 1 -160 140 ps tPD Propagation Delay; NOTE 1 t(Ø) Static Phase Offset; NOTE 2, 4 tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 40 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 fOUT > 40MHz 45 ps tL PLL Lock Time 1 ms tR / tF Output Rise/Fall Time 400 800 ps odc Output Duty Cycle 40 60 % 20% to 80% -10 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t(Ø) Static Phase Offset; NOTE 2, 4 tsk(o) Output Skew; NOTE 3, 4 tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 tL PLL Lock Time tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Maximum Units 15.625 250 MHz PLL_SEL = 0V, f  250MHz, Qx ÷ 2 4.9 6.7 ns PLL_SEL = 2.5V, fREF  167MHz, Qx ÷ 1 -240 110 ps PLL_SEL = 0V 35 ps fOUT > 40MHz 45 ps 1 ms 400 700 ps 44 56 % 20% to 80% Minimum Typical -65 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 7 Rev C 7/13/15 87002-02 DATA SHEET Parameter Measurement Information 1.65V±5% 1.25V±5% SCOPE VDD, VDDA, VDDO SCOPE VDD, VDDA, VDDO Qx GND Qx GND -1.65V±5% -1.25V±5% 3.3V Output Load AC Test Circuit 2.5V Output Load AC Test Circuit VDD V DDO Qx 2 nCLK V V Cross Points PP CMR V DDO CLK 2 tsk(o) Qy GND Differential Input Level Output Skew V DDO V DDO 2 DDO 2 ➤ tcycle n ➤ VOH CLK VOL 2 tcycle n+1 VOH VDDO ➤ 2 VOL FB_IN ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles ➤ t(Ø) ➤ V Q0, Q1 nCLK t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges. Cycle-to-Cycle Jitter Rev C 7/13/15 Static Phase Offset 8 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Parameter Measurement Information, continued nCLK 80% 80% Q0, Q1 CLK 20% 20% tR tF Q0, Q1 VDDO 2 t PD Propagation Delay Output Rise/Fall Time V DDO 2 Q0, Q1 t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 9 Rev C 7/13/15 87002-02 DATA SHEET Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 87002-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. The 10 resistor can also be replaced by a ferrite bead. 3.3V or 2.5V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels Rev C 7/13/15 10 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 3.3V 2.5V R3 120Ω R4 120Ω Zo = 60Ω *R3 CLK CLK Zo = 60Ω nCLK nCLK HCSL *R4 SSTL Differential Input R1 120Ω Differential Input Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR R2 120Ω 11 Rev C 7/13/15 87002-02 DATA SHEET Schematic Example Figure 4 shows an example of 87002-02 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. Figure 4. 87002-02 Schematic Example Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVCMOS Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS output can be left floating. There should be no trace attached. Rev C 7/13/15 12 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Reliability Information Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 87002-02 is: 2578 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 7. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 13 Rev C 7/13/15 87002-02 DATA SHEET Ordering Information Table 8. Ordering Information Part/Order Number 87002AG-02LF 87002AG-02LFT Marking ICS87002A02L ICS87002A02L Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Rev C 7/13/15 14 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Revision History Sheet Rev Table Page T2 Pin Characteristics Table - added CPD specs. Added Recommendations for Unused Input and Output Pins section. Updated Differential Clock Input Interface section. Added Schematic Layout Ordering Information Table - added Lead-Free marking. 4/29/08 T8 2 10 11 12 14 T5A, T5B T5B 7 7 8/9/10 T8 10 14 Added thermal note. 2.5V AC Characteristics Table - due to datasheet conversion on April 29, 2008, corrected typo for static phase offset spec from -650 to -65. Updated Wiring the Differential Levels to Accept Single-ended Levels section. Ordering Information Table - deleted “ICS” prefix from the Part/Order Number column. Updated header/footer of datasheet. T8 14 Ordering Information - removed leaded devices. Updated data sheet format. 7/13/15 B C C Description of Change 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 15 Date Rev C 7/13/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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