LVDS Interface ICs
56bit LVDS Transmitter
56:8 Serializer
No.12057EAT05
BU7988KVT
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits
range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The
ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
1) Wide dot clock range : Single(112MHz)/Dual(224MHz)(NTSC, VGA, SVGA, WXGA UXGA)
2) Support spread spectrum clock generator.
3) Clock edge selectable.
4) Support reduced swing LVDS for low EMI.
5) Power down mode.
6) Package TQFP100V
●Applications
Flat Plane Display
●Precaution
■This chip is not designed to protect from radioactivity.
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© 2011 ROHM Co., Ltd. All rights reserved.
1/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●Block Diagram
LVCMOS Input
CLK_IN
LVDS Output
＋
－
PLL
B10～B17
8
8
8
8
8
R20～R27
8
8
G20～G27
8
8
B20～B27
8
PARALLEL TO SERIAL
G10～G17
8
MUX
R10～R17
PARALLEL TO SERIAL
(4～150MHz)
8
HSYNC
VSYNC
DE
TCLK1 P/N
(8～112MHz)
＋
－
TA1 P/N
＋
－
TB1 P/N
＋
－
TC1 P/N
＋
－
TD 1 P/N
＋
－
TCLK2 P/N
(8～112MHz)
＋
－
TA2 P/N
＋
－
TB2 P/N
＋
－
TC2 P/N
＋
－
TD2 P/N
MODE0
MODE1
XRST
OE
SEL_BIT
RF
RS
MAP
FLIP
Fig.1 Block Diagram
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© 2011 ROHM Co., Ltd. All rights reserved.
2/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●TQFP100V
Package Outline and Specification
Product No.
16.0±0.3
14.0±0.2
51
75
76
50
16.0±0.3
14.0±0.2
BU7988KVT
1PIN MARK
100
26
0.5
Lot No.
25
1
1.2MAX
1.0±0.1
0.1±0.1
0.125±0.1
0.2±0.1
Fig.2
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© 2011 ROHM Co., Ltd. All rights reserved.
0.5
0.1
TQFP100V Package Outline and Specification
3/27
2011.12 - Rev.A
Technical Note
BU7988KVT
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100-Pin TQFP
(Top View)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
LVDS GND
TA1N
TA1P
TB1N
TB1P
LVDS VDD
TC1N
TC1P
TCLK1N
TCLK1P
TD1N
TD1P
LVDS GND
TA2N
TA2P
TB2N
TB2P
LVDS VDD
TC2N
TC2P
TCLK2N
TCLK2P
TD2N
TD2P
LVDS GND
B24
B25
VDD
GND
B26
B27
HSYNC
VSYNC
DE
CLKIN
RF
RS
Reserved0
MAP
MODE1
MODE0
OE
SEL_BIT
XRST
Reserved1
FLIP
N/C
PLL GND
PLL VCC
PLL GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
B15
B16
B17
R20
R21
R22
R23
R24
R25
R26
R27
VDD
GND
G20
G21
G22
G23
G24
G25
G26
G27
B20
B21
B22
B23
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
B14
B13
B12
GND
VDD
B11
B10
G17
G16
G15
G14
G13
G12
G11
G10
R17
R16
R15
R14
GND
VDD
R13
R12
R11
R10
●Pin configuration
Fig.3 Pin Diagram (Top View)
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© 2011 ROHM Co., Ltd. All rights reserved.
4/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●Pin Description
Table 1 : Pin Description
Pin Name
Pin No.
Type
Descriptions
TA1P, TA1N
48, 49
LVDS OUT
TB1P, TB1N
46, 47
LVDS OUT
TC1P, TC1N
43, 44
LVDS OUT
TD1P, TD1N
39, 40
LVDS OUT
TCLK1P, TCLK1N
41, 42
LVDS OUT
TA2P, TA2N
36, 37
LVDS OUT
TB2P, TB2N
34, 35
LVDS OUT
TC2P TC2N
31, 32
LVDS OUT
TD2P, TD2N
27, 28
LVDS OUT
TCLK2P, TCLK2N
29, 30
LVDS OUT
R17～R10
60, 59, 58, 57, 54, 53, 52, 51
IN
G17～G10
68, 67, 66, 65, 64, 63, 62, 61
IN
B17～B10
78, 77, 76, 75, 74, 73, 70, 69
IN
R27～R20
86, 85, 84, 83, 82, 81, 80, 79
IN
G27～G20
96, 95, 94, 93, 92, 91, 90, 89
IN
B27～B20
6, 5, 2, 1, 100, 99, 98, 97
IN
DE
9
IN
DATA-ENABLE input.
VSYNC
8
IN
VSYNC input.
HSYNC
7
IN
HSYNC input.
CLKIN
10
IN
Clock Input.
MAP
14
IN
LVDS mapping table select.
See Table11-14 and Figure11-14.
XRST
19
IN
H : Normal operation,
L : Power down (all outputs are Hi-Z)
FLIP
21
IN
LVDS output pin select. See Table10.
LVDS data out
LVDS clock out
LVDS data out
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LVDS clock out
1ｓｔ Pixel data input.
2ｓｔ Pixel data inputs.
2011.12 - Rev.A
Technical Note
BU7988KVT
Pin Name
Pin No.
Type
Descriptions
LVDS swing mode, RS select.
RS
RS
12
LVDS Swing
IN
VDD
350mV
GND
200mV
Pixel Data Mode
MODE1 MODE0
MODE1, MODE0
15, 16
IN
Mode
L
L
Dual-in/Dual-out
L
H
Dual-in/Single-out
H
L
Single-in/Dual-out
H
H
Single-in/Single-out
SEL_BIT
18
IN
6bit/8bit color select.
*1
H:6bit (TDxP/N are Hi-Z), L：8bit.
OE
17
IN
Outputs enable.
H:Outputs enable,
L:Output disable (all outputs are Hi-Z)
RF
11
IN
Input Clock Triggering Select
H : Rising edge,
L : Falling edge
N/C
22
Reserved1
20
IN
Must be tied to GND
Reserved0
13
IN
Must be open
VDD
3, 55, 71, 87
Power
Power Supply Pins for CMOS inputs, output and
digital circuitry.
GND
4, 56, 72, 88
Ground
Ground Pins for CMOS inputs, outputs and digital
circuitry.
LVDS VDD
33, 45
Power
Power Supply Pins for LVDS Outputs.
LVDS GND
26, 38, 50
Ground
Ground Pins for LVDS Outputs.
PLL VDD
24
Power
Power Supply for PLL circuitry.
PLL GND
23, 25
Ground
Ground Pin for PLL circuitry.
Must be open
*1: X=1,2
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© 2011 ROHM Co., Ltd. All rights reserved.
6/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●Electrical characteristics
■Rating
Table 2 : Absolute Maximum Rating
Rating
Parameter
Symbol
Min
Max
Units
Supply Voltage
VDD
-0.3
4.0
V
Input Voltage
VIN
-0.3
VDD+0.3
V
VOUT
-0.3
VDD+0.3
V
Tstg
-55
125
℃
Output Voltage
Storage Temperature Range
Table 3 : Package Power
PACKAGE
Power Dissipation (mW)
De-rating (mW/℃) *1
900
9.0
1400*2
14.0*2
TQFP100V
*1:
*2:
At temperature Ta >25℃
Package power when mounting on the PCB board.
The size of PCB board :70×70×1.6(mm3)
The material of PCB board : The FR4 glass epoxy board.(3% or less copper foil area)
(It is recommended to apply the above package power requirement to PCB board when the small swing input mode is used)
Table 4 : Recommended Operating Conditions
Parameter
Supply Voltage
Operating Temperature Range
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© 2011 ROHM Co., Ltd. All rights reserved.
Symbol
VDD
Rating
Units
Conditions
Min
Typ
Max
3.0
3.3
3.6
V
VDD,LVDSVDD,PLLVDD
-20
-
85
℃
0
-
70
℃
Clock frequency
from 8MHz up to 90MHz
Clock frequency
from 90MHz up to 112MHz
Topr
7/27
2011.12 - Rev.A
Technical Note
BU7988KVT
■DC characteristics
Table 5 : CMOS DC Specifications(VDD=3.0V～3.6V, Ta=-20℃～+85℃)
Limits
Parameter
Symbol
Min
Typ
Max
Units
High Level Input Voltage
VIH
VDD×0.8
-
VDD
V
Low Level Input Voltage
VIL
GND
-
VDD×0.2
V
Input Leak Current
IINC
-10
-
+10
μA
Conditions
0V≤ VIN≤ VDD
Table 6 : LVDS Transmitter DC Specifications(VDD=3.0V～3.6V, Ta=-20℃～+85℃)
Limits
Parameter
Symbol
Units
Min
Typ
Max
Conditions
Normal swing
RS=VDD
Reduced swing
RS=GND
250
350
450
mV
120
200
300
mV
ΔVOD
-
-
35
mV
VOC
1.125
1.25
1.375
V
Change in VOC between
complementary output states
ΔVOC
-
-
35
mV
Output Short Circuit Current
IOS
-
-
-24
mA
VOUT=0V, RL=100Ω
Output TRI-STATE Current
IOZ
-10
-
+10
μA
XRST=0V, VOUT=0V to VDD
Differential Output Voltage
Change in VOD between
complementary output states
Common Mode Voltage
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© 2011 ROHM Co., Ltd. All rights reserved.
VOD
RL=100Ω
8/27
RL=100Ω
2011.12 - Rev.A
Technical Note
BU7988KVT
■Supply Current
Table 7 : Supply Current (VDD=3.3V, Ta=25℃,RL=100Ω,CL=15pF)
Parameter
Symbol
Rating
Min
Typ
Max
-
98
-
-
70
-
Units
MODE[1:0]=L L
87
-
MODE[1:0]=H L CLKIN = 150MHz
-
62
-
MODE[1:0]=H H CLKIN = 112MHz
-
76
-
MODE[1:0]=L L
-
57
-
ITCCG
CLKIN = 112MHz
MODE[1:0]=L H CLKIN = 56MHz
RS=L
-
67
-
MODE[1:0]=H L CLKIN = 150MHz
-
49
-
MODE[1:0]=H H CLKIN = 112MHz
-
101
-
MODE[1:0]=L L
-
87
-
CLKIN = 112MHz
MODE[1:0]=L H CLKIN = 56MHz
mA
RS=H
-
91
-
MODE[1:0]=H L CLKIN = 150MHz
-
65
-
MODE[1:0]=H H CLKIN = 112MHz
-
79
-
MODE[1:0]=L L
-
63
-
ITCCW
ITCCS
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© 2011 ROHM Co., Ltd. All rights reserved.
CLKIN = 112MHz
MODE[1:0]=L H CLKIN = 56MHz
mA
Transmitter Power Down
Supply Current
RS=H
-
mA
Transmitter Supply Current
(Worst Case pattern)
CLKIN = 112MHz
MODE[1:0]=L H CLKIN = 56MHz
mA
Transmitter Supply Current
(Gray Scale Pattern)
Conditions
RS=L
-
68
-
MODE[1:0]=H L CLKIN = 150MHz
-
55
-
MODE[1:0]=H H CLKIN = 112MHz
-
-
10
9/27
μA
XRST=L
2011.12 - Rev.A
Technical Note
BU7988KVT
Gray Scale Pattern
CLK_IN
Rx0/Gx0/Bx0
Rx1/Gx1/Bx1
Rx2/Gx2/Bx2
Rx3/Gx3/Bx3
Rx4/Gx4/Bx4
Rx5/Gx5/Bx5
Rx6/Gx6/Bx6
Rx7/Gx7/Bx7
x=1.2
Fig.4 Gray scale pattern
Worst Case Pattern (Maximum Power condition)
CLK_IN
Rx0/Gx0/Bx0
Rx1/Gx1/Bx1
Rx2/Gx2/Bx2
Rx3/Gx3/Bx3
Rx4/Gx4/Bx4
Rx5/Gx5/Bx5
Rx6/Gx6/Bx6
Rx7/Gx7/Bx7
x=1.2
Fig.5
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© 2011 ROHM Co., Ltd. All rights reserved.
Worst Case Pattern
10/27
2011.12 - Rev.A
Technical Note
BU7988KVT
■AC characteristics
Table 8 : Switching Characteristics (VDD=3.3V, Ta=25℃)
Parameter
Symbol
Min
Typ
Max
Units
tTCIT
-
-
5.0
ns
8.9
-
125.0
ns
17.8
-
62.5
Single In / Dual Out
6.7
-
250.0
Single In / Single Out
8.9
CLK IN Transition time
Dual In /Dual Out
Dual In / Single Out
CLK IN Period
tTCP
125.0
CLK IN High Time
tTCH
0.35tTCP
0.5tTCP
0.65tTCP
ns
CLK IN Low Time
tTCL
0.35tTCP
0.5tTCP
0.65tTCP
ns
-
TBD
-
ns
-
TBD
-
-
TBD
-
Dual In /Dual Out
Single In/Single Out
CLK IN to TCLK+/-Delay
Dual In / Single Out
tTCD
Single In / Dual Out
CMOS Data Setup to CLK IN
tTS
2.5
-
-
ns
CMOS Data Hold from CLK IN
tTH
0
-
-
ns
8.9
-
125.0
8.9
-
125.0
Single In / Dual Out
13.3
-
125.0
Single In / Single Out
8.9
Dual In /Dual Out
Dual In / Single Out
CLK OUT Period
tTCOP
125.0
LVDS Transition Time
tLVT
-
0.6
1.5
ns
Output Data Position 0
tTOP1
-0.2
0.0
+0.2
ns
Output Data Position 1
tTOP0
Output Data Position 2
tTOP6
Output Data Position 3
tTOP5
Output Data Position 4
tTOP4
Output Data Position 5
tTOP3
Output Data Position 6
tTOP2
tTCP
-0.2
7
tTCP
2
-0.2
7
tTCP
3
-0.2
7
tTCP
-0.2
4
7
tTCP
5
-0.2
7
tTCP
6
-0.2
7
tTCP
7
tTCP
2
7
tTCP
3
7
tTCP
4
7
tTCP
5
7
tTCP
6
7
tTCP
+0.2
7
tTCP
2
+0.2
7
tTCP
3
+0.2
7
tTCP
4
+0.2
7
tTCP
5
+0.2
7
tTCP
6
+0.2
7
Skew Time between TCLKXP and TCLKYP
Tck12
-
-
0.5
ns
Phase Lock Loop Set Time
tTPLL
-
-
10.0
ms
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© 2011 ROHM Co., Ltd. All rights reserved.
11/27
ns
ns
ns
ns
ns
ns
2011.12 - Rev.A
Technical Note
BU7988KVT
●AC Timing
■AC Timing Diagrams
LVCMOS Input
90%
CLK IN
90%
10%
10%
LVDS Output
tTCIT
tTCIT
Vdiff=(TAP)-(TAN)
80%
80%
TAP
5pF
Vdiff
100O
20%
TAN
LVDS Output Load
20%
tLVT
tLVT
LVCMOS Input
tTCP
tTCH
CLKIN VDD/2
VDD/2
VDD/2
tTCP
Rxn/Gxn/
Bxn
HSYNC,
VSYNC,DE
tTCH
VDD/2
RF=L
RF=H
tTH
VDD/2
tTCD
TCLK1/2P
VOC
TCLK1/2N
x=1, 2
y=0-7
Fig.6 AC Timing Diagrams
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12/27
2011.12 - Rev.A
Technical Note
BU7988KVT
■
AC Timing Diagrams
tTOP2
tTOP3
tTOP4
tTOP5
tTOP6
tTOP0
tTOP1
Tyx+/-
Tyx6
Tyx5
Tyx4
Tyx3
Tyx2
Tyx1
Tyx0
Tyx6
Tyx5
Tyx4
Tyx2
Tyx1
Vdiff = 0V
Vdiff = 0V
TCLK1+
Tyx3
tTCOP
Vdiff = 0V
TCLK1P+
tCK12
TCLK2P+
Vdiff = 0V
Note:
Vdiff = (Tyx+) – (Tyx-), (TCLK1P) –
(TCLK1N)
Fig.7 AC Timing Diagrams
■Phase Lock Loop Set Time
XRST
V DD /2
3.6V
3.0V
VDD
t TPLL
CLKIN
V diff=0V
TCLKP/N
Fig.8 Phase Lock Loop Set Time
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13/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●Pixel Map Table for Dual Link
Table 9 : Pixel Map Table for Dual Link
1st Pixel Data
2nd Pixel Data
TFT Panel Data
TFT Panel Data
BU7988KVT Input
18Bit
R20
-
R20
R11
R21
-
R21
R10
R12
R22
R20
R22
R13
R11
R13
R23
R21
R23
R14
R12
R14
R24
R22
R24
R15
R13
R15
R25
R23
R25
R16
R14
R16
R26
R24
R26
MSB
R17
R15
R17
MSB
R27
R25
R27
LSB
G10
-
G10
LSB
G20
-
G20
G11
-
G11
G21
-
G21
G12
G10
G12
G22
G20
G22
G13
G11
G13
G23
G21
G23
G14
G12
G14
G24
G22
G24
G15
G13
G15
G25
G23
G25
G16
G14
G16
G26
G24
G26
MSB
G17
G15
G17
MSB
G27
G25
G27
LSB
B10
-
B10
LSB
B20
-
B20
B11
-
B11
B21
-
B21
B12
B10
B12
B22
B20
B22
B13
B11
B13
B23
B21
B23
B14
B12
B14
B24
B22
B24
B15
B13
B15
B25
B23
B25
B16
B14
B16
B26
B24
B26
B17
B15
B17
B27
B25
B27
MSB
18Bit
R10
-
R10
R11
-
R12
BU7988KVT Input
24Bit
LSB
24Bit
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© 2011 ROHM Co., Ltd. All rights reserved.
LSB
MSB
14/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVDS Data Output Table for Function of FLIP pin
Table 10 : LVDS Data Output Pin Name
Output Pin Names
Pin No
FLIP=L
FLIP=H
49
TA1N
TD2P
48
TA1P
TD2N
47
TB1N
TCLK2P
46
TB1P
TCLK2N
44
TC1N
TC2P
43
TC1P
TC2N
42
TCLK1N
TB2P
41
TCLK1P
TB2N
40
TD1N
TA2P
39
TD1P
TA2N
37
TA2N
TD1P
36
TA2P
TD1N
35
TB2N
TCLK1P
34
TB2P
TCLK1N
32
TC2N
TC1P
31
TC2P
TC1N
30
TCLK2N
TB1P
29
TCLK2P
TB1N
28
TD2N
TA1P
27
TD2P
TA1N
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15/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Input Timing for Dual Link
Example : SXGA+(1400×1050)
HSYNC
DE
C L K _IN
R 1x/G 1x/B 1x
#1
#3
#5
#7
1395
#1397
#1399
R 2x/G 2x/B 2x
#2
#4
#6
#8
1396
#1398
#1400
#1
#2
#1399
#1400
x=0～ 9
TFT P anel
(1 4 0 0 × 1 0 5 0 )
Fig.9 LVCMOS Data Input Timing for Dual Link
●LVCMOS Data Input Timing for Single Link
Example : SXGA+(1400×1050)
HSYNC
DE
C L K _IN
R 1x/G 1x/B 1x
#1
#2
#1
#2
#3
#4
1398
#1399
#1400
#1399
#1400
x=0～ 9
TFT P anel
(1 4 0 0 × 1 0 5 0 )
Fig.10 LVCMOS Data Input Timing for Single Link
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© 2011 ROHM Co., Ltd. All rights reserved.
16/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVDS Output Data Mapping (Dual Link / Single Link)
Previous Cycle
Current Cycle
TCLK1+
TA1+/-
TA14-1 TA13-1 TA12-1 TA11-1 TA10-1 TA16
TA15
TA14
TA13
TA12
TA11
TA10
TA16+1
TB1+/-
TB14-1 TB13-1 TB12-1 TB11-1 TB10-1 TB16
TB15
TB14
TB13
TB12
TB11
TB10
TB16+1
VSYNC HSYNC TC13
TC12
TC11
TC10
DE+1
TD15
TD14
TD13
TD12
TD11
TD10
L
TC1/-
HSYNC-1
TD1+/-
TD13-1 TD12-1 TC11-1 TC10-1
TD14-1 TD13-1 TD12-1 TD11-1 TD10-1
DE
L
TCLK2+
TA2+/-
TA24-1 TA23-1 TA22-1 TA21-1 TA20-1 TA26
TA25
TA24
TA23
TA22
TA21
TA20
TA26+1
TB2+/-
TB24-1 TB23-1 TB22-1 TB21-1 TB20-1 TB26
TB25
TB24
TB23
TB22
TB21
TB20
TB26+1
TC2+/-
HSYNC-1
VSYNC HSYNC TC23
TC22
TC21
TC20
DE+1
TD2+/-
TD24-1 TD23-1 TD22-1 TD21-1 TD20-1
TD25
TD22
TD21
TD20
L
TD23-1 TD22-1 TC21-1 TC20-1
DE
L
TD24
TD23
LVDS Data Output
R1n,~ B1
nn=0~ 7
R2n,~ B2n
n=0~ 7
DATA1n
-1
DATA2n-1
DATA1n
DATA2n
DATA1n
+1
DATA2n+1
VDD
GND
VDD
GND
LVCMOS Data Input
Fig.11 LVDS Output Data Mapping
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
17/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing in Dual Link
Dual-in / Dual-out Mode (MODE=LL , FLIP=L)
Table 11 : LVCMOS Data Inputs Timing Diagrams in Dual Link
1st Pixel Data
2nd Pixel Data
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
LVDS
Output Data
(2nd Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
TA10
R12
R10
TA20
R22
R20
TA11
R13
R11
TA21
R23
R21
TA12
R14
R12
TA22
R24
R22
TA13
R15
R13
TA23
R25
R23
TA14
R16
R14
TA24
R26
R24
TA15
R17
R15
TA25
R27
R25
TA16
G12
G10
TA26
G22
G20
TB10
G13
G11
TB20
G23
G21
TB11
G14
G12
TB21
G24
G22
TB12
G15
G13
TB22
G25
G23
TB13
G16
G14
TB23
G26
G24
TB14
G17
G15
TB24
G27
G25
TB15
B12
B10
TB25
B22
B20
TB16
B13
B11
TB26
B23
B21
TC10
B14
B12
TC20
B24
B22
TC11
B15
B13
TC21
B25
B23
TC12
B16
B14
TC22
B26
B24
TC13
B17
B15
TC23
B27
B25
TC14
HSYNC
HSYNC
TC24
HSYNC
HSYNC
TC15
VSYNC
VSYNC
TC25
VSYNC
VSYNC
TC16
DE
DE
TC26
DE
DE
TD10
R10
R16
TD20
R20
R26
TD11
R11
R17
TD21
R21
R27
TD12
G10
G16
TD22
G20
G26
TD13
G11
G17
TD23
G21
G27
TD14
B10
B16
TD24
B20
B26
TD15
B11
B17
TD25
B21
B27
TD16
L
L
TD26
L
L
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
18/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing Diagrams in Dual Link
Dual-in / Dual-out Mode
(MODE=LL, FLIP=L, MAP=H)
Previous Cycle
Current Cycle
TCLK1+
TA1+/-
R16-1 R15-1 R14-1 R13-1 R12-1 G12
R17
R16
R15
R14
R13
R12 G12+1
TB1+/-
G17-1 G16-1 G15-1 G14-1 G13-1 B13
B12
G17
G16
G15
G14
G13 B13+1
B17-1 B16-1 B15-1 B14-1
DE
VSYNC
HSYNC
B17
B16
B15
B14
DE+1
L
B11
B10
G11
G10
R11
R10
L
TC1/-
TD1+/-
HSYNC-1
B10-1 G11-1 G10-1 R11-1 R10-1
TCLK2+
TA2+/-
R26-1 R25-1 R24-1 R23-1 R22-1 G22
R27
R26
R25
R24
R23
R22 G22+1
TB2+/-
G27-1 G26-1 G25-1 G24-1 G23-1 B23
B22
G27
G26
G25
G24
G23 B23+1
TC2+/-
HSYNC-1
B27-1 B26-1 B25-1 B24-1
DE
VSYNC
HSYNC
B27
B26
B25
B24
DE+1
TD2+/-
B20-1 G21-1 G20-1 R21-1 R20-1
L
B21
B20
G21
G20
R21
R20
L
LVDS Data Output
R1n,~ B1
nn=0~ 7
R2n,~ B2n
n=0~ 7
DATA1n
-1
DATA2n-1
DATA1n
DATA2n
DATA1n
+1
DATA2n+1
VDD
GND
VDD
GND
LVCMOS Data Input
Fig.12 LVCMOS Data Inputs Timing Diagrams in Dual Link
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
19/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing in Single Link
Dual-in / Single-out Mode (MODE=LH, FLIP=L)
Table 12 : LVCMOS Data Inputs Timing Diagrams in Dual Link
LVDS
Output Data
(1st Pixel Data)
Mapping Mode1
(Input Pin Name)
Mapping Mode2
(Input Pin Name)
TA10
R12/R22
R10/R20
TA11
R13/R23
R11/R21
TA12
R14/R24
R12/R22
TA13
R15/R25
R13/R23
TA14
R16/R26
R14/R24
TA15
R17/R27
R15/R25
G10/G20
TA16
G12/G22
TB10
G13/G23
G11/G21
TB11
G14/G24
G12/G22
TB12
G15/G25
G13/G23
TB13
G16/G26
G14/G24
TB14
G17/G27
G15/G25
TB15
B12/B22
B10/B20
TB16
B13/B23
B11/B21
TC10
B14/B24
B12/B22
TC11
B15/B25
B13/B23
TC12
B16/B26
B14/B24
TC13
B17/B27
B15/B25
TC14
HSYNC
HSYNC
TC15
VSYNC
VSYNC
TC16
DE
DE
TD10
R10/R20
R16/R26
TD11
R11/R21
R17/R27
TD12
G10/G20
G16/G26
TD13
G11/G21
G17/G27
TD14
B10/B20
B16/B26
TD15
B11/B21
B17/B27
TD16
L
L
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
20/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing Diagrams in Single Link
Dual-in / Single-out Mode (MODE=LH, FLIP=L, MAP=H)
Previous Cycle
(2nd Pixel Data)
Current Cycle
(1st Pixel Data)
TCLK1+
TA1+/-
R26-1 R25-1 R24-1 R23-1 R22-1 G12
R17
R16
R15
R14
R13
R12
G22
TB1+/-
G27-1 G26-1 G25-1 G24-1 G23-1 B13
B12
G17
G16
G15
G14
G13
B23
VSYNC
HSYNC
B17
B16
B15
B14
DE
B11
B10
G11
G10
R11
R10
L
TC1/-
TD1+/-
HSYNC-1
B27-1 B26-1 B25-1 B24-1 DE
B20-1 G21-1 G20-1 R21-1 R20-1
L
LVDS Data Output
R1n,~ B1
nn=0~ 7
R2n,~ B2n
n=0~ 7
DATA1n
-1
DATA2n-1
DATA1n
DATA2n
DATA1n
+1
DATA2n+1
VDD
GND
VDD
GND
LVCMOS Data Input
Fig.13 LVCMOS Data Inputs Timing Diagrams in Single Link
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
21/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing in Single Link
Single-in / Dual-out Mode (MODE=HH, FLIP=L)
Table 13 : LVCMOS Data Inputs Timing Diagrams in Single Link
1st Pixel Data
2nd Pixel Data
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
TA10
R12
R10
TA20
R12+1
R10+1
TA11
R13
R11
TA21
R13+1
R11+1
+1
R12+1
TA12
R14
R12
TA22
R14
TA13
R15
R13
TA23
R15+1
R13+1
TA14
R16
R14
TA24
R16+1
R14+1
+1
R15+1
TA15
R17
R15
TA25
R17
TA16
G12
G10
TA26
G12+1
G10+1
TB10
G13
G11
TB20
G13+1
G11+1
+1
G12+1
TB11
G14
G12
TB21
G14
TB12
G15
G13
TB22
G15+1
G13+1
TB13
G16
G14
TB23
G16+1
G14+1
+1
G15+1
TB14
G17
G15
TB24
G17
TB15
B12
B10
TB25
B12+1
B10+1
TB16
B13
B11
TB26
B13+1
B11+1
+1
B12+1
TC10
B14
B12
TC20
B14
TC11
B15
B13
TC21
B15+1
B13+1
TC12
B16
B14
TC22
B16+1
B14+1
+1
B15+1
TC13
B17
B15
TC23
B17
TC14
HSYNC
HSYNC
TC24
HSYNC+1
HSYNC+1
TC15
VSYNC
VSYNC
TC25
VSYNC+1
VSYNC+1
+1
DE+1
TC16
DE
DE
TC26
DE
TD10
R10
R16
TD20
R10+1
R16+1
TD11
R11
R17
TD21
R11+1
R17+1
+1
+1
TD12
G10
G16
TD22
G10
TD13
G11
G17
TD23
G11+1
G17+1
TD14
B10
B16
TD24
B10+1
B16+1
+1
B17+1
TD15
B11
B17
TD25
B11
TD16
L
L
TD26
L
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
22/27
G16
L
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing in Dual Link
Single-in / Dual-out Mode (MODE=HL, FLIP=L, MAP=H)
Previous Cycle
Current Cycle
TCLK1+
TA1+/-
R16-2 R15-2 R14-2 R13-2 R12-2 G12
R17
R16
R15
R14
R13
R12 G12+2
TB1+/-
G17-2 G16-2 G15-2 G14-2 G13-2 B13
B12
G17
G16
G15
G14
G13 B13+2
VSYNC
HSYNC
B17
B16
B15
B14
DE+2
B11
B10
G11
G10
R11
R10
L
TC1/-
TD1+/-
HSYNC-2
B17-2 B16-2 B15-2 B14-2 DE
B10-2 G11-2 G10-2 R11-2 R10-2
L
TCLK2+
TA2+/-
R16-1 R15-1 R14-1 R13-1 R12-1 G12+1 R17+1 R16+1 R15+1 R14+1 R13+1 R12+1 G12+3
TB2+/-
G17-1 G16-1 G15-1 G14-1 G13-1 B13+1 B12+1 G17+1 G16+1 G15+1 G14+1 G13+1 B13+3
TC2+/-
HSYNC-1
TD2+/-
B10-1 G11-1 G10-1 R11-1 R10-1
B17-1 B16-1 B15-1 B14-1 DE+1
L
VSYNC+1 HSYNC+1
B17+1 B16+1 B15+1 B14+1 DE+3
B11+1 B10+1 G11+1 G10+1 R11+1 R10+1
L
LVDS Data Output
R1n,G1n,B1n
(n=0~7)
-2
DATA1n
-1
DATA1n
DATA1n
+1
DATA1n
+2
DATA1n
+3
DATA1n
VDD
GND
LVCMOS Data Input
Fig.14 LVCMOS Data Inputs Timing in Dual Link
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
23/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing in Single Link
Single-in / Single-out Mode (MODE=HH, FLIP=L)
Table 14 : LVCMOS Data Inputs Timing Diagrams in Single Link
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
TA10
R12
R10
TA11
R13
R11
TA12
R14
R12
TA13
R15
R13
TA14
R16
R14
TA15
R17
R15
TA16
G12
G10
TB10
G13
G11
TB11
G14
G12
TB12
G15
G13
TB13
G16
G14
TB14
G17
G15
TB15
B12
B10
TB16
B13
B11
TC10
B14
B12
TC11
B15
B13
TC12
B16
B14
TC13
B17
B15
TC14
HSYNC
HSYNC
TC15
VSYNC
VSYNC
TC16
DE
DE
TD10
R10
R16
TD11
R11
R17
TD12
G10
G16
TD13
G11
G17
TD14
B10
B16
TD15
B11
B17
TD16
L
L
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
24/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●LVCMOS Data Inputs Timing Diagrams in Single Link
Single-in / Single-out Mode (MODE=HH, FLIP=L, MAP=H)
Previous Cycle
Current Cycle
TCLK1+
TA1+/-
R16-1 R15-1 R14-1 R13-1 R12-1 G12
R17
R16
R15
R14
R13
R12
G12+1
TB1+/-
G17-1 G16-1 G15-1 G14-1 G13-1 B13
B12
G17
G16
G15
G14
G13
B13+1
B17-1 B16-1 B15-1 B14-1
DE
VSYNC
HSYNC
B17
B16
B15
B14
DE+1
L
B11
B10
G11
G10
R11
R10
L
TC1/-
TD1+/-
HSYNC-1
B10-1 G11-1 G10-1 R11-1 R10-1
LVDS Data Output
R1n,G1n,B1n
(n=0~ 7)
DATA1n-1
DATA1n
DATA1n+1
VDD
GND
LVCMOS Data Input
Fig.15 LVCMOS Data Inputs Timing Diagrams in Single Link
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
25/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●About the Power On Reset
Power On Reset is not mandatory for this device.
(The PD pin should be set to high level when Power On Reset procedure is not used.)
VDD
XRST
BU7988KVT
Fig.16 terminal connection when Power On Reset is not used
However, Power On Reset procedure is strongly recommend for internal logic initialization by following two methods.
① The method of using CR circuit.
② The method of using external specific IC.
It is recommend to do enough examination for target application.
VDD
VDD
schottky barrier diode
10KO
VDD
VT+
XRST
220O
Be careful of temperature of
the capacitor especially over
and again.
B characteristic ceramics and
polymer aluminum
are recommended.
XRST
Internal Reset
2.2µF
td
td is approximately equal to 20ms when the left RC coleus are applied.
Fig.17 Power On Reset by external a CR circuit
VDD
VDD
power on IC
(open drain
output)
VDD
Detection voltage
VDD
220KO
XRST
VOUT
VT+
XRST
0.1µF
GND
B Characteristic
ceramics
Internal Reset
td
Fig.18 Power On Reset by specific
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
26/27
2011.12 - Rev.A
Technical Note
BU7988KVT
●Ordering Part Number
B
U
7
Part No.
9
8
8
K
V
T
Part No.
Packaging and forming specification
None:Tray
Package
KVT: TQFP100V
TQFP100V
16.0±0.3
14.0±0.2
50
100
26
14.0±0.2
Tray (with dry pack)
Quantity
500pcs
Direction of feed
Direction of product is fixed in a tray
1pin
0.5
16.0±0.3
76
1
25
0.125±0.1
1.0±0.1
0.1±0.1
1.2Max.
Container
51
75
0.1
0.5
0.2±0.1
∗ Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
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© 2011 ROHM Co., Ltd. All rights reserved.
27/27
2011.12 - Rev.A
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
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Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
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© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001
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