STD40N2LH5

STD40N2LH5 STU40N2LH5 N-channel 25 V, 0.01 Ω, 40 A, DPAK, IPAK STripFET™ V Power MOSFET Features Type STD40N2LH5 STU40N2LH5 ■ ■ ■ ■ ■ VDSS 25 V 25 V RDS(on) max 0.0118 Ω 0.0124 Ω ID 40 A 40 A 3 1 3 2 1 RDS(on) * Qg industry benchmark Extremely low on-resistance RDS(on) Very low switching gate charge High avalanche ruggedness Low gate drive power losses DPAK IPAK Application ■ Switching applications Figure 1. Internal schematic diagram Description This STripFET™ V Power MOSFET technology is among the latest improvements, which have been especially tailored to achieve very low onstate resistance providing also one of the best-inclass figure of merit (FOM). Table 1. Device summary Marking 40N2LH5 40N2LH5 Package DPAK IPAK Packaging Tape and reel Tube Order codes STD40N2LH5 STU40N2LH5 September 2009 Doc ID 14919 Rev 3 1/15 www.st.com 15 Contents STD40N2LH5, STU40N2LH5 Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 4 5 6 Test circuits .............................................. 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Electrical ratings 1 Electrical ratings Table 2. Symbol VDS VGS ID ID IDM (1) Absolute maximum ratings Parameter Drain-source voltage (VGS=0) Gate-Source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Derating factor Value 25 ± 22 40 28 160 35 0.23 110 -55 to 175 Unit V V A A A W W/°C mJ °C PTOT EAS (2) Tj Tstg Single pulse avalanche energy Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. Starting Tj = 25 °C, ID = 24 A, VDD = 12 V Table 3. Symbol Rthj-case Rthj-amb Tl Thermal resistance Parameter Thermal resistance junction-case max Thermal resistance junction-case max Maximum lead temperature for soldering purpose Value 4.3 100 275 Unit °C/W °C/W °C Doc ID 14919 Rev 3 3/15 Electrical characteristics STD40N2LH5, STU40N2LH5 2 Electrical characteristics (TCASE = 25°C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) Static Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Test conditions ID = 250 µA, VGS= 0 VDS = 25 V VDS = 25 V, TC = 125 °C VGS = ± 22 V VDS= VGS, ID = 250 µA VGS= 10 V, ID= 20 A SMD version 1 0.01 0.0118 Min. 25 1 10 ±100 Typ. Max. Unit V µA µA nA V Ω Ω Ω Ω RDS(on) Static drain-source on resistance VGS= 10 V, ID= 20 A VGS= 5 V, ID= 20 A SMD version VGS= 5 V, ID= 20 A 0.0106 0.0124 0.0135 0.0155 0.0141 0.0161 Table 5. Symbol Ciss Coss Crss Qg Qgs Qgd Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 700 160 27 6.3 2.4 2.7 Max. Unit pF pF pF nC nC nC VDS = 20 V, f=1 MHz, VGS = 0 VDD=15 V, ID = 40 A VGS = 5 V (Figure 14) - - - - Table 6. Symbol td(on) tr td(off) tf Switching on/off (resistive load) Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 10 V, ID= 20 A, RG= 4.7 Ω, VGS= 10 V (Figure 13 and Figure 18) VDD= 10 V, ID= 20 A, RG= 4.7 Ω, VGS= 10 V (Figure 13 and Figure 18) Min. Typ. 4.8 13.6 17.6 3.5 Max. Unit ns ns ns ns - - - - 4/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Electrical characteristics Table 7. Symbol ISD ISDM VSD trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed)(1) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 20 A, VGS=0 ISD= 40 A, di/dt =100 A/µs, VDD= 20 V, Tj = 25 °C (Figure 15) Test conditions Min. 17.6 9.2 1 Typ. Max. 40 160 1.1 Unit A A V ns nC A - 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% Doc ID 14919 Rev 3 5/15 Electrical characteristics STD40N2LH5, STU40N2LH5 2.1 Figure 2. ID (A) Electrical characteristics (curves) Safe operating area AM05425v1 Figure 3. Thermal impedance 100 O Li per m at ite io d ni by n m this ax a R rea D S( on ) is 100µs 1ms 10ms 10 1 Tj=150°C Tc=25°C Sinlge pulse 0.1 0.1 1 10 100 VDS(V) Figure 4. ID (A) 120 100 80 60 Output characteristics AM05426v1 Figure 5. ID (A) 100 80 5V 60 4V 40 20 3V 0 0 Transfer characteristics AM05427v1 VGS=10V VDS=3V 40 20 0 0 1 2 3 4 VDS(V) 2 4 6 8 10 VGS(V) Figure 6. BVDSS (norm) 1.10 Normalized BVDSS vs temperature AM05429v1 Figure 7. RDS(on) (mΩ) 14.0 12.0 10.0 8.0 Static drain-source on resistance AM05428v1 ID=20A VGS=10V 1.05 1.00 6.0 4.0 0.95 2.0 0.90 -50 -25 0 25 50 75 100 125 150 TJ(°C) 0.0 0 10 20 30 40 ID(A) 6/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Figure 8. VGS (V) 12 10 8 6 100 4 2 0 0 10 2 4 6 8 10 Qg(nC) 5 VDD=12.5V ID=40A 1000 Electrical characteristics Capacitance variations AM05431v1 Gate charge vs gate-source voltage Figure 9. AM05430v1 C (pF) Ciss Coss Crss 10 15 20 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature VGS(th) (norm) 1.2 1.1 1.0 0.9 AM05432v1 Figure 11. Normalized on resistance vs temperature RDS(on) (norm) 1.9 1.7 1.5 1.3 AM05433v1 0.8 0.7 0.6 0.5 0.4 -50 -25 0 25 50 75 100 125 150 TJ(°C) 1.1 0.9 0.7 0.5 -50 -25 0 25 50 75 100 125 150 TJ(°C) Figure 12. Source-drain diode forward characteristics VSD (V) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0 5 10 15 20 25 30 35 40 ISD(A) TJ=25°C TJ=150°C AM05434v1 TJ=-55°C Doc ID 14919 Rev 3 7/15 Test circuits STD40N2LH5, STU40N2LH5 3 Test circuits Figure 14. Gate charge test circuit VDD 12V 2200 Figure 13. Switching times test circuit for resistive load 47kΩ 100nF 1kΩ RL VGS VD RG PW D.U.T. µF 3.3 µF VDD Vi=20V=VGMAX 2200 µF IG=CONST 2.7kΩ 47kΩ PW 1kΩ 100Ω D.U.T. VG AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit A D G S B 25 Ω D.U.T. A FAST DIODE B A L=100µH B D G 3.3 µF 1000 µF L VD 2200 µF 3.3 µF VDD VDD ID RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform V(BR)DSS VD Figure 18. Switching time waveform ton tdon tr toff tdoff tf 90% IDM 90% 10% ID VDD VDD 0 10% VDS 90% VGS AM01472v1 0 10% AM01473v1 8/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Figure 19. Gate charge waveform Test circuits Doc ID 14919 Rev 3 9/15 Package mechanical data STD40N2LH5, STU40N2LH5 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Package mechanical data TO-251 (IPAK) mechanical data mm. DIM. A A1 b b2 b4 c c2 D E e e1 H L (L1) L2 V1 9.00 0.80 0.80 10 o 4.40 16.10 9.40 1.20 5.20 0.45 0.48 6.00 6.40 2.28 4.60 min. 2.20 0.90 0.64 typ max. 2.40 1.10 0.90 0.95 5.40 0.60 0.60 6.20 6.60 0068771_H Doc ID 14919 Rev 3 11/15 Package mechanical data STD40N2LH5, STU40N2LH5 TO-252 (DPAK) mechanical data DIM. A A1 A2 b b4 c c2 D D1 E E1 e e1 H L L1 L2 L4 R V2 0o 0.60 0.20 8o 4.40 9.35 1 2.80 0.80 1 6.40 4. 70 2.28 4.60 10.10 mm. min. 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 5.10 6.60 ty p ma x . 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 0068772_G 12/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Packaging mechanical data 5 Packaging mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W BASE QTY 2500 mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 16.3 inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574 0.618 0.641 MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1 Doc ID 14919 Rev 3 13/15 Revision history STD40N2LH5, STU40N2LH5 6 Revision history Table 8. Date 24-Jul-2008 23-Sep-2008 10-Sep-2009 Document revision history Revision 1 2 3 Initial release VGS value has been changed on Table 2 and Table 5 Document status promoted from preliminary data to datasheet. Changes 14/15 Doc ID 14919 Rev 3 STD40N2LH5, STU40N2LH5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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