STH180N10F3-2

STH180N10F3-2 Datasheet N‑channel 100 V, 3.9 mΩ typ., 180 A STripFET F3 Power MOSFET in H²PAK‑2 package Features TAB 2 • • 3 1 H2PAK-2 Order code VDS RDS(on) max. ID STH180N10F3-2 100 V 4.5 mΩ 180 A Ultra low on-resistence 100% avalanche tested Applications • Switching applications D(TAB) Description This device is an N-channel Power MOSFET developed using STripFET F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. G(1) S(2,3) NCHG1DTABS23 Product status link STH180N10F3-2 Product summary Order code STH180N10F3-2 Marking 180N10F3 Package H2PAK-2 Packing Tape and reel DS7317 - Rev 3 - March 2022 For further information contact your local STMicroelectronics sales office. www.st.com STH180N10F3-2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ± 20 V Drain current (continuous) at TC = 25 °C 180 A ID (1) Drain current (continuous) at TC = 100 °C 120 A IDM (2) Drain current (pulsed) 720 A Total power dissipation at TC = 25 °C 315 W Derating factor 2.1 W/ºC Peak diode recovery voltage slope 20 V/ns EAS (3) Single pulse avalanche energy 350 mJ TJ Operating junction temperature ID (1) PTOT dv/dt Tstg -55 to 175 Storage temperature °C °C 1. Current limited by package 2. Pulse width limited by safe operating area 3. Starting TJ = 25 °C, ID = 80, VDD = 50 V Table 2. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance, junction-to-case 0.48 °C/W RthJB (1) Thermal resistance, junction-to-board 35 °C/W 1. When mounted on FR-4 board of 1 inch², 2 oz Cu DS7317 - Rev 3 page 2/13 STH180N10F3-2 Electrical characteristics 2 Electrical characteristics TC= 25 °C unless otherwise specified. Table 3. On/off-state Symbol V(BR)DSS IDSS IGSS Parameter Test conditions Drain-source breakdown voltage (VGS= 0 V) Zero gate voltage drain current (VGS = 0 V) Gate body leakage current (VDS = 0 V) ID = 250 µA Min. Typ. Max. 100 Unit V VDS = 100 V 10 µA VDS = 100 V; TC = 125 °C 100 µA VGS = ±20 V ±200 nA 4 V 3.9 4.5 mΩ Typ. Max. Unit VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 60 A 2 Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Qgs Qgd Test conditions Min. VDS = 25 V, f = 1 MHz, VGS = 0 V 6665 pF 786 pF 49 - pF - Total gate charge VDD = 50 V, ID = 120 A Gate-source charge VGS = 10 V 38.8 nC Gate-drain charge See Figure 13. Test circuit for gate charge behavior 31.9 nC 114.6 nC Table 5. Switching times Symbol td(on) tr td(off) tf DS7317 - Rev 3 Parameter Turn-on delay time Test conditions RG = 4.7 Ω, VGS = 10 V Turn-off delay time See Figure 12. Test circuit for resistive load switching times Typ. Max. 25.6 VDD = 50 V, ID = 60 A, Rise time Fall time Min. - 97.1 99.9 6.9 Unit ns - ns ns ns page 3/13 STH180N10F3-2 Electrical characteristics Table 6. Source-drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current 180 A Source-drain current (pulsed) 720 A 1.5 V Forward on voltage ISD = 120 A, VGS = 0 V trr Reverse recovery time ISD = 120 A, 83.4 ns Qrr Reverse recovery charge di/dt = 100 A/µs, 295.7 nC IRRM Reverse recovery current VDD = 80 V, TJ = 150 °C 7.1 A - 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS7317 - Rev 3 page 4/13 STH180N10F3-2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance GIPG110620141143SA ID (A) 280tok K ᵟ=0.5 100 his t in a ion y m at er d b Op ite Lim 10 0.2 is ea ar (on) S D xR 0.1 100µs 0.05 -1 10 0.02 1ms Tj=175°C Tc=25°C Single pulse 0.1 0.1 1 Single pulse 10ms VDS(V) 10 Figure 3. Output characteristics ID (A) -4 VGS=10V Ƭ -1 10 10 tp (s) 10 AM08617v1 ID (A) 350 7V 300 250 250 200 200 150 6V 100 VDS=2V 150 100 50 50 5V 1 2 4 3 5 6 7 8 VDS(V) Figure 5. Normalized V(BR)DSS vs temperature AM08618v1 V(BR)DSS (norm) ID=1mA 0 0 RDS(on) (mΩ) 4.3 1.05 4.1 1.00 3.9 0.95 3.7 -25 25 75 125 175 TJ(°C) 1 2 3 4 5 6 7 8 9 VGS(V) Figure 6. Static drain-source on-resistance 1.10 0.90 -75 -2 -3 10 300 0 0 tp -2 10 -5 10 Figure 4. Transfer characteristics AM08616v1 350 DS7317 - Rev 3 Zth= k*R thJC δ = tp /Ƭ 0.01 1 3.5 0 AM08626v1 VGS=10V 20 40 60 80 100 120 140 160 180 ID(A) page 5/13 STH180N10F3-2 Electrical characteristics (curves) Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations AM08620v1 VGS (V) VDD=50V ID=120A 12 AM08621v1 C (pF) 20000 10 15000 8 6 10000 4 Ciss 5000 2 0 Crss 0 20 40 60 80 Figure 9. Normalized gate threshold voltage vs temperature 20 40 60 80 100 VDS(V) Figure 10. Normalized on-resistance vs temperature AM08623v1 RDS(on) AM08622v1 VGS(th) (norm) Coss 0 0 100 120 140 Qg(nC) (norm) ID=250µA ID=60A VGS=10V 2.1 1.3 1.9 1.7 1.1 1.5 0.9 1.3 1.1 0.7 0.9 0.5 0.3 -75 0.7 -25 25 75 0.5 -75 175 TJ(°C) 125 -25 25 75 125 175 TJ(°C) Figure 11. Source-drain diode forward characteristics AM08624v1 VSD (V) 1.0 TJ=-55°C 0.9 0.8 TJ=25°C 0.7 0.6 0.5 0.4 DS7317 - Rev 3 TJ=175°C 0 20 40 60 80 100 120 ISD(A) page 6/13 STH180N10F3-2 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A A L 100 µH fast diode B B B G RG VD 3.3 µF D + Figure 15. Unclamped inductive load test circuit 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S _ D.U.T. Vi pulse width AM01470v1 AM01471v1 Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD VDD VGS 0 AM01472v1 DS7317 - Rev 3 10% 0 ID VDS 10% 90% 10% AM01473v1 page 7/13 STH180N10F3-2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 H²PAK-2 package information Figure 18. H²PAK-2 package outline 8159712_9 DS7317 - Rev 3 page 8/13 STH180N10F3-2 H²PAK-2 package information Table 7. H²PAK-2 package mechanical data Dim. mm Min. Typ. Max. A 4.30 4.70 A1 0.03 0.20 C 1.17 1.37 D 8.95 9.35 e 4.98 5.18 E 0.50 0.90 F 0.78 0.85 F2 1.14 1.70 H 10.00 10.40 H1 7.40 J1 2.49 2.69 L 15.30 15.80 L1 1.27 1.40 L2 4.93 5.23 L3 6.85 7.25 L4 1.50 1.70 M 2.60 2.90 R 0.20 0.60 V 0° 8° - 7.80 Figure 19. H²PAK-2 recommended footprint 8159712_9 Note: DS7317 - Rev 3 Dimensions are in mm. page 9/13 STH180N10F3-2 Packing information 4.2 Packing information Figure 20. Tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm P0 Top cover tape T P2 D E F W K0 B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v2 Figure 21. Reel outline T REEL DIMENSIONS 40 mm min. Access hole At slot location B D C N A Tape slot In core for Full radius DS7317 - Rev 3 Tape start G measured At hub page 10/13 STH180N10F3-2 Packing information Table 8. Tape and reel mechanical data Tape Dim. DS7317 - Rev 3 Reel mm mm Dim. Min. Max. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 330 13.2 26.4 30.4 page 11/13 STH180N10F3-2 Revision history Table 9. Document revision history Date Revision 18-Jul-2011 1 26-Nov-2014 2 02-Mar-2022 DS7317 - Rev 3 3 Changes First version • Modified fig 2. • Updated package mechanical data. • Updated the title, features and description. Updated Figure 1. Safe operating area. Minor text changes. page 12/13 STH180N10F3-2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS7317 - Rev 3 page 13/13