STL100N6LF6
N-channel 60 V, 3.3 mΩ typ., 25 A STripFET™ VI DeepGATE™
Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet − production data
Features
Order code
VDS
RDS(on) max
ID
STL100N6LF6
60 V
4.4 mΩ
25 A
• Low gate charge
1
• Very low on-resistance
2
3
4
• High avalanche ruggedness
PowerFLAT™ 5x6
Applications
• Switching applications
Description
Figure 1. Internal schematic diagram
D(5, 6, 7, 8)
8
7
6
5
1
2
3
4
This device is an N-channel Power MOSFET
developed using the 6th generation of STripFET™
DeepGATE™ technology, with a new gate
structure. The resulting Power MOSFET exhibits
the lowest RDS(on) in all packages.
G(4)
Top View
S(1, 2, 3)
AM15540v2
Table 1. Device summary
Order code
Marking
Package
Packaging
STL100N6LF6
100N6LF6
PowerFLAT™ 5x6
Tape and reel
March 2014
This is information on a product in full production.
DocID018491 Rev 3
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www.st.com
15
Contents
STL100N6LF6
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
.............................................. 8
DocID018491 Rev 3
STL100N6LF6
1
Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
60
V
VGS
Gate-source voltage
± 20
V
ID(1)
Drain current (continuous) at TC = 25 °C
130
A
ID (2)
Drain current (continuous) at Tpcb = 25 °C
25
A
(2)
Drain current (continuous) at Tpcb=100 °C
18
A
Drain current (pulsed)
100
A
Total dissipation at Tpcb = 25 °C
4.8
W
- 55 to 175
°C
Value
Unit
Thermal resistance junction-pcb max
31.3
°C/W
Thermal resistance junction-case max
1.13
°C/W
Max value
Unit
10
A
1370
mJ
ID
IDM(3)
PTOT
(2)
Tstg
Storage temperature
Operating junction temperature
Tj
1. The value is rated according to Rthj-c
2. The value is rated according to Rthj-pcb
3. Pulse width limited by safe operating area
Table 3. Thermal data
Symbol
Rthj-pcb
(1)
Rthj-case
Parameter
1. When mounted on FR-4 board of 1 inch², 2 oz Cu, t < 10 sec
Table 4. Avalanche characteristics
Symbol
Parameter
IAS
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj max)
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAS, VDD = 52 V)
DocID018491 Rev 3
3/15
Electrical characteristics
2
STL100N6LF6
Electrical characteristics
(TJ = 25 °C unless otherwise specified)
Table 5. On/off states
Symbol
V(BR)DSS
IDSS
Parameter
Test conditions
Drain-source breakdown
voltage
Zero gate voltage drain
current (VGS = 0)
ID = 1 mA, VGS= 0
Min.
Typ.
Max.
60
Unit
V
VDS = 60 V
1
μA
VDS = 60 V, TC =125 °C
10
μA
±100
nA
2.5
V
Gate body leakage current
(VDS = 0)
VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 μA
Static drain-source onresistance
VGS= 10 V, ID= 11 A
3.3
4.4
mΩ
RDS(on)
VGS= 4.5 V, ID= 11 A
4.3
5.5
mΩ
Min.
Typ.
Max.
Unit
-
6600
-
pF
-
670
-
pF
-
315
-
pF
IGSS
1
Table 6. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
Rg
Gate input resistance
Test conditions
VDS =25 V, f = 1 MHz,
VGS = 0
VDD = 30 V, ID = 20 A
VGS =10 V
(see Figure 14)
-
121
-
nC
-
17
-
nC
-
22
-
nC
f=1 MHz Gate DC Bias=0
test signal level=20 mV
ID=0
-
1.2
-
Ω
Min.
Typ.
Max.
Unit
-
20
-
ns
-
13
-
ns
-
108
-
ns
-
22
-
ns
Table 7. Switching times
Symbol
td(on)
tr
td(off)
tf
4/15
Parameter
Test conditions
Turn-on delay time
Rise time
Turn-off delay time
VDD= 30 V, ID= 20A,
RG=4.7 Ω, VGS=10 V
(see Figure 13)
Fall time
DocID018491 Rev 3
STL100N6LF6
Electrical characteristics
Table 8. Source drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max
Unit
Source-drain current
-
22
A
ISDM(1)
Source-drain current (pulsed)
-
84
A
VSD(2)
Forward on voltage
ISD = 22 A, VGS = 0
-
1.3
V
trr
Reverse recovery time
-
34
ns
Qrr
Reverse recovery charge
-
44
nC
IRRM
Reverse recovery current
ISD = 20 A,
di/dt = 100 A/μs,
VDD= 48V, TJ = 150 °C
(see Figure 15)
-
2.6
A
ISD
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300μs, duty cycle 1.5%
DocID018491 Rev 3
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Electrical characteristics
2.1
STL100N6LF6
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
AM15543v1
ID
(A)
AM15544v1
K
)
on
-1
S(
pe
ra
ite tion
d
by in t
m his
ax a
RD rea
is
d=0.5
10
0.05
0.02
0.01
10ms
Li
m
O
10
1
100ms
Tj=175°C
Tc=25°C
pcb
-2
10
Single pulse
1s
Single
pulse
-3
0.1
0.1
10
1
VDS(V)
Figure 4. Output characteristics
VGS= 10 V
100
10
tp(s)
AM15546v1
ID
(A)
VDS= 3 V
350
300
10 -1
10 -2
Figure 5. Transfer characteristics
AM15545v1
ID
(A)
10
10 -3
300
VGS= 5 V
250
VGS= 4 V
200
200
150
100
100
VGS= 3 V
50
0
0
1
0
VDS(V)
2
Figure 6. Gate charge vs gate-source voltage
AM15450v1
VGS
(V)
12
0
1
2
4
3
5
6
7
8
VGS(V)
Figure 7. Static drain-source on-resistance
AM15547v1
RDS(on)
(mΩ)
VDD=30V
3.4
ID=20A
10
VGS=10V
3.36
8
3.32
6
3.28
4
3.24
2
0
0
6/15
50
100
150
Qg(nC)
3.2
0
DocID018491 Rev 3
4
8
12
16
20 ID(A)
STL100N6LF6
Electrical characteristics
Figure 8. Capacitance variations
Figure 9. Source-drain diode forward
characteristics
AM15452v1
C
(pF)
AM15456v1
VSD
(V)
TJ=-50°C
Ciss
0.8
0.7
TJ=25°C
0.6
0.5
1000
0.4
Coss
Crss
TJ=150°C
0.3
0.2
0.1
100
0.1
1
10
Figure 10. Normalized gate threshold voltage vs
temperature
AM15454v1
VGS(th)
(norm)
0
VDS(V)
5
10
15
20
ISD(A)
Figure 11. Normalized on-resistance vs
temperature
RDS(on)
(norm)
VDS = VGS
ID = 250 µA
1.2
0
AM15455v1
VGS = 10 V
ID = 11 A
2
1
1.5
0.8
0.6
1
0.4
0.5
0.2
0
-75 -50 -25 0 25 50 75 100 125 150 TJ(°C)
0
-75 -50 -25 0 25 50 75 100 125 150 TJ(°C)
Figure 12. Normalized VDS vs temperature
AM15457v1
VDS
(norm)
1.3
ID = 1mA
1.2
1.1
1
0.9
0.8
0.7
0.6
-75 -50 -25 0 25 50 75 100 125 150 TJ(°C)
DocID018491 Rev 3
7/15
Test circuits
3
STL100N6LF6
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
IG=CONST
VDD
VGS
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
Figure 15. Test circuit for inductive load
switching and diode recovery times
A
A
AM01469v1
Figure 16. Unclamped inductive load test circuit
L
A
D
G
D.U.T.
FAST
DIODE
B
B
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/15
0
DocID018491 Rev 3
10%
AM01473v1
STL100N6LF6
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID018491 Rev 3
9/15
Package mechanical data
STL100N6LF6
Figure 19. PowerFLAT™ 5x6 type S-C mechanical data
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10/15
DocID018491 Rev 3
B+B&
STL100N6LF6
Package mechanical data
Table 9. PowerFLAT™ 5x6 type S-C mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
1.00
A1
0.02
0.05
A2
b
0.25
0.30
0.50
D
5.20
E
6.15
D2
4.11
4.31
E2
3.50
3.70
e
1.27
e1
0.65
L
0.715
1.015
K
1.05
1.35
Figure 20. PowerFLAT™ 5x6 recommended footprint (dimensions in mm)
Footprint
DocID018491 Rev 3
11/15
Packaging mechanical data
5
STL100N6LF6
Packaging mechanical data
Figure 21. PowerFLAT™ 5x6 tape(a)
P0
4.0±0.1 (II)
P2
2.0±0.1 (I)
T
(0.30 ±0.05)
E1
1.75±0.1
Y
0.
20
Do
Ø1.55±0.05
W(12.00±0.3)
F(5.50±0.1)(III)
R
Bo (5.30±0.1)
C
L
EF
D1
Ø1.5 MIN.
REF
.R0
.50
Y
P1(8.00±0.1)
Ao(6.30±0.1)
Ko (1.20±0.1)
SECTION Y-Y
(I) Measured from centerline of sprocket hole
to centerline of pocket.
Base and bulk quantity 3000 pcs
(II) Cumulative tolerance of 10 sprocket
holes is ± 0.20 .
(III) Measured from centerline of sprocket
hole to centerline of pocket.
8234350_Tape_rev_C
Figure 22. PowerFLAT™ 5x6 package orientation in carrier tape.
Pin 1
identification
a. All dimensions are in millimeters.
12/15
DocID018491 Rev 3
STL100N6LF6
Packaging mechanical data
Figure 23. PowerFLAT™ 5x6 reel
R0.60
W3
11.9/15.4
PART NO.
1.90
2.50
R25.00
ØN
178(±2.0)
ATTENTION
OBSERVE PRECAUTIONS
FOR HANDLING ELECTROSTATIC
SENSITIVE DEVICES
W2
18.4 (max)
A
330 (+0/-4.0)
4.00
2.50
77
ESD LOGO
W1
12.4 (+2/-0)
06
PS
ØA
128
2.20
R1.10
Ø21.2
All dimensions are in millimeters
13.00
CORE DETAIL
8234350_Reel_rev_C
DocID018491 Rev 3
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Revision history
6
STL100N6LF6
Revision history
Table 10.
Document revision history
Date
Revision
24-Feb-2011
1
First release
10-Nov-2011
2
Section 4: Package mechanical data has been updated.
Minor text changes.
3
– Updated: title on the cover page.
– Modified: RDS(on) and ID values on cover page
– Modified: drain current (continuous) at TC = 25 °C, drain
current (continuous) at Tpcb = 25 °C, drain current
(continuous) at Tpcb=100 °C, IDM, total dissipation at Tpcb =
25 °C, Tstg and Tj values on table 2, Rthj-case value on
Table 3, max values on Table 4, RDS(on) typ and max. values,
typical values on Table 6, 7 and 8
– Inserted: Section 2.1: Electrical characteristics (curves)
– Updated: Section 4: Package mechanical data
– Added: Section 5: Packaging mechanical data
– Minor text changes
10-Mar-2014
14/15
Changes
DocID018491 Rev 3
STL100N6LF6
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