STL15DN4F5

STL15DN4F5 Dual N-channel 40 V, 8 mΩ, 15 A PowerFLAT™(5x6) double island, STripFET™ V Power MOSFET Features Type STL15DN4F5 VDSS 40 V RDS(on) max. 9 mΩ ID 15 A (1) 1. The value is rated according Rthj-pcb ■ ■ ■ ■ RDS(on) * Qg industry benchmark Extremely low on-resistance RDS(on) Very low switching gate charge Low gate drive power losses PowerFLAT™ (5x6) Double island Application ■ Switching applications – Automotive Figure 1. Internal schematic diagram Description The device is a dual N-channel STripFET™ V. This Power MOSFET technology is among the latest improvements, which have been especially tailored to achieve very low on-state resistance providing also one of the best-in-class figure of merit (FOM). Table 1. Device summary Marking 15DN4F5 Package PowerFLAT™(5x6) Double island Packaging Tape and reel Order code STL15DN4F5 September 2010 Doc ID 17739 Rev 1 1/12 www.st.com 12 Contents STL15DN4F5 Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 Test circuits .............................................. 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 Doc ID 17739 Rev 1 STL15DN4F5 Electrical ratings 1 Electrical ratings Table 2. Symbol VDS VGS ID(1) ID(2) ID (2) IDM (3) (1) (2) Absolute maximum ratings Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 °C Value 40 ± 20 60 15 10 60 60 4.3 0.03 -55 to 175 Unit V V A A A A W W W/°C °C (silicon limited) Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100°C Drain current (pulsed) Total dissipation at TC = 25°C Total dissipation at TC = 25°C, t < 10 sec Derating factor PTOT PTOT TJ Tstg Operating junction temperature Storage temperature 1. The value is rated according Rthj-c 2. The value is rated according Rthj-pcb 3. Pulse width limited by safe operating area Table 3. Symbol Rthj-case Rthj-pcb (1) Thermal resistance Parameter Thermal resistance junction-case (drain) (steady state) Thermal resistance junction-ambient Value 2.5 35 Unit °C/W °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec (see Figure 3) Table 4. Symbol IAV EAS(1) Avalanche data Parameter Not-repetitive avalanche current, (pulse width limited by Tj max.) Single pulse avalanche energy (starting TJ = 25 °C, ID = IAV , VDD = 24 V) Value 7.5 150 Unit A mJ 1. Tested at wafer level only. Doc ID 17739 Rev 1 3/12 Electrical characteristics STL15DN4F5 2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On/off states Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 µA, VGS= 0 VDS = Max rating, VDS = Max rating @125 °C VGS = ±20 V VDS= VGS, ID = 250 µA VGS= 10 V, ID= 7.5 A 2 8 Min. 40 1 10 ±100 Typ. Max. Unit V µA µA nA V mΩ 4 9 Table 6. Symbol Ciss Coss Crss Qg Qgs Qgd Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 25 V, f = 1 MHz VGS = 0 VDD= 20 V, ID = 15 A VGS = 10 V (see Figure 14) Min. Typ. 1550 230 25 25 6 5.5 Max. Unit pF pF pF nC nC nC - - - 4/12 Doc ID 17739 Rev 1 STL15DN4F5 Electrical characteristics Table 7. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 20 V, ID = 7.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13) Min. Typ. 18 45 32 5 Max. Unit ns ns ns ns - Table 8. Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 15 A, VGS = 0 ISD = 15 A, di/dt = 100 A/µs, VDD = 32 V, Tj = 150 °C Test conditions Min 30 35 2.2 Typ. Max 15 60 1.1 Unit A A V ns nC A - 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 % Doc ID 17739 Rev 1 5/12 Electrical characteristics STL15DN4F5 2.1 Figure 2. ID (A) 100 Electrical characteristics (curves) Safe operating area AM07129v1 Tj=175°C Tc=25°C Single pulse is rea s a S(on) thi in x RD ion ma t era by Op ited Lim Figure 3. Thermal impedance 10 10ms 100ms 1s 1 0.1 0.01 0.1 1 10 VDS(V) Figure 4. ID (A) Output characteristics AM07130v1 Figure 5. ID (A) 35 30 25 20 15 10 5 4V Transfer characteristics AM07131v1 VGS=10V 35 6V 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 VDS(V) 5V VDS=0.4V 0 0 2 4 6 8 VGS(V) Figure 6. BVDSS 1.15 (norm) Normalized BVDSS vs temperature AM07132v1 Figure 7. RDS(on) (mOhm) Static drain-source on resistance AM07133v1 VGS=10V 8.6 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -75 -50 -25 0 25 50 75 100 125 150 TJ(°C) 7.0 0 2 4 6 8 10 12 14 ID(A) 7.8 8.2 7.4 6/12 Doc ID 17739 Rev 1 STL15DN4F5 Figure 8. VGS (V) 10 Electrical characteristics Capacitance variations AM07134v1 Gate charge vs gate-source voltage Figure 9. AM07135v1 VDD=20V ID=15A C (pF) Ciss 8 6 Coss 4 2 0 0 5 10 10 15 20 25 Qg(nC) 0.1 1 10 VDS(V) 100 1000 Crss Figure 10. Normalized gate threshold voltage vs temperature VGS(th) (norm) AM07136v1 Figure 11. Normalized on resistance vs temperature RDS(on) (norm) 2.0 AM07137v1 1.00 1.5 0.8 1.0 0.6 0.5 0 -75 -50 -25 0.4 -75 -50 -25 0 25 50 75 100 125 150 TJ(°C) 0 25 50 75 100 125 150 TJ(°C) Figure 12. Source-drain diode forward characteristics VSD (V) 0.9 0.8 0.7 0.6 TJ=175°C 0.5 0.4 0 2 4 6 8 10 12 14 ISD(A) TJ=25°C AM07138v1 TJ=-55°C Doc ID 17739 Rev 1 7/12 Test circuits STL15DN4F5 3 Test circuits Figure 14. Gate charge test circuit VDD 12V 2200 Figure 13. Switching times test circuit for resistive load 47kΩ 100nF 1kΩ RL VGS VD RG PW D.U.T. µF 3.3 µF VDD Vi=20V=VGMAX 2200 µF IG=CONST 2.7kΩ 47kΩ PW 1kΩ 100Ω D.U.T. VG AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A D G S B 25 Ω D.U.T. A FAST DIODE B A L=100µH B D G 3.3 µF 1000 µF L VD 2200 µF 3.3 µF VDD VDD ID RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform V(BR)DSS VD Figure 18. Switching time waveform ton tdon tr toff tdoff tf 90% IDM 90% 10% ID VDD VDD 0 10% VDS 90% VGS AM01472v1 0 10% AM01473v1 8/12 Doc ID 17739 Rev 1 STL15DN4F5 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and products status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 17739 Rev 1 9/12 Package mechanical data STL15DN4F5 PowerFLAT™ (5x6) double island mechanical data mm Dim Min A A1 A3 b D D1 D2 E E1 E2 E3 e L L1 0.70 0.48 3.51 2.32 4.11 0.35 0.80 Typ 0.83 0.02 0.20 0.40 5.00 4.75 4.21 6.00 5.75 3.61 2.42 1.27 0.80 0.58 0.90 0.68 3.71 2.52 4.31 0.47 Max 0.90 0.05 8066312_A 10/12 Doc ID 17739 Rev 1 STL15DN4F5 Revision history 5 Revision history Table 9. Date 02-Sep-2010 Document revision history Revision 1 First release Changes Doc ID 17739 Rev 1 11/12 STL15DN4F5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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