STL8P4LLF6

STL8P4LLF6 P-channel 40 V, 0.0175 Ω typ.,8 A, STripFET™ F6 Power MOSFET in a PowerFLAT™ 3.3 x 3.3 package Datasheet - production data Features 1 2 3 Order code VDS RDS(on) max. ID PTOT STL8P4LLF6 40 V 0.0205 Ω 8A 2.9 W • • • • 4 PowerFLAT™ 3.3x3.3 Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications • Switching applications Figure 1: Internal schematic diagram Description This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. Table 1: Device summary Order code Marking Package Packaging STL8P4LLF6 8P4F6 PowerFLAT™ 3.3 x 3.3 Tape and reel March 2015 DocID025617 Rev 2 This is information on a product in full production. 1/14 www.st.com Contents STL8P4LLF6 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/14 PowerFLAT™ 3.3x3.3 package information .................................... 10 Revision history ............................................................................ 13 DocID025617 Rev 2 STL8P4LLF6 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ± 20 V (1) ID Drain current (continuous) at Tpcb = 25 °C 8 A (1) ID Drain current (continuous) at Tpcb = 100 °C 5 A Drain current (pulsed) 32 A PTOT Total dissipation at Tpcb = 25 °C 2.9 W Tstg Storage temperature -55 to 150 °C 150 °C Value Unit Thermal resistance junction-case max 2.50 °C/W Thermal resistance junction-pcb max. 42.8 °C/W (1)(2) IDM Tj Maximum junction temperature Notes: (1) (2) this value is related to Rthj-pcb Pulse width limited by safe operating area. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Notes: (1) When mounted on FR-4 board of 1 inch², 2oz Cu, t ≤ 10 s For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. DocID025617 Rev 2 3/14 Electrical characteristics 2 STL8P4LLF6 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: Static Symbol Parameter V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS Gate-body leakage current VGS(th) RDS(on) Test conditions VGS = 0 V, ID = 250 µA Min. Typ. Max. 40 Unit V VGS = 0 V, VDS = 40 V 1 µA VGS = 0 V, VDS = 40 V, TC = 125 °C 10 µA VDS = 0 V, VGS = ± 20 V ±100 nA 2.5 V Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source onresistance VGS = 10 V, ID = 4 A 1 0.0175 0.0205 VGS = 4.5 V, ID= 4 A 0.021 0.029 Min. Typ. Max. Unit - 2850 - pF - 270 - pF - 180 - pF - 22 - nC - 9.4 - nC - 7.3 - nC - 1.4 - Ω Test conditions Min. Typ. Max. Unit VDD = 20 V, ID = 4 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Switching times test circuit for resistive load") - 43 - ns - 47 - ns - 148 - ns - 19 - ns Ω Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge RG Gate input resistance Test conditions VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 20 V, ID = 8 A, VGS = 4.5 V (see Figure 14: "Gate charge test circuit") ID = 0 A, gate DC bias = 0 V, f = 1 MHz, magnitude of alternative signal = 20 mV Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off-delay time Fall time For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. 4/14 DocID025617 Rev 2 STL8P4LLF6 Electrical characteristics Table 7: Source drain diode Symbol VSD (1) Parameter Test conditions Min. Typ. Max. Unit 1.1 V Forward on voltage VGS = 0 V, ISD = 8 A - trr Reverse recovery time - 26 ns Qrr Reverse recovery charge - 21 nC IRRM Reverse recovery current ISD = 8 A, di/dt = 100 A/µs, VDD = 32 V, Tj = 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 1.7 A Notes: (1) Pulse test: pulse duration = 300 µs, duty cycle 1.5% For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. DocID025617 Rev 2 5/14 Electrical characteristics 2.1 6/14 STL8P4LLF6 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Normalized gate threshold voltage vs temperature Figure 7: Normalized V(BR)DSS vs temperature DocID025617 Rev 2 STL8P4LLF6 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized on-resistance vs. temperature Figure 10: Gate charge vs gate-source voltage Figure 11: Capacitance variations voltage Figure 12: Source-drain diode forward characteristics DocID025617 Rev 2 7/14 Test circuits 3 STL8P4LLF6 Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit Figure 15: Test circuit for inductive load switching and diode recovery times 8/14 DocID025617 Rev 2 STL8P4LLF6 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID025617 Rev 2 9/14 Package information 4.1 STL8P4LLF6 PowerFLAT™ 3.3x3.3 package information Figure 16: PowerFLAT™ 3.3x3.3 package outline BOTTOM VIEW SIDE VIEW TOP VIEW 8465286_A 10/14 DocID025617 Rev 2 STL8P4LLF6 Package information Table 8: PowerFLAT™ 3.3x3.3 mechanical data mm Dim. Min. Typ. Max. A 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 D 3.10 3.30 3.50 D1 3.05 3.15 3.25 D2 2.15 2.25 2.35 e 0.55 0.65 0.75 E 3.10 3.30 3.50 E1 2.90 3.00 3.10 E2 1.60 1.70 1.80 H 0.25 0.40 0.55 K 0.65 0.75 0.85 L 030 0.45 0.60 L1 0.05 0.15 0.25 L2 ϑ 0.5 8° DocID025617 Rev 2 10° 12° 11/14 Package information STL8P4LLF6 Figure 17: PowerFLAT™ 3.3x3.3 recommended footprint 8465286_footprint 12/14 DocID025617 Rev 2 STL8P4LLF6 5 Revision history Revision history Table 9: Document revision history Date Revision 28-Jan-2014 1 Initial release. 2 Text edits throughout document On cover page, updated title, description and features table Updated Table 4: Static Updated Table 5: Dynamic Updated Table 6: Switching times Updated Table 7: Source-drain diode Added Section 2.1: Electrical characteristics (curves) Renamed and updated Section 4.1 PowerFLAT™ 3.3 x 3.3 package information 24-Mar-2015 Changes DocID025617 Rev 2 13/14 STL8P4LLF6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 14/14 DocID025617 Rev 2