AW9109
Feb. 2019 V1.4
9 Programmable LED Driver
GENERAL DESCRIPTION
AW9109 integrates a SRAM program-controlled 9
LED driver. 9 LED driver uses common anode
current source and PWM dimming. Each LED is
8-level driver current selectable with dimming
independently controlled by external MCU or
internal 256word*16bit SRAM program.
ti
a
n
Compatible I2C interface of 400kHz fast mode is
provided. It requires only 3.0V-4.5V single power
supply.
e
8-level LED Maximum Current for each LED,
max 24.5mA
Internal ASP with 256*16bit SRAM
Programmable to Achieve Custom Light Effect
256-level Linear/Logarithmic PWM Dimming,9
bits PWM resolution
Compatible I2C Interface, VIO: 1.8V ~ 3.3V
Single Power Supply, Voltage Range: 3.0V ~
4.5V
QFN 3mm×3mm×0.75mm- 20L Package
fi
d
l
FEATURES
APPLICATIONS
Mobile Phones, MID
n
Portable Media Player
o
Home Appliances
C
TYPICAL APPLICATION CIRCUIT
VBAT
ic
MCU/BB
VBAT
LED1
1mF
4.7kΩ
x3
AD
LED3
GND
LED4
GND
LED5
GND
AW9109
LED6
SCL
SCL
SDA
SDA
INTN
INTN
LED8
GPO
PDN
LED9
a
w
in
VIO
LED2
LED7
Figure 1
AW9109 Typical Application Circuit
All trademarks are the property of their respective owners.
www.awinic.com.cn
1
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
CONTENT
PIN CONFIGURATION AND TOP MARK.................................................................................................... 4
2
PIN DEFINITION ........................................................................................................................................... 4
3
FUNCTIONAL BLOCK DIAGRAM ............................................................................................................... 5
4
TYPICAL APPLICATION CIRCUITS ........................................................................................................... 5
5
ORDERING INFORMATION ........................................................................................................................ 6
6
ABSOLUTE MAXIMUM RATINGS(NOTE 3) .................................................................................................... 6
7
ELECTRICAL CHARACTERISTICS ............................................................................................................ 7
8
I2C INTERFACE TIMING .............................................................................................................................. 8
9
FUNCTIONAL DESCRIPTION ..................................................................................................................... 9
e
n
ti
a
l
1
fi
d
9.1 WORK MODE ....................................................................................................................................................... 9
9.1.1 POWER ON ............................................................................................................................................. 9
9.1.2 WORK MODE .......................................................................................................................................... 9
HARDWARE RESET ........................................................................................................................... 10
9.2.2
SOFTWARE RESET ........................................................................................................................... 10
I 2C
n
9.2.1
INTERFACE .................................................................................................................................................. 10
o
9.3
RESET ................................................................................................................................................................ 10
9.3.1
DEVICE ADDRESS ............................................................................................................................. 10
9.3.2
DATA VALIDATION ............................................................................................................................. 10
9.3.3
ACK(ACKNOWLEDGEMENT)............................................................................................................. 10
9.3.4
I2C START/STOP ................................................................................................................................ 11
C
9.2
9.3.5 WRITE CYCLE .................................................................................................................................... 11
READ CYCLE ...................................................................................................................................... 12
ic
9.3.6
9.4
OSCILLATOR ..................................................................................................................................................... 13
9.5
LED DRIVER ...................................................................................................................................................... 13
LED BRIGHTNESS CONTROLLER .................................................................................................... 13
9.5.2
LED CONSTANT CURRENT DRIVER ................................................................................................ 13
9.5.3
ASP ..................................................................................................................................................... 14
in
9.5.1
REGISTER DESCRIPTION ......................................................................................................................22
w
10
REGISTER CONFIGURATION ......................................................................................................................... 22
10.2
GLOBAL REGISTER DESCRIPTION ............................................................................................................... 23
a
10.1
10.3
10.2.1 IDRST, CHIP ID AND SOFTWARE RESET ...................................................................................... 23
10.2.2
GCR, GLOBAL CONTROL REGISTER ............................................................................................. 23
LED EFFECT CONTROL REGISTER .............................................................................................................. 23
10.3.1 LER1, LED DRIVER ENABLE REGISTER ........................................................................................ 23
10.3.2 LCR, LED EFFECT CONFIGURATION REGISTER ......................................................................... 23
10.3.3
PMD, PROGRAM MODE REGISTER ............................................................................................... 23
10.3.4
RMD, PROGRAM RUN MODE REGISTER ...................................................................................... 24
www.awinic.com.cn
2
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
10.3.5
CTRSR, LED CONTROL SOURCE SELECTION REGISTER .......................................................... 24
10.3.6 IMAX1～IMAX6, LEDX MAXIMUM OUTPUT CURRENT REGISTER ............................................... 24
10.3.7 LISR, LED INTERRUPT STATUS REGISTER .................................................................................. 24
SADDR, PROGRAM START ADDRESS REGISTER ....................................................................... 25
10.3.9
PCR, LED PROGRAM CONTROL POINTER REGISTER ................................................................ 25
10.3.10
CMDR, LED COMMAND REGISTER .............................................................................................. 25
10.3.11
RA/RB/RC/RD,LED INTERNAL PROGRAM REGISTER ................................................................ 25
10.3.12
R1~R8, LED INTERNAL DATA REGISTER .................................................................................... 25
10.3.13
GRP, LED GROUP OPERATION REGISTER................................................................................. 25
ti
a
l
10.3.8
10.3.14 WADDR, LED PROGRAM LOADING ADDRESS REGISTER ........................................................ 26
10.3.15 WDATA, LED PROGRAM LOADING DATA REGISTER ................................................................ 26
11
n
10.3.16 WPR, WRITING PROTECTION REGISTER ................................................................................... 26
TAPE AND REEL INFORMATION ...........................................................................................................27
CARRIER TAPE................................................................................................................................................ 27
11.2
PIN1 DIRECTION ............................................................................................................................................. 27
11.3
REEL................................................................................................................................................................. 28
fi
d
e
11.1
PACKAGE DESCRIPTION ......................................................................................................................29
13
RECOMMENDED LAND PATTERN ........................................................................................................29
14
REFLOW ...................................................................................................................................................30
15
REVISION HISTORY ................................................................................................................................31
16
DISCLAIMER ............................................................................................................................................32
a
w
in
ic
C
o
n
12
www.awinic.com.cn
3
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
PIN CONFIGURATION AND TOP MARK
GND
LED7
LED8
LED9
NC
15
14
13
12
11
17
9
GND
LED4
18
8
VBAT
LED3
19
7
PDN
GND
20
6
AD
5
e
INTN
SCL
SDA
LED1
LED2
fi
d
NAME
1
LED2
LED2 cathode driver, anode connected to VBAT
2
LED1
LED1 cathode driver, anode connected to VBAT
3
SDA
Data I/O of I2C Interface
4
SCL
Clock input of I2C Interface
5
INTN
Open-drain Interrupt output, low active. Typically connected to VIO via
a 4.7kΩ resistor. (floating if not unused)
6
AD
7
PDN
9
o
C
I2C address select pin
Power-down input , low active, internal 1MΩ pull-down resistor
VBAT
Power supply (3.0V to 4.5V)
GND
Ground
NC
in
10
DESCRIPTION
n
No.
8
NC
11
NC
12
LED9
LED9 cathode driver, anode connected to VBAT
13
LED8
LED8 cathode driver, anode connected to VBAT
14
LED7
LED7 cathode driver, anode connected to VBAT
15
GND
Ground
16
LED6
LED6 cathode driver, anode connected to VBAT
17
LED5
LED5 cathode driver, anode connected to VBAT
18
LED4
LED4 cathode driver, anode connected to VBAT
19
LED3
LED3 cathode driver, anode connected to VBAT
20
GND
Ground
w
a
AW9109-AW9109QNR
XXXX-Production Tracing Code
PIN DEFINITION
ic
2
AW9109
XXXX
n
LED5
4
NC
3
10
2
16
1
LED6
l
AW9109 Marking
AW9109 Top View
ti
a
1
www.awinic.com.cn
NC
4
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
3
FUNCTIONAL BLOCK DIAGRAM
LED1
LED2
ASP
VBAT
LDO
OSC
ti
a
LED4
LED
DRIVER
l
LED3
LED5
LED6
GND
n
LED7
LED8
GND
Figure 2
4
SDA
PDN
INTN
LED9
fi
d
SCL
e
I2 C
AD
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATION CIRCUITS
n
VBAT
o
MCU/BB
VBAT
LED1
C
1mF
LED2
GND
LED5
AD
VIO
LED3
GND
ic
4.7kΩ
x3
LED4
GND
AW9109
LED6
SCL
SDA
SDA
INTN
INTN
LED8
GPO
PDN
LED9
LED7
Figure 3 AW9109 Typical Application Circuit
a
w
in
SCL
www.awinic.com.cn
5
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
ORDERING INFORMATION
AW9109QNR
Temperature
-40℃～85℃
Package
Marking
3mm×3mm×0.75mm
QFN-20L
AW9109
Moisture
Sensitivity
Level
MSL3
Environmental
Information
Delivery
Form
ROHS+HF
6000
unit /
Tape
and Reel
fi
d
ABSOLUTE MAXIMUM RATINGS(NOTE 3)
6
PARAMETERS
Supply voltage range VBAT
SCL, SDA
n
Input voltage range
RANGE
-0.3V to 5V
-0.3V to 3.6V
PDN, LED1~LED9
-0.3V to 4.5V
SDA, INTN
-0.3V to 3.6V
o
Output voltage range
e
Package Type
QN: QFN
n
AW9109
Shipping
R: Tape & Reel
C
Junction-to-ambient thermal resistance θJA
45℃/W
-40℃ to 85℃
Operating free-air temperature range
150℃
Maximum Junction temperature TJMAX
ic
l
Part Number
ti
a
5
-65℃ to 150℃
Storage temperature TSTG
Lead Temperature (Soldering 10 Seconds)
260℃
in
ESD(NOTE 4)
HBM (human body model)
±4kV
w
Latch-up
+IT：450mA
-IT：-450mA
a
Test Condition: JEDEC STANDARD NO.78B DECEMBER 2008
NOTE3: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the
ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for
prolonged periods may affect device reliability.
NOTE4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: MIL-STD-883G Method 3015.7
www.awinic.com.cn
6
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
7
ELECTRICAL CHARACTERISTICS
VBAT=3.8V, TA=25℃ for typical values (unless otherwise noted)
Power supply
-
3.0
Current in Shutdown mode
PDN=GND
8
ISTANDBY
Current in Standby mode
PDN=VIO
130
IACTIVE
Current in Active mode
PDN=VIO, GCR=0x01
0.55
VBAT
ISHUTDOWN
Internal oscillator
FOSC
14.8
Frequency accuracy (16MHz)
Digital Logical Interface
SDA,SCL,PDN
VIH
Logic input high level
SDA,SCL,PDN
IIL
Low level input current
SDA,SCL,PDN
IIH
High level input current
SDA,SCL,PDN
Logic output low level
IOL
Maximum output current
IL
Output leakage current
mA
0.8
mA
17.2
MHz
V
V
5
nA
0.4
V
SDA, INTN
10
mA
SDA,INTN open drain
1
mA
400
kHz
n
C
ns
SDA deglitch time
250
ns
LED MAX Current
ILED=24.5mA
Matching accuracy
Drop-out voltage
18.5
24.5
30.5
mA
ILED=24.5mA
10
%
ILED=24.5mA
300
mV
LCR.FREQ=1
110
122
135
Hz
LCR.FREQ =0
220
244
270
Hz
PWM frequency
w
FPWM
160
200
in
IMATCH
mA
nA
IOUT=3mA
ic
IMAX
15
SCL deglitch time
TDeglitch
LED Driver
V
5
I2C-BUS clock frequency
FSCL
4.5
0.9
o
I2C Interface
UNIT
0.45
SDA, INTN
VOL
VDROP
-0.3
16
MAX
e
Logic input low level
fi
d
VIL
TYP
l
MIN
ti
a
TEST CONDITION
n
PARAMETER
a
NOTE5：the value is tested in default configuration.
www.awinic.com.cn
7
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Parameter Name
TDEGLITCH
Deglitch time
SDA
250
ns
Low level width of SCL
1.3
THIGH
High level width of SCL
0.6
TSU:STA
(Repeat-start) Start condition setup time
0.6
THD:DAT
Data hold time
0
TSU:DAT
Data setup time
0.1
TR
Rising time of SDA and SCL
TF
Falling time of SDA and SCL
TSU:STO
Stop condition setup time
TBUF
Time between start and stop condition
o
n
tHD:STA
Start
μs
tHD:DAT
μs
μs
μs
0.3
μs
0.3
μs
0.6
μs
1.3
μs
VIH
VIL
tSP
tF
VIH
VIL
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
a
w
in
ic
Stop
μs
C
SCL
tHIGH
μs
fi
d
TLOW
tR
kHz
ns
0.6
tLOW
400
200
(Repeat-start) Start condition hold time
tBUF
UNIT
SCL
THD:STA
SDA
MAX
ti
a
Interface Clock frequency
TYP
n
FSCL
MIN
l
I2C INTERFACE TIMING
e
8
www.awinic.com.cn
8
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
9
FUNCTIONAL DESCRIPTION
9.1
WORK MODE
9.1.1 Power On
ti
a
l
After power-up, about 100μs delay is required before PDN set to high, otherwise, the device may work
incorrectly. The minimal wait time for I2C communication is 5ms, during this period, some internal modules
(such as LDO) start to work and reach a stable state.
VBAT
100μs
Note: About 100μs delay is required after power on
n
PDN
5ms
Note: The minimal wait time for I2C communication is 5ms
Figure 4
fi
d
e
I2C
AW9109 Power On
9.1.2 Work Mode
o
n
VBAT Power On
Shutdown
C
PDN=0
PDN=1
Registers
Initialization
Software
Reset
ic
in
LDO enable,
powering internal digital module
Delay 5ms
PDN=0
I2C available,
LED control & output shutdown,
Standby
LEDE=1
LEDE=0
PDN=0
w
Internal LDO shutdown,
minimum power dissipation
Active
Figure 5
I2C available,
LED control & output enable
AW9109 Work Mode
a
After VBAT powered on, if PDN pin is low, the AW9109 is in shut-down mode, the current consumption is less
than 15mA. When PDN pin becomes high, the internal LDO is activated, and a power-on reset (POR) signal is
generated to initialize all internal registers, the device enters standby mode, this is a low power consumption
mode, when all circuit functions are disabled. In standby mode, I2C interface is active, all internal configuration
register can be written. If control bit GCR.LEDE is written high, the device enters the active mode.
www.awinic.com.cn
9
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
9.2
9.2.1
RESET
Hardware Reset
When PDN pin changes from low to high, the power-up reset (POR) signal is generated, all internal registers
are reset.
Software Reset
9.3
to reset all internal registers.
ti
a
Writing 0x55AA to register RSTR via I2C interface will activate a software reset
l
9.2.2
I2C INTERFACE
Device Address
e
9.3.1
n
AW9109 supports the I²C serial bus and data transmission protocol in fast mode at 400kHz. It operates as a
slave on the I²C bus. Connections to the bus are made via the open-drain I/O pins SCL and SDA. The pull-up
resistor can be selected in the range of 1k~10kΩ and the typical value is 4.7kΩ. AW9109 can support different
high level (1.8V~3.3V) of this I2C interface.
0
1
0
1
0
AD
R/W
Device Address Configuration
Data Validation
o
9.3.2
1
n
Figure 6
fi
d
The I2C device address (7-bit, followed by the R/W bit(Read=1/Write=0)) of AW9109 is 0x2C/0x2D.
C
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.
SDA
9.3.3
in
ic
SCL
Data Line
Stable
Data Valid
Figure 7
Change
of Data
Allowed
Data Validation Diagram
ACK(Acknowledgement)
w
ACK means the successful transfer of I2C bus data. After master sends 8bits data, SDA must be released;
SDA is pulled to GND by slave device when slave acknowledges.
a
When master reads, AW9109 sends 8bit data, releases the SDA and waits for ACK from master. If ACK is
send and I2C stop is not send by master, AW9109 sends the next data. If ACK is not send by master, AW9109
stops to send data and waits for I2C stop.
www.awinic.com.cn
10
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Data Output
by Transmiter
Not Acknowledge（NACK）
Data Output
by Receiver
Acknowledge（ACK）
8
9
Figure 8
9.3.4
ti
a
Clock Pulse for
Acknowledgement
START
condition
l
2
1
SCL From
Master
I2C ACK Timing
I2C Start/Stop
n
I2C start: SDA changes form high level to low level when SCL is high level.
SDA
SCL
S/Sr
fi
d
e
I2C stop: SDA changes form low level to high level when SCL is high level.
P
9.3.5
Write Cycle
I2C Start/Stop Condition Timing
C
Figure 9
P: STOP condition
o
n
S: START condition
Sr: START Repeated condition
ic
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction.
New data should be sent during the low SCL state. This protocol permits a single data line to transfer both
command/control information and data using the synchronous serial clock.
in
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and
a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow.
a
w
In a write process, the following steps should be followed:
a)
Master device generates START condition. The “START” signal is generated by lowering the SDA
signal while the SCL signal is high.
b)
Master device sends slave address (7-bit) and the data direction bit (W = 0).
c)
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master sends data high 8Bit to be written to the addressed register
g)
Slave sends acknowledge signal
www.awinic.com.cn
11
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Master sends data low 8Bit to be written to the addressed register
I)
Slave sends acknowledge signal
j)
Master generates STOP condition to indicate write cycle end
0
SDA
A6
Start
1
A5
2
A4
3
A3
4
A2
5
6
7
8
0
1
A0 R/W Ack A7
A1
2
A6
I2C Address
A5
A4
4
A3
5
6
A2
A1
7
A0
8
0
1
2
3
4
5
6
Ack D15 D14 D13 D12 D11 D10 D9
Register Address
7
8
0
1
...
6
D6 …… D1
D8 Ack D7
7
D0
Register Low 8BIt
Register High 8Bit
AW9109 I2C Write Timing
Figure 10
9.3.6
3
8
Ack
Stop
ti
a
SCL
l
h)
Read Cycle
n
In a read cycle, the following steps should be followed:
Master device generates START condition
b)
Master device sends slave address (7-bit) and the data direction bit (W = 0).
c)
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master generates STOP condition followed with START condition or REPEAT START condition
g)
Master device sends slave address (7-bit) and the data direction bit (R = 1).
h)
Slave device sends acknowledge signal if the slave address is correct.
i)
Slave sends data high 8Bit from addressed register.
j)
Master sends acknowledge signal
k)
Slave sends data low 8Bit from addressed register.
l)
If the master device sends acknowledge signal, the slave device will increase the control register
address by one, then send the next data from the new addressed register. If master sends no
acknowledge signal, the slave device stop to send data and wait for STOP condition.
ic
C
o
n
fi
d
e
a)
in
m) If the master device generates STOP condition, the read cycle is ended.
SCL
0
SDA
1
A6
A5
w
0
……
a
A6
1
A5
RS
A4
4
A3
……
A2
2
3
A4
A3
4
A1
6
7
A2
8
0
A6
S
1
A5
2
A4
3
A3
A0 R/W Ack A7
1
A6
6
7
8
2
3
A5
A4
4
A3
5
A2
0
1
...
6
7
D8
8
5
A1
2
I C Address
6
7
8
8
7
A1
A0
Ack
1
...
6
Ack
0
D7
0
1
...
D6 …… D1
7
8
D0 Ack
Register Data
Low 8Bit
Register Data
High 8Bit
4
6
Register Address
A0 R/W Ack D15 D14 …… D9
A1
A2
0
……
5
6
A0 R/W Ack D15 D14 …… D9
7
8
0
D8 Ack D7
Register Data
High 8Bit
1
...
Stop
6
D6 …… D1
Register Data
Low 8Bit
7
D0
8
Ack
Stop
AW9109 I2C Read Timing
Figure 11
www.awinic.com.cn
5
I2C Address
Separated
Read/write
transaction ……
P
3
I2C Address
Start
Using
Repeat start……
2
12
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
9.4
OSCILLATOR
An internal oscillator provides clock for LED controlling circuit. If register bit GCR.LEDE is high, the OSC
starts to work, the start-up time is about 5 μs. When both the register bit GCR.LEDE are low, the internal OSC
stops.
9.5
LED DRIVER
ti
a
l
LED driver provide 9 current sources to drive LEDs, a dedicated Application-Specific-Processor（ASP）is
designed to produce versatile lighting effect for mobile devices.
ASP
n
If the control bit GCR.LEDE is 0 , LED driver circuit is in reset state, all 9 LED outputs are disabled. If control
bit GCR.LEDE is 1, the LED driver circuit is enabled, the control bit LER.LENx (x=1 to 9) configure the
corresponding LED channel is active or not.
fi
d
PWM2
PWM
Controller
Program
Controller
...
...
LED1
LED2
...
LED9
o
n
PWM9
PWM
Controller
e
PWM1
PWM
Controller
C
I2C Interface
Figure 12
9.5.1
SDA
ic
SCL
AW9109 LED Dimming Control Module Diagram
LED brightness controller
in
Pulse Width Modulation (PWM) is used to adjust the brightness of LED, 256 level brightness with 9bit
resolution is adapted. The PWM frequency can be configured between 125Hz or 250Hz by control bit
LCR.FREQ.
w
The ASP generates the PWM signal with dedicated and highly efficient dimming control instruction for all 9
independent LED constant current source. By programming, user-defined complicated lighting effect could be
produced.
a
The LED control instruction executed by ASP could come from LED SRAM or external I2C register. The
register CTRS can choose every LED channel to be controlled by SRAM program or by I2C register.
-
CTRS[n] = 0, LED n controller is controlled by the internal SRAM instruction;
CTRS[n] = 1, LED n controller is controlled by the external I2C register.
9.5.2
LED Constant current driver
For each LED, the maximum output constant current is 24.5mA, with 8 level adjustable by register IMAXn
(n=1~9).
www.awinic.com.cn
13
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
9.5.3
ASP
ASP module is consist of one program controller and 9 PWM controllers.
SCL
Control
Instruction
PWM1
PWM
Controller
PWM2
PWM
Controller
PWM3
ti
a
PC
PWM
Controller
n
SRAM
256×16bits
PWM
Controller
PWM9
fi
d
Figure 13
9.5.3.1
...
e
...
Program_controller
l
SDA
ASP Structure Diagram
Program Controller
C
o
n
The program controller is clocked by 32kHz internal clock, each instruction is executed in one clock cycle. The
program controller is consist of a program SRAM, an algorithmic logic unit ( ALU) and other internal
registers. The 256x16bit internal SRAM is used to store LED lighting effect program loaded through I2C
interface, the I2C interface also can start or stop the program execution. There are 4 internal registers
RA/RB/RC/RD participating ALU operation so as to generate complicated program control such as repeating
and looping. Except for that, there are 8 8bit temporary data registers(R1~R8) and 5 special function registers.
Their internal address and function description is shown in the table below.
Table 1 Address allocation of
Address(HEX)
R1
00
R1 data temporary register，8bit，I2C readable
01
R2 data temporary register，8bit，I2C readable
02
R3 data temporary register，8bit，I2C readable
R4
03
R4 data temporary register，8bit，I2C readable
R5
04
R5 data temporary register，8bit，I2C readable
R6
05
R6 data temporary register，8bit，I2C readable
R7
06
R7 data temporary register，8bit，I2C readable
R8
07
R8 data temporary register，8bit，I2C reading
GMSK1
GMSK2
0d
0e
Global control mask register(M6~M1)
Global control mask register(M9~M7)
w
in
R3
ic
Register
R2
a
internal data register in ASP
Description
Table 2 Special function registers definition
Register B7
B6
B5
B4
B3
B2
B1
B0
Description
GMSK1
M5
M4
M3
M2
M1
-
-
M9
M8
M7
Mask control for global control
instruction. When Mn=1, LEDn
will not be affected by global
M6
GMSK2
www.awinic.com.cn
14
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
control instruction.
9.5.3.2
PWM Controller
ti
a
l
The PWM controller is execution unit of LED control instruction. There are 9 PWM controllers receiving the
LED effect instruction from SRAM, and generate 8bit PWM code, which will be convert to 9bit duty cycle
control code by logarithmic l transformation. If LCR.LOGLN=00, the transformation is natural logarithm( loge ).
If LCR.LOGLN=01, the transformation is logarithm of 10 (log10 ), otherwise the 8b-to-9b transformation of
PWM code is linear.
SCL
8
log/lin
PWM
Generator
fi
d
Register
9
LEDx
e
Cmd
Execute
From
SRAM
n
SDA
3
PWM Controller Schematic Diagram
o
Figure 14
n
1MHz
C
100
95
90
85
ic
80
75
LO
LO
IN
G
G
=1
/L
/L
0
IN
IN
=0
=0
0
1
65
a
w
in
Brightness（%）
70
LO
G
/L
60
55
50
45
40
35
30
25
20
15
10
5
0
16
32 48
64 80 96 112 128 144 160 176 192 208 224 240 256
Control Signal Value（Decimal）
www.awinic.com.cn
15
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Figure 15
9.5.3.3
a)
8bit-to-9bit PWM code transformation curve
Program Loading and execution
Program loading
b)
ti
a
l
It is recommended to load SRAM program only when control bit PMD.PROGMD is 00. In this state, the
internal program can be read/write through I2C interface. When loading program, please write the SRAM
loading address in register WADDR(0x7E) at first, and then write the 16bit LED effect instruction to register
WDATA(0x7F). Continuously loading program is supported, after a 16b instruction is written through register
WDATA, the value of WADDR will automatically plus by 1.
Program execution
Register bit PMD.PROGMD[1:0] controls the loading and execution mode of SRAM program.
n
When register bit IPMD.PROGMD[1:0]=00, program execution is shut down, SRAM program and program
pointer(PC) are permitted to be loaded.
e
When IPMD.PROGMD[1:0] is written to be 01 from another value, current program will stop , and PC will be
reload by register SADDR, and then executes the SRAM program starting from the address of PC
fi
d
When Register bit PMD.PROGMD[1:0] =10, the SRAM program will be executed by the mode defined by
register bit RMD.RUNMD[1:0]
Table 3 Program running mode control register
RMD.RUNMD
Hold mode. program stop and PC
01
Single step mode, only used for debugging. Once writing 01 to RUNMD,
only one instruction will be executed with PC+1, and then RMD.RUMND
is cleared (return to hold mode)
10
Continuously running mode, program starts from the address of
11
Repeating mode, only used for debugging. Once writing 11 to RUNMD,
current instruction will be executed without PC+1, and then RMD.RUMND
is cleared (return to hold mode)
hold after one instruction is finished.
C
o
n
00
PC.
ic
9.5.3.4
Function Description
SRAM program Instruction
Table 4 LED Effect Instruction
Command
15 14 13 12 11 10
9
8
JP
0
0
0
0
0
0
0
0
a
w
in
There are 27 commands in ASP instruction set, including LED control command, data operation and transfer
command, wait and branch control command. The Rx,Ry and Rz in instruction list means the internal register
RA, RB, RC and RD, each of them can participate the ALU operation as source or destination register.
NOP
0
0
0
0
0
0
0
1
-----
0
0
0
0
0
0
1
X
JPZ Addr
0
0
0
0
0
1
0
0
ADDR[7:0]
JPNZ Addr
0
0
0
0
0
1
0
1
ADDR[7:0]
JPS Addr
0
0
0
0
0
1
1
0
ADDR[7:0]
JPNS Addr
0
0
0
0
0
1
1
1
ADDR[7:0]
www.awinic.com.cn
16
7
6
5
4
3
2
1
0
-
-
-
ADDR[7:0]
-
-
-
-
-
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
0
0
0
0
1
0
Rz
Im[7:0]
CMPI Rz Im
0
0
0
0
1
1
Rz
Im[7:0]
ANDR Rz Im
0
0
0
1
0
0
Rz
Im[7:0]
ORR Rz Im
0
0
0
1
0
1
Rz
Im[7:0]
RDR Rz Addr
0
0
0
1
1
0
Rz
ADDR[7:0]
WDR Rz Addr
0
0
0
1
1
1
Rz
ADDR[7:0]
ADDI Rz Im
0
0
1
0
0
0
Rz
Im[7:0]
AUBI Rz Im
0
0
1
0
0
1
Rz
Im[7:0]
ADDR Rx Ry
0
0
1
0
1
0
Rz
-
-
-
-
SUBR Rx Ry
0
0
1
0
1
1
Rz
-
-
-
-
CMPR Rx Ry
0
0
1
1
0
0
0
0
-
-
-
-
----
0
0
1
1
0
0
X
X
END Int Rst
0
0
1
1
0
1
0
0
-
-
-
INTN_MASKOFF
0
0
1
1
0
1
1
0
-
-
INTN_MASKON
0
0
1
1
0
1
1
1
-
-
WAITI Pre Time
0
0
1
1
1 Pre
SETPWMR Rx Ry
0
1
0
0
0
0
RAMPR Dir Rx
0
1
0
0
0
0
SETSTEPTMRR Pre Rx Ry
0
1
0
0
0
1
SETSTEPTMRI Pre Ch Im
1
0
0
SETPWMI Ch Im
1
0
1
RAMPI Dir Ch Im
1
1 Dir
Ry
Rx
Ry
Rx
Ry
n
Rx
-
-
Int
Rst
-
-
-
-
-
-
-
-
-
-
-
-
fi
d
e
-
T[9:0]
-
-
0
0
0
Rx
Ry
1
Dir
-
0
0
0
Rx
Ry
0
-
Pre
0
0
0
Rx
Ry
Pre
-
n
0
o
Ch[4:0]
Im[5:0]
Ch[4:0]
Im[7:0]
Ch[4:0]
Im[7:0]
C
Ry
ti
a
LD Rz Im
l
Feb. 2019 V1.4
a) Special LED Control Command
There are 3 types of LED control command.
SETPWM:
RAMP：
SETSTEP:
set the brightness level (0~255)for specified LED channel;
set the specified LED channel fade in or fade out for expected step( 0~255)
set the fading slope for specified LED channel;
ic
-
in
All control parameter in above commands can either come from specified register (RA~RD), or from
immediate data contained in command..
All LED control command supports broadcast mode, one instruction may send to multiple or all LEDs
w
When SRAM program running, if Ch field or value of Rx in LED control command is ‘11111’, the current
command is active for all LED with setting of CTRSR.bitn=0. If Ch field or value of Rx in LED control
command is ‘11110’, the current command is only active for those channel with setting of GMSKx=0.
a
When LED instruction is come from I2C interface directly, it is recommended to use only the command with
immediate data. If the Ch field in command is “11111”, the current command is only active for those LED with
STRSR.bitn=1..
Table 5 LED Control Instruction explanation
Instruction
www.awinic.com.cn
Description
17
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Register Parameter
SETPWMR
Set the Fade-in/Fade-out for specified step with parameter in
register
Dir: 1: Fade-in; 0: Fade-out
Rx: LED channel number, 2~10 for LED 1~ LED 9 respectively
Ry: the step number of Fade-in/Fade-out
Dir Rx Ry
SETSTEPTMRR
ti
a
l
RAMPR
Set the PWM brightness level with parameter in register
Rx: LED channel number, 2~10 for LED 1~ LED 9 respectively
Ry: Brightness level, 0~255
Rx Ry
Set the RAMP slope with parameter in register
Pre: basic time unit, 0: 0.5ms; 1: 16ms
Rx: LED channel number, 2~10 for LED 1~ LED 9 respectively
Ry: RAMP step time = (Ry+1)*Pre
Pre Rx Ry
n
Immediate Data
Set the PWM brightness level with immediate parameter
Ch: LED channel number, 2~10 for LED 1~ LED 9 respectively
Im: Brightness level, 0~255
RAMPI Dir Ch Im
Set the Fade-in/Fade-out for specified steps with immediate
parameter
Dir: 1: Fade-in; 0: Fade-out
Ch: LED channel number, 2~10 for LED 1~ LED 9 respectively
Im: the steps of Fade-in/Fade-out
SETSTEPTMRI
Set the RAMP step time with immediate parameter
Pre: basic unit of time, 0: 0.5ms; 1: 16ms
Ch: LED channel number, 2~10 for LED 1~ LED 9 respectively
Im: RAMP step time = (Im +1)*Pre, 0~63
fi
d
e
SETPWMI Ch Im
a
w
in
ic
C
o
n
Pre Ch Im
www.awinic.com.cn
18
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Table 6 Program Control and operation Instruction
Instruction
Encoding
Description
Addr
0x00xx
Immediate Jump, jump to PC = Addr
Addr
0x04xx
Conditional Jump, If Rz is 0, jump to PC = Addr
JPNZ Addr
0x05xx
Conditional Jump, If Rz is not 0, jump to PC = Addr
JPS
Addr
0x06xx
Conditional Jump, If Rz < 0, jump to PC = Addr
JPNS Addr
0x07xx
Conditional Jump, If Rz >= 0, jump to PC = Addr
JPZ
0x08xx
0x0bxx
Rz = Im
RDR Rz Addr
0x18xx
0x1bxx
Rz = *Addr
WDR Rz Addr
0x1cxx
0x1fxx
*Addr = Rz
n
Computation Instruction
fi
d
LD Rz Im
e
n
Data Transfer Instruction
ti
a
JP
l
branch Instruction
0x0cxx
0x0fxx
Rz – Im, only change S/Z flag
CMPR Rx Ry
0x30xx
Rx – Ry, only change S/Z flag
ANDR Rz Im
0x10xx
0x13xx
C
o
CMPI Rz Im
ic
Rz = Rz & Im, affect S/Z flag
0x14xx
0x17xx
Rz = Rz | Im, affect S/Z flag
0x20xx
0x23xx
Rz = Rz + Im, affect S/Z flag
SUBI Rz Im
0x24xx
0x27xx
Rz = Rz - Im, affect S/Z flag
ADDR Rz Rx Ry
0x28xx
0x2bxx
Rz = Rz + Ry, affect S/Z flag
SUBR Rz Rx Ry
0x28xx
0x2bxx
Rz = Rz - Ry, affect S/Z flag
0x34xx
Program end with optionally reset register RMD and generate
in
ORR Rz Im
a
w
ADDI Rz Im
Control Instruction
END Int Rst
www.awinic.com.cn
19
interrupt
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Int= 0: no interrupt after instruction executed;
Int= 1: generate interrupt after instruction executed
Rst=0: PC add 1 after instruction executed;
Rst=1: Reload PC with SADDR after instruction executed
0x36xx
Unmask internal interrupt
INTN_MASKON
0x37xx
Mask internal interrupt
WAITI Pre Time
0x38xx
0x3fxx
Wait for specified time
Pre: time of basic waiting cycle, 0: 0.5ms; 1: 16ms
Time: number of waiting cycle, max value is 1023, wait time=Pre*Time
ti
a
9.6.3.5
l
INTN_MASKOFF
Example
n
PWM Value
255
256
384
512
640
768
Figure 16
896
Time (ms)
1024 1152 1280 1408 1536 1664 1792 1920 2048 2176
fi
d
128
e
LED1
128
LED Effect Programming Diagram
Table 7 Reference Instruction of LED Effect Programming
Machine Code
explanation
0
SETSTEPTMRI 0x00 0x1F 0x03
0x9F03
RAMPI step time: 2ms
1
SETPWMI 0x1F 0x00
0xBF00
ALL LED turn off
C
START:
n
Assemble Instruction
o
PC
Address Label “START” (01H)
RAMPI 0x01 0x02 0x80
0xE280
LED1 fade in, 128 steps breath
3
WAITI 0x01 0x20
0x3C20
Wait 512ms
4
RAMPI 0x00 0x02 0x80
0xC280
LED1 fade out, 128 steps breath
5
WAITI 0x01 0x38
0x3C38
Wait 896ms
6
JP START
0x0002
Jump to START, PC=2
ic
2
in
Step1: Power On, configure register
a
w
VBAT power on, 4.2V
Pull PDN to 3V
Wait 5ms
GCR = 0x0001
LER = 0x0004
IMAX1 = 0x0100
PMD.PROGRMD = 00
RMD.RUNMD = 00
Step2: Load Instruction to SRAM
WADDR = 0x0000
WDATA = 0x9F03
WDATA = 0xBF00
WDATA = 0xE280
WDATA = 0x3C20
WDATA = 0xC280
www.awinic.com.cn
// enable LED module
// enable LED1
// IMAX1 = 3.5mA
//hold mode
//hold mode
// load program starting at address =0x0000
20
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
WDATA = 0x3C38
WDATA = 0x0002
Step3: Run
SADDR = 0x0000
RMD.RUNMD = 10
PMD.PROGMD = 01
// execution mode change to run mode,
// start program from 0x0000
a
w
in
ic
C
o
n
fi
d
e
n
ti
a
l
www.awinic.com.cn
21
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
REGISTER DESCRIPTION
REGISTER CONFIGURATION
14
D14
0
0
13
D13
0
0
12
D12
0
0
11
D11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IMAX2
IMAX6
0
0
0
0
0
TIER
TIVEC
ISR2
SADDR
0
0
0
0
0
0
0
0
0
0
0
0
0x60
PCR
0
0
0
0x61
0x62
0x63
0x64
0x65
0x66
~
0x6D
6E
7D
7E
7F
CMDR
RA
RB
RC
RD
R1
~
R8
GRPR
WP
WADDR
WDATA
D15
0
0
0
0
D14
0
0
0
0
D13
0
0
0
0
0
0
0
-
ic
in
w
a
www.awinic.com.cn
0
0
0
0
10
9
D10
D9
0
0
LED9 LED8
0
0
0
CS9
0
0
0
0
8
7
6
5
4
D8
D7
D6
D5
D4
0
0
0
0
0
LED7 LE6
LE5
LE4
LE3
RESERVED
0
SRMINI
LIRMD
TIMD
0
0
0
0
0
0
0
0
0
0
0
0
CS8
CS7
CS6
CS5
CS4
CS3
RESERVED
IMAX1
0
IMAX5
0
IMAX4
IMAX9
0
IMAX8
n
15
D15
0
0
fi
d
e
Register
IDRST
GCR
LER
LCR
PROGMD
RUNMD
CTRS
IMAX1
IMAX2
IMAX3
n
Address
0x00
0x01
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5a
0x5B
0x5C
0x5D
0x5E
0x5F
o
10.1
TIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D12
0
0
0
0
D11
0
0
0
0
D10
0
0
0
0
D9
0
0
0
0
D8
0
0
0
0
D7
D6
D5
0
GS9
GS8
GS7
GS6
0
GS5
0
GS4
0
0
0
0
0
0
0
WPW
0
0
22
3
D3
0
LE2
2
D2
0
LE1
LIE
0
0
CS2
FREQ
0
0
CS1
1
D1
0
0
0
D0
LEDE
0
LOG/LIN
PROGMD
RUNMOD
0
0
0
IMAX3
IMAX7
0
0
RESERVED
0
0
0
0
C
10
ti
a
l
AW9109
Feb. 2019 V1.4
0
CODE
0
0
TIVEC
0
0
SADDR
PC
D4
D3
RA
RB
RC
RD
R1
~
R8
GS3 GS2`
0
0
ADDR
0
0
KIE
0
0
LIS
D2
D1
D0
GS1
0
D1
0
D0
0
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
10.2
GLOBAL REGISTER DESCRIPTION
10.2.1
IDRST, Chip ID and Software Reset
10.2.2
GCR, Global Control Register
Address: 0x01, R/W, default: 0x0000
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
Bit
Symbol Description
0
LEDE
LED driver function
0: disable LED driver (default)
1: enable LED driver
6
0
5
0
4
0
3
0
1
D1
0
D0
2
0
1
0
0
LEDE
10.3
LED Effect Control Register
10.3.1
LER1, LED Driver Enable Register
fi
d
e
n
7
0
2
D2
l
12
11
10
9
8
7
6
5
4
3
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
Description
Chip ID: 0xB223
Software Reset: write 0x55AA to IDRST, reset the whole device.
ti
a
Address: 0x00, R/W
15
14
13
D15 D14
D13
Bit
Symbol
15:0 IDRST
6
LE5
5
LE4
4
LE3
3
LE2
2
LE1
1
0
0
0
10.3.2
C
o
n
Address: 0x50, R/W, default: 0x0000
15
14
13
12
11 10
9
8
7
0
0
0
0
0 LE9 LE8 LE7 LE6
Bit
Symbol
Description
1:0
Reserved, must be 0
10:2
LEx
LED output enable
0: disable
1: enable
15:11
Reserved, must be 0
LCR, LED Effect Configuration Register
a
w
in
ic
Address: 0x52, R/W, default: 0x0080
15
14
13
12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SRMINI
LIRMD
0
LIE
FREQ
LOGLIN
Bit
Symbol
Description
1:0
Log/Lin
Log/Linear dimming mode selection
00: log dimming 1, log(e) （default）
01: log dimming 2, log10
1x: linear dimming
2
FREQ
PWM frequency selection
0: 250Hz （default）
1: 125Hz
3
LIE
LED program end interrupt enable
0: disable interrupt（default）
1: enable interrupt
5:4
Reserved
7:6
LIRMD
LED effect code run mode after responding to interrupt request
00: hold mode, PC point can be changed, program hold and wait for RMD.RUNMD
01: step mode
10: run mode (default)
8
SRMINI
SRAM reset bit, write 1, reset SRAM; read SRAM status, default is 0.
10.3.3
PMD, Program Mode Register
Address: 0x53, R/W, default: 0x0000
15
14
13
12
11
10
9
www.awinic.com.cn
8
23
7
6
5
4
3
2
1
0
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
0
0
Symbol
PROGMD
0
0
0
0
0
0
0
0
0
0
0
PROGMD
Description
Program control mode
00: load program via I2C interface (default)
01: re-load program and execute. When write 01 to PROGMD[1:0], set PC pointer will
be updated with SADDR, then start to run program, and finally PROGMD[1:0] is
changed to 10 automatically
10: run program. Under this mode, the control bit RUNMD in register RMD can
configure different program running mode for normal operation or debug.
11: undefined
10.3.4
ti
a
l
0
Bit
1:0
RMD, Program Run Mode Register
10.3.5
fi
d
e
n
Address: 0x54, R/W, default: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RUNMD
Bit
Symbol
Description
1:0
RUNMD
SRAM program run mode, only active for these LED set with CTRSR.CSx=0
00: hold mode, program stop and hold PC pointer (default)
01: step mode, RUNMD reset, PC+1 after the current program executed
10: run mode, normal program run
11: repeat mode, RUNMD reset, PC hold after the current program executed
CTRSR, LED Control Source Selection Register
3
CS2
2
CS1
1
0
0
0
IMAX1～IMAX6, LEDx Maximum Output Current Register
C
10.3.6
o
n
Address: 0x55, R/W, default: 0x0000
15
14
13 12 11
10
9
8
7
6
5
4
0
0
0
0
CS9 CS8 CS7 CS6 CS5 CS4 CS3
Bit
Symbol
Description
7:2
CSx
LED control source
0: LEDx controlled by SRAM program
1: LEDx controlled by external MCU via I2C interface
6
5
IMAX4
IMAX8
4
0
3
0
2
1
0
IMAX3
IMAX7
w
in
ic
Address: 0x57~0x59, R/W, default: 0x0000
15
14
13
12
11
10
9
8
7
0
IMAX2
0
IMAX1
0
IMAX6
0
IMAX5
0
0
0
0
0
IMAX9
Bit
Symbol
Description
10:8
IMAX1
LEDx maximum output current selection
14:12
IMAX2
000: 0mA (default)
2:0
IMAX3
001: 3.5mA
6:4
IMAX4
010: 7.0mA
10:8
IMAX5
011: 10.5mA
14:12
IMAX6
100: 14.0mA
2:0
IMAX7
101: 17.5mA
6:4
IMAX8
110: 21.0mA
10:8
IMAX9
111: 24.5mA
LISR, LED Interrupt Status Register
a
10.3.7
Address: 0x5E, R(clear by reading), default: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LIS
Bit
Symbol
Description
1
LIS
LED program end interrupt status, set by END instruction with parameter int=1, used for
inform external MCU that program has finished. LCR.LIE is the enable bit for LIS.
0: no interrupt
1: interrupt request
www.awinic.com.cn
24
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
10.3.8
SADDR, Program Start Address Register
Address: 0x5F, R/W, default: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
SADDR
Bit
Symbol
Description
7:0
SADDR
SRAM program starting address. For reload and run mode,
PMD.PROGMD=10, program will jump to PC=SADDR and run again.
if
PCR, LED Program Control Pointer Register
0
setting
l
10.3.9
1
CMDR, LED Command Register
Address: 0x61, R/W, default: 0x0000
15
14
13
12
11
10
7
CMD
6
5
4
3
2
1
0
fi
d
10.3.11
8
Symbol
CMD
Description
External controlled Command. used to send external LED command which is only
active for those LED configured with control bit CTRSR.CSx=1. The external
controlled command adapted the same instruction with internal ASP.
RA/RB/RC/RD,LED Internal Program Register
n
Bit
15:0
9
e
10.3.10
n
ti
a
Address: 0x60, R/W, default: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PC
Bit
Symbol
Description
7:0
PC
SRAM program pointer(PC), can be written by I2C interface.
For normal program execution, set the PC pointer at PMD.PROGMD= 00 mode at first,
and then write PMD.PROGMD with 10.
2
1
0
10.3.12
ic
C
o
Address: 0x62~0x65, R, default: 0x0000
15 14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
RA
0
0
0
0
0
0
0
0
RB
0
0
0
0
0
0
0
0
RC
0
0
0
0
0
0
0
0
RD
Bit
Symbol
Description
7:0 RA/RB/RC/RD LED internal program register, read only, for debug usage.
R1~R8, LED Internal Data Register
5
4
3
R1
R2
R3
R4
R5
R6
R7
R8
2
1
0
a
w
in
Address: 0x66~0x6D, R, default: 0x0000
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Description
7:0
LED internal data register, for debug usage.
R1～R8
10.3.13
GRP, LED Group Operation Register
Address: 0x6E, R, default: 0x0000
15
14
13
12
11
10
0
0
0
0
0
GS9
Bit
Symbol
Description
www.awinic.com.cn
9
GS8
25
8
GS7
7
GS6
6
GS5
5
GS4
4
GS3
3
GS2
2
GS1
1
0
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
GS[8:0]
WADDR, LED Program Loading Address Register
Address: 0x7E, R/W, default: 0x0000
15 14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
Bit Symbol
Description
7:0 ADDR
SRAM address for program access via I2C interface
10.3.16
2
WDATA, LED Program Loading Data Register
Address: 0x7F, R/W, default: 0x0000
15
14
13
12
11
10
Symbol
CODE
9
8
7
CODE
6
5
1
0
4
Description
SARM data for program access via I2C interface
3
2
1
0
n
Bit
15:0
3
ADDR
e
10.3.15
4
l
10.3.14
LED channel selection for external group control command.
GS[n]=0, LEDn is not included in external LED command with chan=0x1E;
GS[n]=1, LEDn is included in external LED command with chan=0x1E;
ti
a
10:2
WPR, Writing Protection Register
a
w
in
ic
C
o
n
fi
d
Address: 0x7D, R/W, default: 0x5500
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WPW
0
0
0
0
0
0
0
0
Bit
Symbol Description
15:8
WPW
writing protection control, If WPW=0x55, all register is writable, otherwise all register
except for WPR is not allowed to be written.
www.awinic.com.cn
26
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
11
TAPE AND REEL INFORMATION
Carrier Tape（All Dimensions are in Millimeters）
11.2
PIN1 Direction
ic
C
o
n
fi
d
e
n
ti
a
l
11.1
a
w
in
User Direction of Feed
www.awinic.com.cn
27
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
Reel
fi
d
e
n
ti
a
l
11.3
Notes:
n
Material: polystyrene
Flatness: maximum permissible 3mm
All dimensions are in millimeters
Surface resistivity: 105 to 1011 ohms/sq or less
All unmarked tolerance: ±0.5
a
w
in
ic
C
o
i.
ii.
iii.
iv.
v.
www.awinic.com.cn
28
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
12
PACKAGE DESCRIPTION
PIN 1# DOT
BY MARKING
1.650±0.050
Exp.DAP
3.000±0.050
PIN 1# IDENTIFICATION
CHAMFER C0.300x45º
TQFN-20L
(3 X 3mm)
1.650±0.050
Exp.DAP
ti
a
3.000±0.050
0.400 Bsc
1.600
Ref.
Note: All Dimensions are in Millimeters
fi
d
e
BOTTOM VIEW
n
0.200±0.050
TOP VIEW
0.750±0.050
n
0.000-0.050
0.203 Ref.
SIDE VIEW
RECOMMENDED LAND PATTERN
C
o
13
l
0.400±0.050
ic
0.3
0.3
4X(0.825)
20X(0.5)
a
w
in
4X(1.1)
20X(0.2)
16X(0.4)
TOP VIEW
Note：All Dimensions are in Millimeters
www.awinic.com.cn
29
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
REFLOW
Reflow Note
Average ramp-up rate (217°C to peak)
n
fi
d
e
n
ti
a
l
14
Spec
Max. 3°C /sec
60-120sec
Time to be maintained above 217°C
60-150sec
C
o
Time of Preheat temp. (from 150°C to 200°C)
>260°C
Time within 5°C of actual peak temp
20-40sec
Ramp-down rate
Max. 6°C /sec
ic
Peak Temperature
Time from 25°C to peak temp
Max. 8min
in
Package Reflow Standard Profile
NOTE 1: All data are compared with the package-top temperature, measured on the package surface;
a
w
NOTE 2: AW9109 adopted the Pb-Free assembly.
www.awinic.com.cn
30
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
REVISION HISTORY
Date
Change Record
V1.0
Sept. 2017
V1.1
June. 2018
V1.2
Sep. 2018
Officially Released
Update the ordering information
Add the recommended land pattern
Update the electrical characteristics
Update the reflow information
Update the storage temperature
V1.3
Nov. 2018
Update document description of AW9109
V1.4
Feb. 2019
Add power on procedure
ti
a
l
Vision
a
w
in
ic
C
o
n
fi
d
e
n
15
www.awinic.com.cn
31
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9109
Feb. 2019 V1.4
16
DISCLAIMER
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of use of such
information.
ti
a
l
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
e
n
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC
Technology products in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
fi
d
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
o
n
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
C
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
a
w
in
ic
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
www.awinic.com.cn
32
Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD
工商网监
湘ICP备2023018690号
