STL140N4F7AG

STL140N4F7AG Automotive-grade N-channel 40 V, 2.1 mΩ typ., 120 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 package Datasheet - production data Features       Order code VDS RDS(on) max ID STL140N4F7AG 40 V 2.5 mΩ 120 A AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Wettable flank package Applications Figure 1: Internal schematic diagram  Switching applications Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code STL140N4F7AG February 2017 Marking Package 140N4F7 TM PowerFLAT DocID028588 Rev 2 This is information on a product in full production. Packaging 5x6 Tape and reel 1/14 www.st.com Contents STL140N4F7AG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 5 3 Test circuits ..................................................................................... 7 4 Package information ....................................................................... 8 5 2/14 4.1 PowerFLAT™ 5x6 package information ............................................ 8 4.2 PowerFLAT™ 5x6 packing information ........................................... 11 Revision history ............................................................................ 13 DocID028588 Rev 2 STL140N4F7AG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at TC = 25 °C 120 A ID(1) Drain current (continuous) at TC = 100 °C 120 A IDM(2) Drain current (pulsed) 480 A Total dissipation at TC = 25 °C 111 W IAV Avalanche current, repetitive (pulse width limited by maximum junction temperature) 16 A EAS Single pulse avalanche energy (Tj= 25 °C, ID= IAV, VDD= 25 V) 260 mJ Tstg Storage temperature range -55 to 175 °C Value Unit Thermal resistance junction-pcb max. 31.3 °C/W Thermal resistance junction-case max. 1.35 °C/W PTOT (1) Tj Operating junction temperature range Notes: (1)Drain current is limited by package, the current capability of the silicon is 178 A at 25 °C. (2)Pulse width is limited by safe operating area. Table 3: Thermal data Symbol Rthj-pcb (1) Rthj-case Parameter Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s DocID028588 Rev 2 3/14 Electrical characteristics 2 STL140N4F7AG Electrical characteristics (TC = 25 °C unless otherwise specified). Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID= 250 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 40 V IGSS Gate-body leakage current VGS = 20 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 16 A Min. Typ. Max. Unit V 40 1 µA 100 nA 4 V 2.1 2.5 mΩ Min. Typ. Max. Unit - 2300 - pF - 786 - pF - 43 - pF - 29 - nC - 13 - nC - 5.6 - nC Min. Typ. Max. Unit - 14 - ns - 6.6 - ns - 19 - ns - 5.7 - ns Min. Typ. Max. Unit 1.2 V 2 Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS= 0 V Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 20 V, ID = 32 A, VGS = 0 to 10 V (see Figure 14: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 20 V, ID = 16 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") Rise time Turn-off delay time Fall time Table 7: Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 32 A, VGS = 0 V - trr Reverse recovery time - 55 ns Qrr Reverse recovery charge - 67 nC IRRM Reverse recovery current ID = 32 A, di/dt = 100 A/µs, VDD = 32 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 2.4 A Notes: (1)Pulsed: 4/14 pulse duration = 300 µs, duty cycle 1.5% DocID028588 Rev 2 STL140N4F7AG 2.1 Electrical characteristics Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028588 Rev 2 5/14 Electrical characteristics STL140N4F7AG Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics 6/14 DocID028588 Rev 2 STL140N4F7AG 3 Test circuits Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID028588 Rev 2 7/14 Package information 4 STL140N4F7AG Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 PowerFLAT™ 5x6 package information Figure 19: PowerFLAT™ 5x6 WF type C package outline 8231817_WF_typeC_r14 8/14 DocID028588 Rev 2 STL140N4F7AG Package information Table 8: PowerFLAT™ 5x6 WF type C mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 C 5.80 6.00 6.10 5.20 5.40 D 5.00 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.10 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 4.45 1.27 E 6.20 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.85 1.00 1.15 E9 4.00 4.20 4.40 E10 3.55 3.70 3.85 K 1.05 L 0.90 1.00 1.10 L1 0.175 0.275 0.375 θ 0° DocID028588 Rev 2 6.40 6.60 1.35 12° 9/14 Package information STL140N4F7AG Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_rev14 10/14 DocID028588 Rev 2 STL140N4F7AG 4.2 Package information PowerFLAT™ 5x6 packing information Figure 21: PowerFLAT™ 5x6 WF tape (dimensions are in mm) Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape DocID028588 Rev 2 11/14 Package information STL140N4F7AG Figure 23: PowerFLAT™ 5x6 reel (dimensions are in mm) 12/14 DocID028588 Rev 2 STL140N4F7AG 5 Revision history Revision history Table 9: Document revision history Date Revision 14-Jan-2015 1 First release 2 Updated package silhouette on cover page and Section 4: "Package information". Updated Table 2: "Absolute maximum ratings". Minor text changes 15-Feb-2017 Changes DocID028588 Rev 2 13/14 STL140N4F7AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 14/14 DocID028588 Rev 2