STD10NF10T4
N-channel 100 V, 0.115 Ω typ., 13 A STripFET™ II
Power MOSFET in a DPAK package
Datasheet - production data
Features
Order code
VDS
RDS(on) max.
ID
STD10NF10T4
100 V
0.130 Ω
13 A
Exceptional dv/dt capability
Application oriented characterization
Applications
Figure 1: Internal schematic diagram
Switching applications
Description
D(2, TAB)
This Power MOSFET series realized with
STMicroelectronics unique STripFET™ process
is specifically designed to minimize input
capacitance and gate charge. It is therefore ideal
as a primary switch in advanced high-efficiency
isolated DC-DC converters for Telecom and
Computer applications. It is also suitable for any
application with low gate charge drive
requirements.
G(1)
S(3)
AM01475v1_Tab
Table 1: Device summary
Order code
Marking
Package
Packing
STD10NF10T4
D10NF10
DPAK
Tape and reel
April 2016
DocID029150 Rev 1
This is information on a product in full production.
1/17
www.st.com
Contents
STD10NF10T4
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.2
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
5
2/17
4.1
DPAK (TO-252) type A package information..................................... 9
4.2
DPAK (TO-252) type C package information .................................. 11
4.3
Packing information ......................................................................... 14
Revision history ............................................................................ 16
DocID029150 Rev 1
STD10NF10T4
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
100
V
VDGR
Drain-gate voltage (RGS = 20 kΩ)
100
V
VGS
Gate-source voltage
±20
V
ID
Drain current (continuous) at TC = 25 °C
13
A
ID
Drain current (continuous) at TC = 100 °C
9
A
(1)
IDM
Drain current (pulsed)
52
A
PTOT
Total dissipation at TC = 25 °C
50
W
(2)
EAS
Single pulse avalanche energy
70
mJ
Peak diode recovery voltage slope
9
V/ns
- 55 to 175
°C
dv/dt
(3)
Tj
Operating junction temperature range
Tstg
Storage temperature range
Notes:
(1)
(2)
(3)
Pulse width limited by safe operating area.
Starting TJ = 25 °C, ID = 13 A, VDD = 50 V
ISD ≤ 13 A, di/dt ≤ 300 A/µs; VDS peak < V(BR)DSS, TJ ≤ TJMAX
Table 3: Thermal data
Symbol
Parameter
Rthj-case
Rthj-pcb
(1)
Value
Unit
Thermal resistance junction-case
3
°C/W
Thermal resistance junction-pcb
50
°C/W
Notes:
(1)
When mounted on 1 inch² FR-4, 2 Oz copper board
DocID029150 Rev 1
3/17
Electrical characteristics
2
STD10NF10T4
Electrical characteristics
TC = 25 ° C unless otherwise specified
Table 4: On/off-state
Symbol
Parameter
Test conditions
Min.
V(BR)DSS
Drain-source breakdown voltage
VGS = 0 V, ID = 250 µA
100
Typ.
Max.
Unit
V
VGS = 0 V, VDS = 100 V
1
µA
IDSS
Zero gate voltage drain current
VGS = 0 V, VDS = 100 V
(1)
TC = 125 °C
10
µA
IGSS
Gate body leakage current
VDS=0 V, VGS ±20 V
± 100
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
3
4
V
RDS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 5 A
0.115
0.130
Ω
Max.
Unit
2
Notes:
(1)
Defined by design, not subject to production test.
Table 5: Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
Test conditions
Min.
Typ.
-
460
pF
-
70
pF
-
30
pF
-
15.3
-
3.7
nC
-
4.7
nC
Test conditions
Min.
Typ.
Max.
Unit
VDD= 50 V, ID = 5 A, RG = 4.7 Ω
VGS = 10 V
(see Figure 13: "Test circuit for
resistive load switching times")
-
16
-
ns
-
25
-
ns
-
32
-
ns
-
8
-
ns
VDS = 25 V, f = 1 MHz,
VGS = 0 V
VDD = 80 V, ID = 10 A
VGS= 10 V
(see Figure 14: "Test circuit
for gate charge behavior" )
21
(1)
nC
Notes:
(1)
Defined by design, not subject to production test.
Table 6: Switching times
Symbol
td(on)
tr
td(off)
tf
4/17
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
DocID029150 Rev 1
STD10NF10T4
Electrical characteristics
Table 7: Source-drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain
current
-
13
A
(1)
Source-drain
current (pulsed)
-
52
A
(2)
Forward on
voltage
ISD = 10 A, VGS = 0 V
-
1.5
V
trr
Reverse recovery
time
ISD = 10 A, di/dt = 100 A/µs,
-
90
ns
Qrr
Reverse recovery
charge
-
230
nC
IRRM
Reverse recovery
current
VDD = 50 V, Tj = 150 °C
(see Figure 15: "Test circuit for
inductive load switching and diode
recovery times")
-
5
A
ISD
ISDM
VSD
Notes:
(1)
(2)
Pulse width limited by safe operating area
Pulsed: pulse duration = 300 µ s, duty cycle 1.5%
DocID029150 Rev 1
5/17
Electrical characteristics
2.2
STD10NF10T4
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
9
Figure 6: Gate charge vs gate-source voltage
6/17
Figure 7: Static drain-source on-resistance
DocID029150 Rev 1
STD10NF10T4
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Source-drain diode forward characteristics
DocID029150 Rev 1
7/17
Test circuits
3
8/17
STD10NF10T4
Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID029150 Rev 1
STD10NF10T4
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
4.1
DPAK (TO-252) type A package information
Figure 19: DPAK (TO-252) type A package outline
0068772_A_21
DocID029150 Rev 1
9/17
Package information
STD10NF10T4
Table 8: DPAK (TO-252) type A mechanical data
mm
Dim.
Min.
Max.
A
2.20
2.40
A1
0.90
1.10
A2
0.03
0.23
b
0.64
0.90
b4
5.20
5.40
c
0.45
0.60
c2
0.48
0.60
D
6.00
6.20
D1
4.95
E
6.40
E1
4.60
4.70
4.80
e
2.16
2.28
2.40
e1
4.40
4.60
H
9.35
10.10
L
1.00
1.50
(L1)
2.60
2.80
3.00
L2
0.65
0.80
0.95
L4
0.60
R
V2
10/17
Typ.
5.10
5.25
6.60
1.00
0.20
0°
DocID029150 Rev 1
8°
STD10NF10T4
4.2
Package information
DPAK (TO-252) type C package information
Figure 20: DPAK (TO-252) type C package outline
0068772_C_21
DocID029150 Rev 1
11/17
Package information
STD10NF10T4
Table 9: DPAK (TO-252) type C mechanical data
mm
Dim.
Min.
Typ.
Max.
A
2.20
2.30
2.38
A1
0.90
1.01
1.10
A2
0.00
0.10
b
0.72
0.85
b4
5.13
5.46
c
0.47
0.60
c2
0.47
0.60
D
6.00
D1
5.25
E
6.50
E1
4.70
e
6.10
6.20
6.60
6.70
2.186
2.286
2.386
H
9.80
10.10
10.40
L
1.40
1.50
1.70
L1
L2
2.90 REF
0.90
L3
L4
1.25
0.51 BSC
0.60
L6
12/17
5.33
0.80
1.00
1.80 BSC
θ1
5°
7°
9°
θ2
5°
7°
9°
V2
0°
DocID029150 Rev 1
8°
STD10NF10T4
Package information
Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_21
DocID029150 Rev 1
13/17
Package information
4.3
STD10NF10T4
Packing information
Figure 22: DPAK (TO-252) tape outline
14/17
DocID029150 Rev 1
STD10NF10T4
Package information
Figure 23: DPAK (TO-252) reel outline
Table 10: DPAK (TO-252) tape and reel mechanical data
Tape
Reel
mm
mm
Dim.
Dim.
Min.
Max.
A0
6.8
7
A
B0
10.4
10.6
B
1.5
12.1
C
12.8
B1
D
1.5
D1
1.5
E
1.65
F
1.6
Min.
Max.
330
13.2
D
20.2
G
16.4
1.85
N
50
7.4
7.6
T
K0
2.55
2.75
P0
3.9
4.1
Base qty.
2500
P1
7.9
8.1
Bulk qty.
2500
P2
1.9
2.1
R
40
T
0.25
0.35
W
15.7
16.3
DocID029150 Rev 1
18.4
22.4
15/17
Revision history
5
STD10NF10T4
Revision history
Table 11: Document revision history
16/17
Date
Revision
06-Apr-2016
1
DocID029150 Rev 1
Changes
First release.
STD10NF10T4
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
DocID029150 Rev 1
17/17
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